NON-FINAL REJECTION
DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 2, 2026 has been entered.
Response to Amendment
The Amendment filed February 2, 2026 has been entered. Claims 1-5, 7-12, and 14-20 remain pending in the application. Claims 6 and 13 have been cancelled. Applicant's amendments to the claims have overcome the objections and the 35 U.S.C. rejections previously set forth in the Final Office Action mailed November 3, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 7-12, and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 6-11, and 13-17 of U.S. Patent No. 11,880,600. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are anticipated by at least one claim set of each of the listed patents above as discussed in the Non-Final Office Action mailed June 4, 2025.
In the event that any claim is not completely anticipated by at least one claim of a patent
above, the claims would still be rejected on the grounds of obvious nonstatutory double
patenting in further view of the prior art below that teaches or makes obvious that missing part,
and one of ordinary skill in the art could have incorporated such teachings prior to the effective
filings date of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Riedle (US 6,298,415), Eckert et al. (US 2015/0067264), and Lee (US 2016/0196216).
Regarding claim 1, Riedle discloses:
A system comprising:
a non-volatile memory device (Fig. 1 Disk Drive System 40, 42, 44);
a volatile memory device (Fig. 1 Cache 28; Col 5, lines 32-39: A cache 28 is also provided which is coupled to DRAM/XOR controller 30. Cache 28 may be configured into a plurality of temporary storage positions for data. DRAM/XOR controller 30 is utilized to control access to random access memory and also provides a hardware implemented exclusive or (XOR) circuit which may be utilized to rapidly and efficiently calculate parity for changes in updated data); and
a processing device, operatively coupled with the non-volatile memory device and the volatile memory device (Fig. 1 Processor 14; Col 5, line 4-6: processor 14 is utilized to control data storage system 10 which is preferably a RAID data storage system; Col 5, line 17-21: Operational code is thereafter fetched from ROM 22 by processor 14 upon initiation of operation to direct the operation of processor 14 to perform functions including the functions of the present invention), to perform operations comprising:
receiving a write request directed to the non-volatile memory device (FIG. 4 step 90 Update data),…
determining whether a stripe associated with…the write request is present in the volatile memory device (FIG. 4 step 96 Is dirty data a contiguous stripe unit of data?; Col 7, lines 1-3: Block 96 depicts a determination of whether or not the dirty data page to be handled correlates with a contiguous stripe unit of dirty data present within the cache)…wherein the volatile memory device includes a plurality of stripes, each stripe comprising a plurality of managed units (Col 3, lines 4-8: the cache may include sufficient pages of data to completely update at least one stripe or may include pages of data to update stripe units of multiple stripes. Pages of data may include all sectors for a stripe unit or an assortment of sectors for a stripe unit);
…determining whether the stripe is full, wherein the stripe is full when each managed unit of the stripe contains data (FIG. 4 step 100 Is a contiguous stripe of pages of data in cache including data to be handles? Yes; Col 7, line 5-7: Block 100 illustrates a determination of whether or not there is a contiguous stripe of contiguous pages of data present within the cache, including the dirty data page, to be handled);
responsive to determining that the stripe is full, copying, from the stripe in the volatile memory device, the data in each managed unit of the stripe to a managed unit of a corresponding fault tolerant stripe in the non-volatile memory device (Fig. 4 step 122 Writing the pages of dirty data and calculated parity to the data storage drives; Col 3, line 63-Col 4, line 4: An associated cache is provided with the data storage system into which data is received. The data in the cache is periodically examined to determine if the cache includes all sequential data sectors contained within a complete stripe within the data storage system. Parity is calculated for the complete stripe by first calculating a range of sectors between which all sectors received into the cache for the complete stripe fall);
…and; storing, in the corresponding fault tolerant stripe in the non-volatile memory device, the redundancy metadata (Fig. 4 step 122 …and calculated parity to the data storage drives).
Riedle do not appear to explicitly teach “the write request comprising an address;” determining whether a stripe is “associated with the address specified” by the write request is present in the volatile memory device “by obtaining, from the address, stripe information identifying the stripe and a managed unit index identifying a managed unit within the stripe, and comparing the stripe information with a plurality of stripes stored in the volatile memory device,…responsive to determining that the stripe associated with the write request is present in the volatile memory device, performing the write request on the managed unit of the stripe identified by the managed unit index…calculating, after the data in each managed unit of the stripe is copied to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device, a redundancy metadata using the data in the corresponding fault tolerant stripe in the non-volatile memory device.” However, Eckert et al. disclose:
the write request comprising an address ([0027] The memory access request specifies an address);
[determining whether a stripe] associated with the address specified [by the write request is present in the volatile memory device] by obtaining, from the address, stripe information identifying the stripe and a managed unit index identifying a managed unit within the stripe, and comparing the stripe information with a plurality of stripes stored in the volatile memory device ([0027] Addresses for information cached in respective cache lines 216 in the cache data array 214 are divided into multiple portions, including an index and a tag. Cache lines 216 are installed in the cache data array 214 at locations indexed by the index portions of the addresses, and tags are stored in the cache tag array 212 at locations indexed by the index portions of the addresses. (A cache line 216 may correspond to a plurality of addresses that share common index and tag portions.)…To perform a memory access operation in the cache memory 200, a memory access request is provided to the cache controller 202 (e.g., from a processor core 104-0 or 104-1, FIG. 1). The memory access request specifies an address. If a tag stored at a location in the cache tag array 212 indexed by the index portion of the specified address matches the tag portion of the specified address, then a cache hit occurs…For a write request that results in a cache hit, the cache line 216 at the corresponding location in the cache data array 214 is modified); FIG. 2),…
responsive to determining that the stripe associated with the write request is present in the volatile memory device, performing the write request on the managed unit of the stripe identified by the managed unit index ([0027] For a write request that results in a cache hit, the cache line 216 at the corresponding location in the cache data array 214 is modified);
Riedle and Eckert et al. are analogous art because Riedle and Lee teaches RAID memory systems and Eckert et al. teach cache memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Riedle and Eckert et al. before him/her, to modify the teachings of Riedle with the teachings of Eckert et al. because specifying the address of the access request enables the determination of whether there is a cache hit for the associated line.
Riedle and Eckert et al. do not appear to explicitly teach “calculating, after the data in each managed unit of the stripe is copied to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device, a redundancy metadata using the data in the corresponding fault tolerant stripe in the non-volatile memory device.” However, Lee discloses:
calculating, after the data in each managed unit of the stripe is copied to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device, a redundancy metadata using the data in the corresponding fault tolerant stripe in the non-volatile memory device ([0193] After sequentially writing data to the first through (N-1)th SSDs 1300-1 through 1300-(N-1), defining one stripe, in the above-described manner, the RAID controller 1100B calculates parity information about the data that is stored in the NVRAM 1500 and defines one stripe, and writes the calculated parity information to a memory block #1 of the N-th SSDN 1300-N; Note that the data in the NVRAM is the same data that has been written to the SSDs (see FIG. 12C));
Riedle, Eckert et al., and Lee are analogous art because Riedle and Lee teach RAID memory systems and Eckert et al. teach cache memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Riedle, Eckert et al., and Lee before him/her, to modify the combined teachings of Riedle and Eckert et al. with the teachings of Lee. Riedle’s teaches concurrently writing the pages of dirty data and calculating parity to the data storage drives and Lee teaches calculating parity after data is written to the stripe in the non-volatile memory device. The modification would decrease the required size of volatile memory.
Regarding claim 2, Riedle further discloses:
The system of claim 1, wherein the redundancy metadata reflects an XOR parity of the corresponding fault tolerant stripe (Fig. 4 step 120).
Regarding claim 3, Eckert et al. further disclose:
The system of claim 1, wherein the plurality of stripes are stored in a content addressable memory of the volatile memory device (FIG. 4A; [0039] the group definition table 302 may be implemented using a content-addressable memory that stores a portion of the address bits in the tag. Each entry in the content-addressable memory corresponds to a distinct cache line 216. Entries with matching stored portions of the tag are assumed to correspond to cache lines 216 in the same page. To identify all of the cache lines 216 for a particular page, the tag portion for the page is provided to the content-addressable memory as a search key. All entries in the content-addressable memory that match the search key are considered to point to cache lines 216 in the same page).
Regarding claim 4, Riedle further discloses:
The system of claim 1, wherein a size of the stripe in the volatile memory device and a size of the corresponding fault tolerant stripe in the non-volatile memory device are equivalent in size (Col 3, lines 4-8: dirty data in the cache may include sufficient pages of data to completely update at least one stripe or may include pages of data to update stripe units of multiple stripes. Pages of data may include all sectors for a stripe unit or an assortment of sectors for a stripe unit; Fig. 4 step 122; Col 7, lines 27-30: Block 122 illustrates the writing of the dirty data pages and the calculated parity from the cache to the data storage drives).
Regarding claim 5, Eckert et al. further disclose:
The system of claim 1, wherein copying the data in each managed unit of the stripe to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device comprises:
copying the data in each managed unit of the stripe into a buffer queue (FIG. 2 Write-Back Buffer 218; [0030] If write-back is to be performed (e.g., because the evicted cache line 216 is modified or because the cache memory 200 is non-inclusive with respect to a lower-level cache memory), the evicted cache line is placed in a write-back buffer 218); and
copying the data in each managed unit of the stripe from the buffer queue into the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device (One of ordinary skill in the art recognizes that evicted cache lines with modified data are written to memory (i.e., the disk drive system of Riedle). Therefore, it would be obvious to one skilled in the art before the effective filing date of the claimed invention that the evicted cache line with modified data placed in the write-back buffer is written back to the non-volatile memory device).
Regarding claim 7, Riedle further discloses:
The system of claim 1, wherein copying the data in each managed unit of the stripe to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device is in response to determining that the stripe is full (Fig. 4 step 118).
Claims 8-12, and 14-20 recite limitations substantially similar to the limitations of claims 1-5 and 7. Therefore, claims 8-12, and 14-20 are rejected under the same reasoning as claims 1-5 and 7.
Regarding claim 8, the limitations stand rejected under the same reasoning as the limitations of claim 1. However, the limitations “determining whether a stripe associated with the address specified by the write request is present in a volatile memory device…responsive to determining that the stripe associated with the write request is present in the volatile memory device, performing the write request on the managed unit of the stripe identified by the managed unit index” and “determining whether the, stripe is full…responsive to determining that the stripe is full, copying, from the stripe in the volatile memory device, the data in each managed unit of a corresponding fault tolerant stripe in the non-volatile memory device; calculating, after the data in each managed unit of the stripe is copied to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device, a redundancy metadata using the data in the corresponding fault tolerant stripe in the non-volatile memory device; and storing, in the corresponding fault tolerant stripe in the non-volatile memory device, the redundancy metadata” are contingent conditions. The broadest reasonable interpretation of a method claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition precedent are not met, MPEP § 2111.04 II. In this case, when it is determined that the stripe associated with the write request is not present in the volatile memory device, then the contingent step of “performing the write request on the managed unit of the stripe identified by the managed unit index” is not required. When it is determined that the stripe is not full, then the contingent steps of “copying, from the stripe in the volatile memory device, the data in each managed unit of a corresponding fault tolerant stripe in the non-volatile memory device; calculating, after the data in each managed unit of the stripe is copied to the managed unit of the corresponding fault tolerant stripe in the non-volatile memory device, a redundancy metadata using the data in the corresponding fault tolerant stripe in the non-volatile memory device; and storing, in the corresponding fault tolerant stripe in the non-volatile memory device, the redundancy metadata” are not required. Claims 9, 12, and 14 recite limitations that depend from the contingent steps. Therefore, evidence of the anticipation/obviousness of method steps are not required to be performed under the broadest reasonable interpretation of claims 8, 9, 12, and 14.
Response to Arguments
Applicant’s arguments, filed February 2, 2026, with respect to the rejection of the claims under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Riedle, Eckert et al., and Lee.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137