DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15, 17-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yun et al. (US 2021/0143096) (hereinafter, “Yun”).
Re: independent claim 15, Yun discloses in fig. 5A-8B a semiconductor device, comprising: a substrate (100) of semiconductor material; a plurality of stacks of memory cells (MCR0, MCR1) disposed within the substrate; a capacitor (FR1) disposed between two adjacent stacks of memory cells, the capacitor comprising at least two conductive layers separated by a dielectric layer (including EP1-EP7, THV1, [0116]); and a power supply line (TH_L) conductively connected to one conductive layer of the at least two conductive layers.
Re: claim 17, Yun discloses in figs. 5A-8B the semiconductor device of claim 15, wherein the power supply line is conductively connected to a first layer of the at least two conductive layers and wherein a second layer of the at least two conductive layers is electrically grounded (a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. MPEP § 2114.).
Re: claim 18, Yun discloses in figs. 5A-8B the semiconductor device of claim 15, wherein the power supply line (TH_L) is a metal stripe extending perpendicularly over the plurality of stacks (fig. 7).
Re: claim 20, Yun discloses in figs. 5A-8B the semiconductor device of claim 15, wherein the capacitor (including THV1) is substantially oblong (fig. 7).
Allowable Subject Matter
Claims 1-14 are allowed.
Claims 16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, a semiconductor device, comprising: a substrate of semiconductor material; a plurality of stacks of memory cells disposed within the substrate, each stack comprising a conductive string connecting a plurality of memory cells to a bitline, wherein each memory cell is located at an intersection of the conductive string and a wordline; a capacitor having a body disposed between two adjacent stacks of the plurality of stacks, the capacitor comprising an inner conductive layer and an outer conductive layer at least partially surrounding the inner conductive layer, wherein the inner conductive layer and the outer conductive layer are separated by a dielectric layer; and a power supply line conductively connected to an end of the capacitor at a base of the body; and as recited in independent claim 8, a semiconductor device, comprising: a substrate of semiconductor material; a plurality of conductive strings, each string connecting a stack of memory cells disposed within the substrate to a bitline, wherein each memory cell is located at an intersection of the string and a wordline; a capacitive structure disposed between two adjacent stacks of memory cells, the capacitive structure comprising an inner conductive layer and an outer conductive layer that is concentric with the inner conductive layer, wherein the inner conductive layer and the outer conductive layer are separated by a dielectric layer; and a power supply line conductively connected to a base of the capacitive structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. US 9,659,954 teach a non-volatile memory device with vertically integrated capacitor electrodes having a circular pillar shape.
Nishikawa et al. US 10,629,675 teach a memory device including capacitor pillars.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 12/31/2025