DETAILED ACTION
1. This Office Action is taken in response to Applicants’ Amendments and Remarks filed on 2/24/2026 regarding application 18/405,063 filed on 1/5/2024.
Claims 1, 3-10, and 12-22 are pending for consideration.
2. Response to Amendments and Remarks
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
(1) In view of the amendments and remarks, the rejections of claims 1, 3-10, and 12-22 under 35 U.S.C. 112(b) have been withdrawn.
However, the presently amended limitation “responsive to sending the first command, obtain read data for each memory cell of the target memory page, wherein the read data for a respective one of the memory cells has a first value responsive to a threshold voltage of the one of the memory cells being lower than the first read voltage,” because the wordings “a first value responsive to a threshold voltage …” may still lead to the confusion that the first value is the result due to the applying of the threshold voltage instead of the applying of the first read voltage.
It is strongly suggested that “a first value responsive to a threshold voltage …” be changed to “a first value corresponding to a threshold voltage …” Similarly, the wordings “a second value responsive to a threshold voltage …” should be rephrased as “a second value corresponding to a threshold voltage …”
(2) In response to the amendments and remarks, an updated claim analysis has been made with newly identified reference(s). Refer to the corresponding sections of the following Office Action for details.
3. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 3-5, 7-10, 12-13, 15-20, and 22 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yoon et al. (US Patent Application Publication 2015/0332777, hereinafter Yoon).
As to claim 1, Yoon teaches A memory system [memory system as shown in figures 1-2, and 24-26], comprising:
a memory device comprising a plurality of memory pages each comprising a plurality of memory cells [memory device as shown in figure 4; Example embodiments of the inventive concept provide a read method of a nonvolatile memory device that includes sensing data in a selected memory area of the nonvolatile memory device using at least one or more read voltages, the sensed data being latched by a page unit. The read method further includes backing up a page of the latched data, and combining the latched data by page unit, the combined data being output as read data corresponding to a page unit … (¶ 0008-0009); FIG. 2 is a distribution diagram schematically illustrating drooping and spreading of a threshold voltage distribution of memory cells (¶ 0012)]; and
a memory controller [memory controller, figure 3, 110] coupled with the memory device [as shown in figure 3, where the memory controller (110) is connected to the NVM memory device (112)] and configured to:
send a first command to cause the memory device to perform a read operation on data in a target memory page at a first read voltage [as shown in figure 21, where the memory controller (310) sends a read command R_CMD to the NVM (320); A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage … (abstract)];
responsive to sending the first command, obtain read data for each memory cell of the target memory page, wherein the read data for a respective one of the memory cells has a first value responsive to a threshold voltage of the one of the memory cells being lower than the first read voltage and a second value responsive to the threshold voltage of the one of the memory cells being larger than the first read voltage [as shown in figure 5, where the read voltage RV is applied to a plurality of memory cells, and where those memory cells with threshold voltage Vth lower than the read voltage RV (i.e., S1) have a first value of “1” and those memory cells with threshold voltage Vth larger than the read voltage RV (i.e., S2) have a second value of “0”; FIG 5 shows a variation in threshold voltages of memory cells. Referring to FIG. 5, there are illustrated distributions S1 and S2 of threshold voltages of memory cells immediately after programming, and distributions S1′ and S2′ of threshold voltages of memory cells changed due to the lapse of time and a specific cause … Threshold voltages of memory cells may form distributions S1 and S2 immediately after a program operation. The distributions S1 and S2 may be distinguished using a read voltage RV. The read voltage RV may be decided to have a threshold voltage level corresponding to a distribution valley at which the distributions S1 and S2 are overlapped, by analyzing various factors … In the case a sensing operation is performed with the read voltage RV, a ratio of logical 0s to logical 1s stored in memory cells may be maintained in balance at a point in time when the distributions S1 and S2 are maintained. The reason is that data is randomized such that program states are uniformly distributed. However, if the distributions S1 and S2 are changed into distributions S1′ and S2′ due to a variation in threshold voltages of memory cells, the balance among program states may be broken and no longer exist. For example, the number of logical 1s may increase when memory cells of which threshold voltages belong to the distributions S1′ and S2′ are sensed with the read voltage RV (¶ 0071-0073)];
obtain a difference between a count of the first value and a count of the second value [as shown in figure 22, where the number of difference between “1” and “0” is tabulated as a function of ∆v; … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … (¶ 0143-0145)];
determine the first read voltage not to be a target read voltage responsive to an absolute value of the difference between the count of the first value and the count of the second value being larger than a preset value [the corresponding “target read voltage” is the “optimal read voltage;” which is determined by the difference between the number of “1” and “0” being less than a reference value -- … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … A shift degree of a distribution valley may be decided by detecting a variation in a relative ratio of logical 1s and logical 0s that are uniformly distributed in read data R_Data, or by detecting an absolute variation in the number of logical 1s or logical 0s … (¶ 0143-0145); The memory controller 110 receives the SLC data S_Data to detect an increment of logical 1. For example, in a case that the number of logical 1s included in the SLC data S_Data is more than (or exceeds) a reference value Rn by as many as 1 to 5, the memory controller 110 increases an optimal read voltage corresponding to a distribution valley by a. That is, in the case that the number of logical 1s included in the SLC data S_Data increases, the memory controller 110 determines a location of the distribution valley as being increased. The memory controller 110 may decide an optimal read voltage by increasing a read voltage by a corresponding to an increment of logical 1 … (¶ 0077-0078); If an uncorrectable error is detected, the memory controller 210 requests the number of logical 1s or 0s included in backed-up SLC data S_Data from the nonvolatile memory device 220 … The memory controller 210 estimates a location of a distribution valley and decides an optimal read voltage corresponding to the estimated location. The memory controller 210 may include a table 215 which is configured to decide a shift degree of a distribution valley based on a relative magnitude of logical 0 or logical (¶ 0126)]; and
determine the first read voltage to be the target read voltage responsive to the absolute value of the difference between the count number of the first value and the count number of the second value being smaller than or equal to the preset value [the corresponding “target read voltage” is the “optimal read voltage;” which is determined by the difference between the number of “1” and “0” being less than a reference value -- … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … A shift degree of a distribution valley may be decided by detecting a variation in a relative ratio of logical 1s and logical 0s that are uniformly distributed in read data R_Data, or by detecting an absolute variation in the number of logical 1s or logical 0s … (¶ 0143-0145); The memory controller 110 receives the SLC data S_Data to detect an increment of logical 1. For example, in a case that the number of logical 1s included in the SLC data S_Data is more than (or exceeds) a reference value Rn by as many as 1 to 5, the memory controller 110 increases an optimal read voltage corresponding to a distribution valley by a. That is, in the case that the number of logical 1s included in the SLC data S_Data increases, the memory controller 110 determines a location of the distribution valley as being increased. The memory controller 110 may decide an optimal read voltage by increasing a read voltage by a corresponding to an increment of logical 1 … (¶ 0077-0078); If an uncorrectable error is detected, the memory controller 210 requests the number of logical 1s or 0s included in backed-up SLC data S_Data from the nonvolatile memory device 220 … The memory controller 210 estimates a location of a distribution valley and decides an optimal read voltage corresponding to the estimated location. The memory controller 210 may include a table 215 which is configured to decide a shift degree of a distribution valley based on a relative magnitude of logical 0 or logical (¶ 0126)].
As to claim 3, Yoon teaches The memory system of claim 1, wherein the preset value is in a range of 100 to 300 [as shown in figure 22, where the range of the number of difference between “1” and “0” is tabulated as a function of ∆v, and the difference may range from -5 to 500, thus covering the range from 100 to 300 ].
As to claim 4, Yoon teaches The memory system of claim 1, wherein each of the memory cells stores one bit of data [as shown in figure 5, where each memory cell stores one bot of data, “1” or “0”; … The nonvolatile memory device 120 may also perform a backup operation on data (e.g., SLC data) corresponding to at least one of a plurality of single level cell (SLC) read operations that are executed during a procedure of reading out the read data R_Data … (¶ 0055-0058)].
As to claim 5, Yoon teaches The memory system of claim 1, wherein the memory controller is configured to: send a second command responsive to an absolute value of the difference between the count of the first values and the count of the second values being larger than a preset value and the count of the first values is larger than the count of the second values, the second command indicating to perform the read operation on the data in the target memory page at a second read voltage [A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract)], the second read voltage being smaller than the first read voltage [as shown in figure 22, when the ∆v (i.e., the difference between the first and the second read voltages) is negative, the second read voltage is smaller than the first read voltage]; and send a third command responsive to the absolute value of the difference between the count number of the first values and the count number of the second values being larger than the preset value and the count number of the first values is smaller than the count number of the second values, the third command indicating to perform the read operation on the data in the target memory page at a third read voltage, the third read voltage being larger than the first read voltage [as shown in figure 22, when a plurality of ∆v (i.e., the difference between the first and the second read voltages) are applied to the memory cells, in order to reach the optimal read voltage; FIG. 22 is a table schematically illustrating distribution valley detection table 315 shown in FIG. 19, according to an embodiment of the inventive concept. Referring to FIG. 22, distribution valley detection table 315 shows a relation between an increment or decrement of logical 1 and a shift degree of a distribution valley … (¶ 0158-0164)].
As to claim 7, Yoon teaches The memory system of claim 1, wherein the memory page corresponds to a read voltage table that comprises a plurality of read voltages arranged in order from small to large, values of two adjacent read voltages differing by a fixed offset; and the memory controller is configured to: select the read voltage from the read voltage table using a dichotomization method to perform the read operation on the data in the target memory page, responsive to the read operation being performed on the target memory page [as shown in figure 22, when a plurality of ∆v (i.e., the difference between the first and the second read voltages) are applied to the memory cells, in order to reach the optimal read voltage; FIG. 22 is a table schematically illustrating distribution valley detection table 315 shown in FIG. 19, according to an embodiment of the inventive concept. Referring to FIG. 22, distribution valley detection table 315 shows a relation between an increment or decrement of logical 1 and a shift degree of a distribution valley … (¶ 0158-0164)].
As to claim 8, Yoon teaches The memory system of claim 1, wherein the memory system comprises a memory card or a solid-state drive [SSD as shown in figure 24, and memory card as shown in figure 25].
As to claim 9, Yoon teaches The memory system of claim 1, wherein the memory device comprises a memory array and a peripheral circuit coupled with the memory array, and the peripheral circuit is configured to: receive the first command sent from the memory controller; and send the first value and the second value read from the target memory page to the memory controller [the memory device as shown in figure 24, which includes a memory array (1230), and controller (1210); figure 21 shows the read commands and read data communications between the memory controller (310) and the NVM memory (320)].
As to claim 10, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 12, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 13, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 9, and is rejected for the same reasons set forth in the analysis of claim 9. Refer to “As to claim 9” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 18, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 22, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
5. Claims 1, 4-10, 13-17, and 19-22 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ueki et al. (US Patent Application Publication 2018/0076829, hereinafter Ueki).
As to claim 1, Ueki teaches A memory system [as shown in figures 1-2; A memory system includes a memory that includes a plurality of memory cells, and a controller … (abstract)], comprising:
a memory device comprising a plurality of memory pages [A memory system includes a memory that includes a plurality of memory cells, and a controller … (abstract); … In a case of the lower page … in a case of the upper page … (¶ 0134)]; and a memory controller coupled with the memory device [memory controller, figure 1, 2; A memory system includes a memory that includes a plurality of memory cells, and a controller … (abstract); Thus, according to the third embodiment, the memory controller 2 counts the number of memory cells having a threshold voltage in the range including the optimum voltage value (S309 to S313) … (¶ 0135)] and configured to:
send a first command that indicates to perform a read operation on data in a target memory page at a first read voltage [the corresponding “first read voltage” may be “the optimum voltage value V_AB_OPT” as shown in figures 12-13; FIG. 12 is a diagram for illustrating a distribution of the number of memory cells which are counting targets. FIG. 12 illustrates a distribution A and a distribution B as an example. In addition, in the example of FIG. 12, the number of memory cells having a threshold voltage in a range of 2×dV centered on a voltage value in which the total amount of the distribution A and the distribution B is minimized (the optimum voltage value V_AB_OPT relevant to the read voltage V_AB) (corresponding to an area of a shaded portion 400 in FIG. 12) is the counting target. The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage. Furthermore, any method may be used as a setting method of the range. Hereinafter, the memory cell which is the counting target will be referred to as a target memory cell (¶ 0120)]
obtain a first value and a second value read from the target memory page [the first value and the second value are “0” and “1,” respectively -- as shown in figures 12-13; FIG. 12 is a diagram for illustrating a distribution of the number of memory cells which are counting targets. FIG. 12 illustrates a distribution A and a distribution B as an example. In addition, in the example of FIG. 12, the number of memory cells having a threshold voltage in a range of 2×dV centered on a voltage value in which the total amount of the distribution A and the distribution B is minimized (the optimum voltage value V_AB_OPT relevant to the read voltage V_AB) (corresponding to an area of a shaded portion 400 in FIG. 12) is the counting target. The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage. Furthermore, any method may be used as a setting method of the range. Hereinafter, the memory cell which is the counting target will be referred to as a target memory cell (¶ 0120)], the read data being the first value responsive to a threshold voltage of a memory cell being lower than the first read voltage, and the read data being the second value responsive to the threshold voltage of the memory cell being larger than the first read voltage [V_AB_OPT+dV corresponds to the threshold voltage higher than the first read voltage V_AB_OPT, and V_AB_OPT-dV corresponds to the threshold voltage lower than the first read voltage V_AB_OPT -- as shown in figures 12-13; FIG. 12 is a diagram for illustrating a distribution of the number of memory cells which are counting targets. FIG. 12 illustrates a distribution A and a distribution B as an example. In addition, in the example of FIG. 12, the number of memory cells having a threshold voltage in a range of 2×dV centered on a voltage value in which the total amount of the distribution A and the distribution B is minimized (the optimum voltage value V_AB_OPT relevant to the read voltage V_AB) (corresponding to an area of a shaded portion 400 in FIG. 12) is the counting target. The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage. Furthermore, any method may be used as a setting method of the range. Hereinafter, the memory cell which is the counting target will be referred to as a target memory cell (¶ 0120)];
obtain a difference between a number of the first value and a number of the second value [as shown in figures 12-13; … The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage … (¶ 0120); Subsequently, the first processing unit 241 executes the shift reading in the binary mode by using (V_AB_OPT−dV) as the read voltage (S311). Furthermore, (V_AB_OPT−dV) corresponds to a lower limit value of the range. The first processing unit 241 counts the number of “1” included in the data output from the NAND memory 1 to the memory controller 2, and sets the value as B (S312). Then, the first processing unit 241 calculates a difference |A−B| between a count value A and a count value B (S313). A value obtained by the processing of S313 corresponds to the number of target memory cells (¶ 0130)]; and
determine the first read voltage not to be a target read voltage responsive to an absolute value of the difference between a number of the first value and a number of the second value being larger than a preset value; and
determine the first read voltage to be the target read voltage responsive to the absolute value of the difference between the number of the first value and the number of the second value being smaller than or equal to the preset value [as shown in figures 12-13; FIG. 13 is a flowchart illustrating an operation of the memory system 100 according to the third embodiment. In S301 to S308, the first processing unit 241 executes the same processing as that of S201 to S208 in FIG. 11, and thus, estimates the optimum voltage value V_AB_OPT. Subsequently, the first processing unit 241 executes the shift reading in the binary mode by using (V_AB_OPT+dV) as the read voltage (S309). Furthermore, (V_AB_OPT+dV) corresponds to an upper limit value of the range. The first processing unit 241 counts the number of “1” included in the data output from the NAND memory 1 to the memory controller 2, and sets the value to A (S310). The first processing unit 241 stores the count value, for example, in the RAM 22 or the like. Subsequently, the first processing unit 241 executes the shift reading in the binary mode by using (V_AB_OPT−dV) as the read voltage (S311). Furthermore, (V_AB_OPT−dV) corresponds to a lower limit value of the range. The first processing unit 241 counts the number of “1” included in the data output from the NAND memory 1 to the memory controller 2, and sets the value as B (S312). Then, the first processing unit 241 calculates a difference |A−B| between a count value A and a count value B (S313). A value obtained by the processing of S313 corresponds to the number of target memory cells … (¶ 0129-0136)].
As to claim 4, Ueki teaches The memory system of claim 1, wherein each of the memory pages comprises a plurality of memory cells, each of which stores one bit of data [as shown in figures 12-13; A memory system includes a memory that includes a plurality of memory cells, and a controller … (abstract); FIG. 12 is a diagram for illustrating a distribution of the number of memory cells which are counting targets. FIG. 12 illustrates a distribution A and a distribution B as an example. In addition, in the example of FIG. 12, the number of memory cells having a threshold voltage in a range of 2×dV centered on a voltage value in which the total amount of the distribution A and the distribution B is minimized (the optimum voltage value V_AB_OPT relevant to the read voltage V_AB) (corresponding to an area of a shaded portion 400 in FIG. 12) is the counting target. The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage. Furthermore, any method may be used as a setting method of the range. Hereinafter, the memory cell which is the counting target will be referred to as a target memory cell (¶ 0120)].
As to claim 5, Ueki teaches The memory system of claim 1, wherein the memory controller is configured to: send a second command responsive to an absolute value of the difference between the number of the first value and the number of the second value being larger than a preset value and the number of the first value is larger than the number of the second value, the second command indicating to perform the read operation on the data in the target memory page at a second read voltage, the second read voltage being smaller than the first read voltage; and send a third command responsive to the absolute value of the difference between the number of the first value and the number of the second value being larger than the preset value and the number of the first value is smaller than the number of the second value, the third command indicating to perform the read operation on the data in the target memory page at a third read voltage, the third read voltage being larger than the first read voltage [as shown in figures 12-13; FIG. 12 is a diagram for illustrating a distribution of the number of memory cells which are counting targets. FIG. 12 illustrates a distribution A and a distribution B as an example. In addition, in the example of FIG. 12, the number of memory cells having a threshold voltage in a range of 2×dV centered on a voltage value in which the total amount of the distribution A and the distribution B is minimized (the optimum voltage value V_AB_OPT relevant to the read voltage V_AB) (corresponding to an area of a shaded portion 400 in FIG. 12) is the counting target. The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage. Furthermore, any method may be used as a setting method of the range. Hereinafter, the memory cell which is the counting target will be referred to as a target memory cell (¶ 0120); as shown in figures 12-13; FIG. 13 is a flowchart illustrating an operation of the memory system 100 according to the third embodiment. In S301 to S308, the first processing unit 241 executes the same processing as that of S201 to S208 in FIG. 11, and thus, estimates the optimum voltage value V_AB_OPT. Subsequently, the first processing unit 241 executes the shift reading in the binary mode by using (V_AB_OPT+dV) as the read voltage (S309). Furthermore, (V_AB_OPT+dV) corresponds to an upper limit value of the range. The first processing unit 241 counts the number of “1” included in the data output from the NAND memory 1 to the memory controller 2, and sets the value to A (S310). The first processing unit 241 stores the count value, for example, in the RAM 22 or the like. Subsequently, the first processing unit 241 executes the shift reading in the binary mode by using (V_AB_OPT−dV) as the read voltage (S311). Furthermore, (V_AB_OPT−dV) corresponds to a lower limit value of the range. The first processing unit 241 counts the number of “1” included in the data output from the NAND memory 1 to the memory controller 2, and sets the value as B (S312). Then, the first processing unit 241 calculates a difference |A−B| between a count value A and a count value B (S313). A value obtained by the processing of S313 corresponds to the number of target memory cells … (¶ 0129-0136)].
As to claim 6, Ueki teaches The memory system of claim 1, wherein the memory controller comprises a register and is configured to: store the first value and the second value read from the target memory page into the register temporarily [The sense amplifier 117 stores the read data in the data register 116. The data stored in the data register 116 is sent to the I/O signal processing circuit 110 through a data line, and is transmitted to the memory controller 2 from the I/O signal processing circuit 110 (¶ 0046)]; and count numbers of the first value and the second value using the register [… Here, “1” is set as the first data value, “0” is set as the second data value, and the number of “1” is set to be counted, as an example. When the counted number of “1” is plotted with respect to the read voltage, it is possible to obtain a curve illustrated in a lower portion of FIG. 10. In addition … the first processing unit 241 may count the number of “0” instead of the number of “1”. In such a case, the first processing unit 241 calculates an absolute value of the amount of change of the number of “0”. Thus, it is possible to obtain an approximation of the distribution of the memory cell with respect to the threshold voltage … (¶ 0098-0102)].
As to claim 7, Ueki teaches The memory system of claim 1, wherein the memory page corresponds to a read voltage table that comprises a plurality of read voltages arranged in order from small to large, values of two adjacent read voltages differing by a fixed offset; and the memory controller is configured to: select the read voltage from the read voltage table using a dichotomization method to perform the read operation on the data in the target memory page, responsive to the read operation being performed on the target memory page [as shown in figures 12-13; FIG. 12 is a diagram for illustrating a distribution of the number of memory cells which are counting targets. FIG. 12 illustrates a distribution A and a distribution B as an example. In addition, in the example of FIG. 12, the number of memory cells having a threshold voltage in a range of 2×dV centered on a voltage value in which the total amount of the distribution A and the distribution B is minimized (the optimum voltage value V_AB_OPT relevant to the read voltage V_AB) (corresponding to an area of a shaded portion 400 in FIG. 12) is the counting target. The number of memory cells having a threshold voltage in the range of 2×dV centered on V_AB_OPT is capable of being obtained by calculating a difference in the number of “0” or the number of “1” included in two data items read at the time of performing the shift reading in the binary mode by using each of V_AB_OPT+dV and V_AB_OPT−dV as the read voltage. Furthermore, any method may be used as a setting method of the range. Hereinafter, the memory cell which is the counting target will be referred to as a target memory cell (¶ 0120)].
As to claim 8, Ueki teaches The memory system of claim 1, wherein the memory system comprises a memory card or a solid-state drive [The memory system 100 includes a NAND type flash memory (a NAND memory) 1, a memory controller 2 between the host device 200 and the NAND memory 1, which executes data transmission. Furthermore, the memory system 100 may include other types of memory instead of the NAND memory 1. For example, the memory system 100 may include a NOR type flash memory instead of the NAND memory 1 (¶ 0025); FIG. 16 is a diagram illustrating a mounting example of the memory system 100. The memory system 100, for example, is mounted on a server system 1000. A disk array 2000 and a rack-mounted server 3000 are connected to the server system 1000 through a communication interface 4000 … (¶ 0156-0157)].
As to claim 9, Ueki teaches The memory system of claim 1, wherein the memory device comprises a memory array and a peripheral circuit coupled with the memory array, and the peripheral circuit is configured to: receive the first command sent from the memory controller; and send the first value and the second value read from the target memory page to the memory controller [as shown in figure 1; A memory system includes a memory that includes a plurality of memory cells, and a controller … (abstract); FIG. 1 is a diagram illustrating a configuration example of a memory system according to a first embodiment. A memory system 100 is connected to a host device 200. The host device 200, for example, corresponds to a server, a personal computer, a mobile type information processing device, or the like. The memory system 100 functions as an external storing device of the host device 200. The host device 200 is capable of issuing an access request (a read request and a write request) with respect to the memory system 100. Any communication interface standard may be used in the embodiments. For example, the communication interface is based on an advanced technology attachment (ATA) standard, a serial attached SCSI (SAS) standard, a peripheral components interconnect (PCI) express standard, and the like (¶ 0024)].
As to claim 10, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 13, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 14, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 9, and is rejected for the same reasons set forth in the analysis of claim 9. Refer to “As to claim 9” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 21, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 22, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 6, 14, and 21 and are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US Patent Application Publication 2015/0332777, hereinafter Yoon), and in view of Ueki et al. (US Patent Application Publication 2018/0076829, hereinafter Ueki).
Regarding claim 6, Yoon teaches counting the numbers of the first value and the second value [… If the memory controller 210 requests the backed-up SLC data S_Data, the nonvolatile memory device 220 counts the number of logical 1s or 0s included in the backed-up SLC data S_Data. The nonvolatile memory device 220 may include a bit counter 227 that counts the number of logical 1s or 0s included in SLC data S_Data … (¶ 0125-0126)], but does not teach the memory controller comprises a register and is configured to: store the first value and the second value read from the target memory page into the register temporarily.
However, Ukei specifically teaches the memory controller comprises a register and is configured to: store the first value and the second value read from the target memory page into the register temporarily [The sense amplifier 117 stores the read data in the data register 116. The data stored in the data register 116 is sent to the I/O signal processing circuit 110 through a data line, and is transmitted to the memory controller 2 from the I/O signal processing circuit 110 (¶ 0046)]; and count numbers of the first value and the second value using the register [… Here, “1” is set as the first data value, “0” is set as the second data value, and the number of “1” is set to be counted, as an example. When the counted number of “1” is plotted with respect to the read voltage, it is possible to obtain a curve illustrated in a lower portion of FIG. 10. In addition … the first processing unit 241 may count the number of “0” instead of the number of “1”. In such a case, the first processing unit 241 calculates an absolute value of the amount of change of the number of “0”. Thus, it is possible to obtain an approximation of the distribution of the memory cell with respect to the threshold voltage … (¶ 0098-0102)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to use a register to store the first vale (“1”) and the second value (“0”), as specifically demonstrated by Ukei, and to incorporate it into the existing scheme disclosed by Yoon, in order to facilitate counting the number of the first vale (“1”) and the second value (“0”).
As to claim 14, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 21, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
Conclusion
7. Claims 1, 3-10, and 12-22 are rejected as explained above.
8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE
MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
Prosecution Insights