DETAILED ACTION
1. This Office Action is taken in response to Applicants’ Amendments and Remarks filed on 6/24/2026 regarding application 18/405,063 filed on 1/5/2024.
Claims 1, 3-10, and 12-22 are pending for consideration.
2. Response to Amendments and Remarks
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
(1) In response to the amendments and remarks, an updated claim analysis has been made with newly identified reference(s). Refer to the corresponding sections of the following Office Action for details.
3. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
4. Claims 1, 3-10, and 12-22 are rejected, because claim 1 recites the limitation "wherein both the count of the first value and the count of the second value are derived from the read data obtained responsive to sending the first command.” There is insufficient antecedent basis for “the count of the first value” and “the count of the second value,” and all the preceding limitations do not recite “a count of the first value” and “a count of the second value.”
It is noted that a limitation “obtain a difference between a count of the first value and a count of the second value” is recited following the above cited limitation. The order of these two limitations should be reversed in order to avoid the lack of antecedence issue.
Corrections are needed.
Claims 3-9 are rejected by virtue of their dependency from claim 1.
Claims 10 suffers from the same deficiency as in claim 1.
Claims 12-16 are rejected by virtue of their dependency from claim 10.
Claims 17 suffers from the same deficiency as in claim 1.
Claims 18-22 are rejected by virtue of their dependency from claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 3-10, and 12-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US Patent Application Publication 2015/0332777, hereinafter Yoon), and in view of Yang (US Patent Application Publication 2020/0133767).
As to claim 1, Yoon teaches A memory system [memory system as shown in figures 1-2, and 24-26; Yang also teaches this limitation – as shown in figures 1 and 2], comprising:
a memory device comprising a plurality of memory pages each comprising a plurality of memory cells [memory device as shown in figure 4; Example embodiments of the inventive concept provide a read method of a nonvolatile memory device that includes sensing data in a selected memory area of the nonvolatile memory device using at least one or more read voltages, the sensed data being latched by a page unit. The read method further includes backing up a page of the latched data, and combining the latched data by page unit, the combined data being output as read data corresponding to a page unit … (¶ 0008-0009); FIG. 2 is a distribution diagram schematically illustrating drooping and spreading of a threshold voltage distribution of memory cells (¶ 0012); Yang also teaches this limitation – A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks for storing data and each block includes a plurality of pages ... (abstract); ... In reality, the NAND flash device always reads complete pages from the memory cells and writes complete pages to the memory cells. After a page of data is read from the array into a buffer inside the device, the host can access the data bytes or words one by one by serially clocking them out using a strobe signal (¶ 0003)]; and
a memory controller [memory controller, figure 3, 110; Yang also teaches this limitation – controller, figure 1, 160] comprising an error correction unit configured to perform low density parity check (LDPC) hard decoding [A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract); The memory controller 110 may perform an error detection and correction on the read data R_Data ... (¶ 0056);
Yang more expressively teaches low density parity check (LDPC) hard decoding -- When the controller 160 reads page data from the flash memory 180 using a read threshold voltage, the retrieved page data is transmitted to the error-correction circuit 168, and the error-correction circuit 168 is configured to perform error correction on the page data, and the error-correction scheme performed by the error-correction circuit 168 can be referred to as hard data decoding. In some embodiments, the error-correction circuit 168 includes a low-density parity-check code (LDPC) error-correction engine (not shown in FIG. 1) and/or a BCH-code error-correction engine (not shown in FIG. 1), but the invention is not limited thereto (¶ 0024-0025)], the memory controller coupled with the memory device [as shown in figure 3, where the memory controller (110) is connected to the NVM memory device (112); Yang also teaches this limitation – as shown in figure 1, where the controller (160) is coupled to the flash memory device (180)] and configured to:
select a first read voltage from a read voltage table using a dichotomization method, the read voltage table comprising a plurality of read voltages arranged in order from small to large with values of two adjacent read voltages differing by a fixed offset [a plurality of read voltages as shown in figures 7, 14, 22, and 23; The memory controller 310 may perform an error detection and correction of the read data R_Data. If the read data R_Data is uncorrectable, the memory controller 310 may estimate a shift degree of a distribution valley, based on the number of logical 1s or logical 0s included in the read data R_Data ... Herein, the distribution valley detection table 315 is used to estimate a shift degree of a distribution valley according to various references. For example, the distribution valley detection table 315 may map a shift degree ΔV of a distribution valley onto a difference between the number of logical 1s of the read data R_Data and the number of logical 0s thereof. Or, the distribution valley detection table 315 may map a shift degree ΔV of a distribution valley onto a difference between the number of logical 1s of the read data R_Data and a reference value ... (¶ 0143-0145); Yang also teaches this limitation – read voltages tables as shown in 4A and 4B; ... In response to a failure of the default read operation, the controller is configured to sequentially perform a read operation on the flash memory using a configuration of a respective read threshold voltage corresponding to each entry of a plurality of entries in a read-retry table, and replace the configuration of the default read threshold voltage with the configuration of the read threshold voltage corresponding to the read operation being successfully performed (¶ 0005); The read-retry procedure may perform read operations according to a read-retry table 141. The read-retry table 141 includes a plurality of entries, and each entry records a configuration of a read threshold voltage required for the read operation ... (¶ 0027-0028)];
responsive to the error correction unit failing to decode data read from a target memory page at a default read voltage [A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract); it is noted that “a first voltage” mentioned in the abstract is the corresponding “default read voltage” as recited in this limitation;
Yang more expressively teaches the default read voltage – as shown in figure 5, steps 510-522; A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks for storing data and each block includes a plurality of pages. The controller is configured to convert a host read command into a read-operation instruction to the flash memory to perform a default read operation to read page data from the flash memory. The default read operation has a default read threshold voltage. In response to a failure of the default read operation, the controller is configured to sequentially perform a read operation on the flash memory using a read threshold voltage with respect to each entry of a plurality of entries in a read-retry table, and replace the default read threshold voltage with the read threshold voltage corresponding to the read operation being successfully performed (abstract)], send a first command to cause the memory device to perform a read operation on data in a target memory page at a first read voltage [A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract); it is noted that “a second voltage” mentioned in the abstract is the corresponding “first read voltage” as recited in this limitation; Example embodiments of the inventive concept provide a read method of a nonvolatile memory device that includes sensing data in a selected memory area of the nonvolatile memory device using at least one or more read voltages, the sensed data being latched by a page unit. The read method further includes backing up a page of the latched data, and combining the latched data by page unit, the combined data being output as read data corresponding to a page unit ... (¶ 0008); Yang also teaches this limitation – read voltages tables as shown in 4A and 4B; ... In response to a failure of the default read operation, the controller is configured to sequentially perform a read operation on the flash memory using a configuration of a respective read threshold voltage corresponding to each entry of a plurality of entries in a read-retry table, and replace the configuration of the default read threshold voltage with the configuration of the read threshold voltage corresponding to the read operation being successfully performed (¶ 0005); The read-retry procedure may perform read operations according to a read-retry table 141. The read-retry table 141 includes a plurality of entries, and each entry records a configuration of a read threshold voltage required for the read operation ... (¶ 0027-0028)];
responsive to sending the first command, obtain read data for each memory cell of the target memory page, wherein the read data for a respective one of the memory cells has a first value responsive to a threshold voltage of the one of the memory cells being lower than the first read voltage and a second value responsive to the threshold voltage of the one of the memory cells being larger than the first read voltage [as shown in figure 5, where the read voltage RV is applied to a plurality of memory cells, and where those memory cells with threshold voltage Vth lower than the read voltage RV (i.e., S1) have a first value of “1” and those memory cells with threshold voltage Vth larger than the read voltage RV (i.e., S2) have a second value of “0”; FIG 5 shows a variation in threshold voltages of memory cells. Referring to FIG. 5, there are illustrated distributions S1 and S2 of threshold voltages of memory cells immediately after programming, and distributions S1′ and S2′ of threshold voltages of memory cells changed due to the lapse of time and a specific cause … Threshold voltages of memory cells may form distributions S1 and S2 immediately after a program operation. The distributions S1 and S2 may be distinguished using a read voltage RV. The read voltage RV may be decided to have a threshold voltage level corresponding to a distribution valley at which the distributions S1 and S2 are overlapped, by analyzing various factors … In the case a sensing operation is performed with the read voltage RV, a ratio of logical 0s to logical 1s stored in memory cells may be maintained in balance at a point in time when the distributions S1 and S2 are maintained. The reason is that data is randomized such that program states are uniformly distributed. However, if the distributions S1 and S2 are changed into distributions S1′ and S2′ due to a variation in threshold voltages of memory cells, the balance among program states may be broken and no longer exist. For example, the number of logical 1s may increase when memory cells of which threshold voltages belong to the distributions S1′ and S2′ are sensed with the read voltage RV (¶ 0071-0073)], wherein both the count of the first value and the count of the second value are derived from the read data obtained responsive to sending the first command [A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract); it is noted that “a second voltage” mentioned in the abstract is the corresponding “first read voltage” as recited in this limitation; The memory controller 310 may perform an error detection and correction of the read data R_Data. If the read data R_Data is uncorrectable, the memory controller 310 may estimate a shift degree of a distribution valley, based on the number of logical 1s or logical 0s included in the read data R_Data ... Herein, the distribution valley detection table 315 is used to estimate a shift degree of a distribution valley according to various references. For example, the distribution valley detection table 315 may map a shift degree ΔV of a distribution valley onto a difference between the number of logical 1s of the read data R_Data and the number of logical 0s thereof. Or, the distribution valley detection table 315 may map a shift degree ΔV of a distribution valley onto a difference between the number of logical 1s of the read data R_Data and a reference value ... (¶ 0143-0145)];
obtain a difference between a count of the first value and a count of the second value [as shown in figure 22, where the number of difference between “1” and “0” is tabulated as a function of ∆v; … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … (¶ 0143-0145)];
determine the first read voltage not to be a target read voltage responsive to an absolute value of the difference between the count of the first value and the count of the second value being larger than a preset value [the corresponding “target read voltage” is the “optimal read voltage;” which is determined by the difference between the number of “1” and “0” being less than a reference value -- … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … A shift degree of a distribution valley may be decided by detecting a variation in a relative ratio of logical 1s and logical 0s that are uniformly distributed in read data R_Data, or by detecting an absolute variation in the number of logical 1s or logical 0s … (¶ 0143-0145)]; and
determine the first read voltage to be the target read voltage responsive to the absolute value of the difference between the count number of the first value and the count number of the second value being smaller than or equal to the preset value [the corresponding “target read voltage” is the “optimal read voltage;” which is determined by the difference between the number of “1” and “0” being less than a reference value -- … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … A shift degree of a distribution valley may be decided by detecting a variation in a relative ratio of logical 1s and logical 0s that are uniformly distributed in read data R_Data, or by detecting an absolute variation in the number of logical 1s or logical 0s … (¶ 0143-0145)], wherein the preset value is configured according to an acceptable error rate of read data of the memory system [The memory controller 310 may perform an error detection and correction of the read data R_Data. If an error is not detected or is correctable, a read operation of the selected memory cells may end (Yes). In contrast, if the read data R_Data is uncorrectable (No), the memory controller 310 decides a shift degree of a distribution valley only using the read data R_Data. That is, the memory controller 310 decides a shift degree of a distribution valley based on an increment or decrement of logical 1 or logical 0 of the uncorrectable read data R_Data, or based on a relative ratio of logical 1s to logical 0s of the uncorrectable read data R_Data (¶ 0154)].
Regarding claim 1, Yoon teaches performing error correction operations to correct errors of read data [A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract); The memory controller 110 may perform an error detection and correction on the read data R_Data ... (¶ 0056)], but does not expressively teach doing so using a low density parity check (LDPC) hard decoding.
However, a low density parity check (LDPC) hard decoding is well known and widely used in the art.
For example, Yang specifically teaches performing error correction operations with a low density parity check (LDPC) hard decoding [When the controller 160 reads page data from the flash memory 180 using a read threshold voltage, the retrieved page data is transmitted to the error-correction circuit 168, and the error-correction circuit 168 is configured to perform error correction on the page data, and the error-correction scheme performed by the error-correction circuit 168 can be referred to as hard data decoding. In some embodiments, the error-correction circuit 168 includes a low-density parity-check code (LDPC) error-correction engine (not shown in FIG. 1) and/or a BCH-code error-correction engine (not shown in FIG. 1), but the invention is not limited thereto (¶ 0024-0025)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to perform error correction operations with a low density parity check (LDPC) hard decoding, as specifically demonstrated by Yang, and to incorporate it into the existing scheme disclosed by Yoon, in order to better facilitate error correction operations.
As to claim 3, Yoon in view of Yang teaches The memory system of claim 1, wherein the preset value is in a range of 100 to 300 [Yoon -- as shown in figure 22, where the range of the number of difference between “1” and “0” is tabulated as a function of ∆v, and the difference may range from -5 to 500, thus covering the range from 100 to 300].
As to claim 4, Yoon in view of Yang teaches The memory system of claim 1, wherein each of the memory cells stores one bit of data [Yoon -- as shown in figure 5, where each memory cell stores one bot of data, “1” or “0”; … The nonvolatile memory device 120 may also perform a backup operation on data (e.g., SLC data) corresponding to at least one of a plurality of single level cell (SLC) read operations that are executed during a procedure of reading out the read data R_Data … (¶ 0055-0058)].
As to claim 5, Yoon in view of Yang teaches The memory system of claim 1, wherein the memory controller is configured to: send a second command responsive to an absolute value of the difference between the count of the first values and the count of the second values being larger than a preset value and the count of the first values is larger than the count of the second values, the second command indicating to perform the read operation on the data in the target memory page at a second read voltage [Yoon -- A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data (abstract)], the second read voltage being smaller than the first read voltage [Yoon -- as shown in figure 22, when the ∆v (i.e., the difference between the first and the second read voltages) is negative, the second read voltage is smaller than the first read voltage]; and send a third command responsive to the absolute value of the difference between the count number of the first values and the count number of the second values being larger than the preset value and the count number of the first values is smaller than the count number of the second values, the third command indicating to perform the read operation on the data in the target memory page at a third read voltage, the third read voltage being larger than the first read voltage [Yoon -- as shown in figure 22, when a plurality of ∆v (i.e., the difference between the first and the second read voltages) are applied to the memory cells, in order to reach the optimal read voltage; FIG. 22 is a table schematically illustrating distribution valley detection table 315 shown in FIG. 19, according to an embodiment of the inventive concept. Referring to FIG. 22, distribution valley detection table 315 shows a relation between an increment or decrement of logical 1 and a shift degree of a distribution valley … (¶ 0158-0164)].
As to claim 6, Yoon in view of Yang teaches The memory system of claim 1, wherein the memory controller comprises a register and is configured to: store the first values and the second values read from the target memory page into the register temporarily [Yang -- For example, each time the controller 160 reads page data from the flash memory 180 using the configuration of the read threshold voltage corresponding to each entry in the read-retry table and the error-correction circuit 168 fails to perform error correction on the read page data using hard error decoding, the original read page data (or the calibrated page data) may be recorded in a register or DRAM 166 by the computation unit 162 ... (¶ 0032)]; and count numbers of the first values and the second values using the register [Yoon -- … That is, to decide a location of a distribution valley, the memory controller 310 detects only a difference between logical 1s and logical 0s included in the read data R_Data, a ratio of logical 1s to logical 0s in the read data R_Data, or whether or not the number of logical 1s or logical 0s in the read data R_Data is more than a reference value … A shift degree of a distribution valley may be decided by detecting a variation in a relative ratio of logical 1s and logical 0s that are uniformly distributed in read data R_Data, or by detecting an absolute variation in the number of logical 1s or logical 0s … (¶ 0143-0145)].
As to claim 7, Yoon in view of Yang teaches The memory system of claim 1, wherein the memory page corresponds to a read voltage table that comprises a plurality of read voltages arranged in order from small to large, values of two adjacent read voltages differing by a fixed offset; and the memory controller is configured to: select the read voltage from the read voltage table using a dichotomization method to perform the read operation on the data in the target memory page, responsive to the read operation being performed on the target memory page [Yoon -- as shown in figure 22, when a plurality of ∆v (i.e., the difference between the first and the second read voltages) are applied to the memory cells, in order to reach the optimal read voltage; FIG. 22 is a table schematically illustrating distribution valley detection table 315 shown in FIG. 19, according to an embodiment of the inventive concept. Referring to FIG. 22, distribution valley detection table 315 shows a relation between an increment or decrement of logical 1 and a shift degree of a distribution valley … (¶ 0158-0164)].
As to claim 8, Yoon in view of Yang teaches The memory system of claim 1, wherein the memory system comprises a memory card or a solid-state drive [Yoon -- SSD as shown in figure 24, and memory card as shown in figure 25].
As to claim 9, Yoon in view of Yang teaches The memory system of claim 1, wherein the memory device comprises a memory array and a peripheral circuit coupled with the memory array, and the peripheral circuit is configured to: receive the first command sent from the memory controller; and send the first value and the second value read from the target memory page to the memory controller [Yoon -- the memory device as shown in figure 24, which includes a memory array (1230), and controller (1210); figure 21 shows the read commands and read data communications between the memory controller (310) and the NVM memory (320)].
As to claim 10, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 12, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 13, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 14, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 9, and is rejected for the same reasons set forth in the analysis of claim 9. Refer to “As to claim 9” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 18, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 21, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 22, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
Conclusion
6. Claims 1, 3-10, and 12-22 are rejected as explained above.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
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