Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khlat (US 20210184633 A1, cited by the applicant), hereafter referred to as “Khlat”.
Regarding claim 1, in the embodiment of Fig. 2, Khlat discloses:
A power amplifier circuit (Fig. 2, Doherty amplifier system 10) comprising:
a first amplifier (carrier amplifier 12);
a second amplifier (carrier amplifier 12);
an output terminal (RF signal output 30); and
an impedance conversion circuit (impedance inverter 26) connected to an output end of one of the first amplifier or the second amplifier (main output 16),
wherein the impedance conversion circuit comprises:
a first line (inductor L1) with a first end (left end of L1) connected to the output end (left of L1 is connected to main output 16),
a second line (inductor L2) with a first end (L2 left end) connected to a second end of the first line (right of inductor L1, shown to be connected to the left end of L2), and
a first capacitor (capacitor CBY1) with a first end (left of CBY1) connected to a node between the first line and the second line (middle node 24), and with a second end (right end of CBY1) connected to a reference potential (fixed voltage node connected to right side of CBY1 is connected to ground),
wherein the first line and the second line are coupled to each other (L1 and L2 comprises magnetic coupling K1), and
wherein a signal is output from the output terminal (RF signal output 30), the signal being based on a node (e.g. node 28 or node between 22 and inductor L3) between an output end of another of the first amplifier and the second amplifier (peaking output 22) that is not connected to the impedance conversion circuit and a second end of the second line (right side of L2).
Regarding claim 2, in the embodiment of Fig. 2, Khlat discloses:
wherein the first amplifier and the second amplifier constitute a Doherty amplifier circuit (Doherty amplifier system 10),
wherein one of the first amplifier or the second amplifier is a peak amplifier of the Doherty amplifier circuit (peaking amplifier 18), and
wherein another of the first amplifier and the second amplifier is a carrier amplifier of the Doherty amplifier circuit (carrier amplifier 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 20210184633 A1, cited by the applicant) in view of Dupuy (US 20100207703 A1), hereafter referred to as “Khlat” and “Dupuy”, respectively.
Regarding claims 3-6 and 9-10, in the embodiment of Fig. 2, Khlat discloses:
the impedance conversion circuit and the output terminal (Fig. 2, impedance inverter 26 and RF signal output 30, per claim 3), the first amplifier and the second amplifier (per claim 4), and
wherein an output end of the peak amplifier and an output end of the carrier amplifier are connected via the impedance conversion circuit (as shown in Fig. 1), a node between the output end of the peak amplifier and the output end of the carrier amplifier, and the output terminal (node between 22, inductor L3, and inductor C1), and an amplified signal subjected to a combination of currents is output from the output terminal (current from a fixed voltage node (e.g. ground results in current flowing to inductors L3 and L4 and output to RF signal output 30, per paragraph [0024]-[0025] per claims 9 and 10).
However, Khlat is silent in teaching a harmonic processing circuit, the harmonic processing circuit is a common circuit to the first amplifier and the second amplifier, wherein the harmonic processing circuit is a series resonant circuit comprising a first inductor and a second capacitor that are connected in series, and having one end connected to the reference potential, and the harmonic processing circuit comprises a second capacitor with a first end connected to the reference potential, and the harmonic processing circuit comprises a second capacitor with a first end (bottom end) connected to the reference potential, and the power amplifier circuit further comprises a matching network.
Dupuy teaches:
a harmonic processing circuit (Figs. 1, 1D/1E, and 36B, unit cell 12, FIGS. 1D and 1E illustrates examples of the original CRLH (Composite Right and Left Handed) unit cell in FIG. 1, the CRLH TL can provide capability as a harmonic trap per column [0093] lines 11-13), wherein the harmonic processing circuit is a series resonant circuit (Figs. 1D-1G, show series circuits of the CRLH unit cell are also resonators per paragraph [0062] (page 4)) comprising a first inductor (Inductor LL in Figs 1D/1E) and a second capacitor (capacitor CL in Figs 1D/1E) that are connected in series, and having one end connected to the reference potential (as shown in Figs. 1D/1E), and the harmonic processing circuit comprises a second capacitor (Fig. 1F/1G, capacitors CR and C’R) with a first end (bottom end) connected to the reference potential (capacitors CR and C’R are shown to be connected to ground), the power amplifier circuit further comprises a matching network (Fig. 36B, output matching network (OMN)).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to include the harmonic processing circuit as taught by Dupuy (Figs. 1D-1G and 36B) to be connected as a common circuit to the amplifiers and between the impedance conversion circuit and the output terminal as taught by Khlat (Fig. 2) to create a desired phase response curve (Dupuy, paragraph [0063]), thereby suggesting the obviousness of such a combination. Furthermore, it would been obvious to include a matching network, such as the matching network taught by Dupuy (Fig. 36B) to the output of the power amplifier circuit taught by Khlat (Fig. 2) to match the output impedance of a transistor to the output load so as to maximize the output power transfer (paragraph [0106]), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 7, 8, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 7, 8, and 11:
the cited prior art of record, Khlat (US 20210184633 A1, cited by the applicant), either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
“a fourth capacitor with a first end connected to an output end of the carrier amplifier, and a second inductor, wherein a second end of the third capacitor and a second end of the fourth capacitor are connected to each other, wherein a first end of the second inductor is connected to a node between the second end of the third capacitor and the second end of the fourth capacitor, wherein a second end of the second inductor is connected to the reference potential” per claim 7,
“a fourth inductor with a first end connected to a second end of the third inductor, and a fourth capacitor with a first end connected to a node between the third inductor and the fourth inductor, wherein a second end of the fourth inductor is connected to a power supply potential, wherein a second end of the fourth capacitor is connected to the reference potential” per claim 8, and
“the first pattern and the second pattern overlap when the semiconductor substrate is viewed in a plan view, and wherein a length of a portion of the first and second patterns that overlap is not greater than a quarter of a wavelength of a fundamental frequency” per claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
