DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the RCE and amendment filed on 9/17/2026.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/17/2026 has been entered.
Claims 1 and 14 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran (US 7,023,761), Mazumder (US 2017/0366188), and Chang et al. (US 2024/0355374).
With respect to claim 1, Tran teaches of a voltage-adaptive static random-access memory (SRAM) comprising: at least one-bit SRAM cell (column 1, lines 13-23; SRAM data cells are arranged into an array); and
a memory controller configured to determine operation modes and control voltage to a power rail of the at least one-bit SRAM cell based on an operation mode of the operation modes (fig. 1; column 1, lines 24-28, column 1, lines 33-42, column 2, line 58-column 3, line 61; where the programmable switching control circuit controls the positive and negative supply switches to control the voltage to the cells of the memory groups based on if the memory is in activation mode or retention mode. Where the memory is in activation mode while data is being transferred to and from the memory and the memory is in retention mode when data is not being written to or read from the memory).
Tran fails to explicitly teach of the at least one-bit SRAM cell having address, data and control buses.
However, Mazumder teaches of the at least one-bit SRAM cell having address, data and control buses (fig. 6; paragraphs 33-35; where the SRAM memory array has a command/address/parity data bus and input/output data buffers).
The combination of Tran and Mazumder teaches of wherein the memory controller utilizes a control logic to determine the operation modes based on (i) address, data, and control buses inputs (Tran, fig. 1; column 1, lines 24-28, column 1, lines 32-42; column 2, line 58-column 3, line 61; Mazumder fig. 6; paragraphs 33-35; where in the combination, the memory is in retention mode when data is not being written to or read from the memory and in the activation mode when data is being written to and read from the memory. As when data isn’t being written to or read from the memory, the address, data and control, inputs do not contain signals telling the memory to operate, this suggests to one of ordinary skill in the art that the controller uses the control, address, and data lines of Mazumder to establish whether a R/W operation is occurring or not and thus whether or not the memory is active).
The combination of Tran and Mazumder fails to explicitly teach of wherein the memory controller utilizes a control logic to determine the operation modes based on (ii) a DC supply level available to the voltage-adaptive SRAM.
However, Chang teaches of wherein the memory controller utilizes a control logic to determine the operation modes based on (ii) a DC supply level available to the voltage-adaptive SRAM (paragraph 20, 31; where when provided with a varying supply voltage, the operation modes of the SRAM change accordingly to adjust the read and/or write WL pulse width in real-time).
The combination of Tran, Mazumder, and Chang teaches of wherein the memory controller utilizes a control logic to determine the operation modes based on both (i) address, data, and control buses inputs and (ii) a DC supply level available to the voltage-adaptive SRAM (Tran, fig. 1; column 1, line 24-42; column 2, line 58-column 3, line 61; Mazumder fig. 6; paragraphs 33-35; Chang, paragraph 20, 31; where in the combination, the memory can be in activation mode when data is being written to and read from the memory and in retention mode, when data isn’t being written to and read from the memory as taught in Tran and Mazumder. When a higher supply voltage occurs, it operates in a mode with smaller read and write margins and when a lower supply voltage occurs, it operates in a mode with larger read and write margins as taught in Chang).
Tran and Mazumder are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into Tran. Their motivation would have been to more efficiently access the memory.
Tran, Mazumder, and Chang are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, and Chang before the time of the effective filing of the claimed invention to incorporate the dynamically adjusting the pulse widths based on the supply voltage in the combination of Tran and Mazumder as taught in Chang. Their motivation would have been to ensure both Vmin reliability and Fmax performance in the SRAM (Chang, paragraph 19-20).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, and Chang as applied to claim 1 above, and further in view of Westwick et al. (US 2009/0089599).
With respect to claim 3, Tran teaches of wherein the operation modes comprising an active mode; a retention mode (fig. 1; column 2, line 58-column 3, line 61; where the programmable switching control circuit controls the positive and negative supply switches to control the voltage to the cells of the memory groups based on if the memory is in activation mode or retention mode).
The combination of Tran, Mazumder, and Chang fails to explicitly teach of a brownout mode.
However, Westwick teaches of wherein the operation modes comprising a brownout mode (paragraph 73; where the brownout detector maintains the power management unit in a reset mode when the voltage is not stable and high enough to operate).
Tran, Mazumder, Chang, and Westwick are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, and Westwick before the time of the effective filing of the claimed invention to incorporate the brownout detector of Westwick into the combination of Tran, Mazumder, and Chang. Their motivation would have been to ensure the power is adequate for operation.
Claim(s) 4-6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, and Westwick as applied to claim 3 above, and further in view of Wong et al. (US 2018/0004276).
With respect to claim 4, Tran teaches of wherein the memory controller further comprises: an active-switch; and a retention-switch (fig. 1, 5; column 2, line 58-column 4, line 24; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups between activation and retention modes).
Westwick teaches of wherein the memory controller further comprises: a brownout detector; a safe-mode circuit (fig. 1, 26; paragraph 73, 146-147; brown-out detector and POR circuitry).
The combination of Tran, Mazumder, Chang, and Westwick fails to explicitly teach of wherein the memory controller further comprises: a check-valve.
However, Wong teaches of wherein the memory controller further comprises: a check-valve (paragraph 34, 49; power rail switching circuits).
Tran, Mazumder, Chang, Westwick, and Wong are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, and Wong before the time of the effective filing of the claimed invention to incorporate power switching circuitry of Wong into the combination of Tran, Mazumder, Chang, and Westwick. Their motivation would have been to prevent short circuit conditions when switching the voltage (Wong, paragraph 34).
With respect to claim 5, Tran teaches of wherein in an active-mode the memory controller engages the active-switch for routing a VDDdig voltage to the power rail of the at least one-bit SRAM cell to enable read-write operations (fig. 1, 5; column 2, line 58-column 4, line 24; column 4, lines 35-39; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups to activation mode where the memory groups are coupled to Vdd for reading and writing to the memory).
With respect to claim 6, Tran teaches of wherein in the retention mode the memory controller engages the retention-switch for routing a VDDaon voltage to the power rail of the at least one-bit SRAM cell to conserve energy while retaining vital information and maintaining necessary functionalities in a low DC supply level (fig. 1, 5; column 2, line 58-column 4, line 24; column 5, lines 13-18; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups to retention mode where the memory groups are coupled to the common node with voltage Vcn to retain data in the memory cells with reducing power consumption with a lower voltage potential).
With respect to claim 11, Wong teaches of wherein the check-valve prevent current flowing from the power rail to the DC supply and facilitates low voltage drop between VDDaon and the power rail (fig. 13; paragraph 101-103; where the switching circuit has a switch that is to be placed in the one-way current-flow state such that current is prevented from flowing toward the power supply rail and in the combination, the switching circuit connects a rail to Vcn of Tran to provide the second voltage).
The reasoning for obviousness is the same as indicated above with respect to claim 4.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, Westwick, and Wong as applied to claim 4 above, and further in view of Cheng et al. (US 2013/0094307).
With respect to claim 7, the combination of Tran, Mazumder, Chang, Westwick, and Wong fails to explicitly teach of wherein in a brownout-mode the memory controller blocks the at least one-bit SRAM cell to prevent current leakage and inhibit inrush current through the at least one-bit SRAM cell.
However, Cheng teaches of wherein in a brownout-mode the memory controller blocks the at least one-bit SRAM cell to prevent current leakage and inhibit inrush current through the at least one-bit SRAM cell (paragraph 7, 15, 47; where the bit lines for the cells are coupled together when in low power mode to eliminate current leakage and inrush current when switching out of low power mode).
Tran, Mazumder, Chang, Westwick, Wong, and Cheng are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, Wong, and Cheng before the time of the effective filing of the claimed invention to incorporate the tying the bit lines of the cells together when in low power mode in the combination of Tran, Mazumder, Chang, Westwick, and Wong as taught in Cheng. Their motivation would have been to eliminate current leakage (Cheng, paragraph 5).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, Westwick, and Wong as applied to claim 4 above, and further in view of Deng et al. (US 2005/0128852).
With respect to claim 9, Westwick teaches of wherein the brownout detector together with the safe mode circuit are configured to detect an unsafe voltage threshold (fig. 1, 26; paragraph 73, 146-147; brown-out detector and POR circuitry determines if the voltage supply is stable and at a level required to operate).
The combination of Tran, Mazumder, Chang, Westwick, and Wong fails to explicitly teach of wherein the brownout detector together with the safe mode circuit isolate a memory data bus once the threshold surpassed.
However, Deng teaches of wherein the brownout detector together with the safe mode circuit isolate a memory data bus once the threshold surpassed (paragraph 11, 14-15; where in sleep mode, the bit lines are isolated).
Tran, Mazumder, Chang, Westwick, Wong, and Deng are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, Wong, and Deng before the time of the effective filing of the claimed invention to incorporate the isolation of the bit lines when in low power mode in the combination of Tran, Mazumder, Chang, Westwick, and Wong as taught in Deng. Their motivation would have been to eliminate current leakage.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, Westwick, and Wong as applied to claim 4 above, and further in view of Rai (US 2014/0036612).
With respect to claim 10, the combination of Tran, Mazumder, Chang, Westwick, and Wong fails to explicitly teach of wherein the memory controller further comprises a memory unsafe circuit facilitates memory retention at a DC supply level below 200 millivolts.
However, Rai teaches of wherein the memory controller further comprises a memory unsafe circuit facilitates memory retention at a DC supply level below 200 millivolts (fig. 3; paragraph 15; where the SRAM has a data retention voltage of 150 mV, thus the memory circuitry facilitates memory retention at a voltage level below 200 mV).
Tran, Mazumder, Chang, Westwick, Wong, and Rai are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, Wong, and Rai before the time of the effective filing of the claimed invention to incorporate the retention of data with a voltage of 150 mV in the SRAM of the combination of Tran, Mazumder, Chang, Westwick, and Wong as taught in Rai. Their motivation would have been to keep the stored data valid utilizing less power.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, and Chang as applied to claim 1 above, and further in view of Bashir et al. (US 2016/0099720).
With respect to claim 21, the combination of Tran, Mazumder, and Chang fails to explicitly teach of wherein the DC supply level available to the voltage-adaptive SRAM is provided by a power supply based on radio frequency (RF) energy harvester.
However, Bashir teaches of wherein the DC supply level available to the voltage-adaptive SRAM is provided by a power supply based on radio frequency (RF) energy harvester (fig. 19; paragraph 115, 117; where the energy management circuitry converts energy from the energy harvester harvesting RF energy from the environment into voltage levels required by the circuitry. In the combination with Tran, Mazumder, and Chang, the power is supplied to the SRAM).
Tran, Mazumder, Chang, and Bashir are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, and Bashir before the time of the effective filing of the claimed invention to incorporate the harvesting of energy from the environment to power the circuitry of the combination of Tran, Mazumder, and Chang as taught in Bashir. Their motivation would have been to more efficiently power the memory.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir, Tran, Mazumder, Chang, and Westwick.
With respect to claim 14, Bashir teaches of an Internet of things (loT) device, comprising: a system-on-a-chip (SoC) (fig. 19; paragraph 114-115; the IOT node is integrated as a SOC);
a transceiver supporting a short-range communication protocol for communicating with other loT devices (fig. 19; paragraph 115-117; where the transceiver uses the antenna to communicate with the other IOT nodes using a communication standard); and
a power supply based on radio frequency (RF) energy harvester (fig. 19; paragraph 115, 117; where the energy management circuitry converts energy from the energy harvester harvesting RF energy from the environment into voltage levels required by the circuitry);
wherein the SoC comprising: a processor; an input and output module (fig. 19; paragraph 114-115, 117; application processor, sensors and actuators that interact with the environment).
Bashir fails to explicitly teach of a voltage-adaptive static random-access memory (SRAM) comprising: at least one-bit SRAM cell having address, data and control buses; and a memory controller configured to determine operation modes and control voltage to a power rail of the at least one-bit SRAM cell based on an operation mode of the operation modes; wherein the memory controller utilizes a control logic to determine the operation modes based on both (i) address, data, and control buses inputs and (ii) a DC supply level available to the SoC, and wherein the operation modes comprising an active mode; a retention mode; and a brownout mode.
However, the combination of Tran, Mazumder, Chang, and Westwick teaches of the limitations cited and described above with respect to claims 1 and 3 for the same reasoning as detailed with respect to claims 1 and 3.
Bashir, Tran, Mazumder, Chang, and Westwick are analogous art because they are from the same field of endeavor, as they involve memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir and Tran before the time of the effective filing of the claimed invention to incorporate the programmable switching SRAM of Tran into Bashir. Their motivation would have been to more efficiently operate the memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into the combination of Tran and Bashir. Their motivation would have been to more efficiently access the memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, and Chang before the time of the effective filing of the claimed invention to incorporate the dynamically adjusting the pulse widths based on the supply voltage in the combination of Bashir, Tran and Mazumder as taught in Chang. Their motivation would have been to ensure both Vmin reliability and Fmax performance in the SRAM (Chang, paragraph 19-20).
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, Chang, and Westwick before the time of the effective filing of the claimed invention to incorporate the brownout detector of Westwick into the combination of Bashir, Tran, Mazumder, and Chang. Their motivation would have been to ensure the power is adequate for operation.
Claim(s) 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir, Tran, Mazumder, Chang, and Westwick as applied to claim 14 above, and further in view of Wong.
With respect to claims 15-17 and 20, the combination of Bashir, Tran, Mazumder, Chang, Westwick, and Wong teaches of the limitations cited and described in claims 4-6 and 11 for the same reasoning as described above with respect to claims 4-6 and 11.
Bashir, Tran, Mazumder, Chang, Westwick, and Wong are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, Chang, Westwick, and Wong before the time of the effective filing of the claimed invention to incorporate power switching circuitry of Wong into the combination of Bashir, Tran, Mazumder, and Westwick. Their motivation would have been to prevent short circuit conditions when switching the voltage (Wong, paragraph 34).
Allowable Subject Matter
Claims 8 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 8 and 18, the prior art of Nakai et al. (US 2008/0291754) discloses setting control signals to a high level/Vcc when the SRAM is in standby mode to reduce standby current in paragraph 28. However, this is not maintaining the address, data, and control busses at a logic zero as described in the claims.
With respect to claim 8, the prior art does not teach or suggest, “wherein the address, data and control buses are maintained at a logic zero in a brownout mode,” in the context of the claim.
With respect to claim 18, the prior art does not teach or suggest, “wherein in a brownout-mode…the address, data and control buses are maintained at a logic zero,” in the context of the claim.
Response to Arguments
Applicant's arguments filed 9/17/2026 have been fully considered but they are not persuasive.
Applicant argues with respect to independent claim 1, that the combination of Tran and Mazumder does not teach of wherein the memory controller utilizes a control logic to determine the operation modes based on address, data, and control buses inputs. The examiner disagrees.
Tran discloses in column 1, lines 24-28 and lines 33-42 that the memory is considered to be in activation mode while data is being transferred to and from the memory array and the memory is considered to be in retention mode when data is not being written to or read from the memory array. Mazumder discloses in figure 6 and paragraphs 33-35 that the SRAM array has a command/address/parity data bus and input/output data buffers that make up an input/output data bus. Therefore in the combination, when Tran indicates that the presence or absence of writing data to or reading data from the memory determines the mode it is in, since these command/data/address signals would reach the controller over the appropriate busses, the activities or lack thereof generated by the signals on the bus determine the memory’s mode. Thus the combination of Tran and Mazumder read on the limitation at issue.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the occurrence of an inspection operation on the command, address, and data busses) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant also alleges that Mazumder teaches away from being combined with Tran as Mazumder appears to teach of using a supply voltage with an unchanging and always available level. The examiner disagrees.
In order for a reference to each away, "the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." See MPEP 2145(X)(D)(1) and MPEP 2141.02(VI). While Mazumder may imply the use of a supply voltage that is unchanging, it does not criticize, discredit, or otherwise discourage the use of other supply voltages including those that may be variable. Thus, Mazumder does not teach away from the claimed invention. The combination including the application of Mazumder is proper.
Applicant argues with respect to independent claim 1 that the combination of Tran, Mazumder, and Chang does not teach of, “wherein the memory controller utilizes a control logic to determine the operation modes based on both (i) address, data, and control buses inputs and (ii) a DC supply level available to the voltage-adaptive SRAM,” as the application of Tran and Mazumder the claim teaches determining the operation modes based on address, data, and control buses inputs while Chang teaches determining the operation modes based on a DC supply level available to the voltage-adaptive SRAM. Thus, the combination cannot teach of the mode being determined using both address, data, and control buses inputs and a DC supply level available to the voltage-adaptive SRAM. The examiner disagrees with this reasoning.
As written, claim 1 generically states that the memory controller determines “operation modes” stating, “wherein the memory controller utilizes a control logic to determine the operation modes based on both (i) address, data, and control buses inputs and (ii) a DC supply level available to the voltage-adaptive SRAM.” This indicates that the controller determines a plural amount of operation modes and uses both address, data, and control buses inputs as well as a DC supply level available to the voltage-adaptive SRAM in it’s process. The claims do NOT require that a particular single mode be determined by using both the address, data, and control buses inputs and the a DC supply level available to the voltage-adaptive SRAM as the applicant appears to argues on pages 9-10 of the remarks filed on 9/17/2026. The way the claims are written, they allow for one mode of the claimed operation modes to be determined by using the address, data, and control buses inputs and another mode of the claimed operation modes to be determined, thus when viewed as a collective (operation modes) as claimed, the operation modes are determined by the memory controller based on “both (i) address, data, and control buses inputs and (ii) a DC supply level available to the voltage-adaptive SRAM.”
Therefore, as described above the combination of Tran, Mazumder, and Chang discloses that Tran’s SRAM is in activation mode when data is being written to and read from the memory and is in retention mode when data isn’t being written to and read from the memory, see Tran figure 1 and column 1, line 32-40; column 2, line 58-column 3, line 61. The controller is able to determine this as it receives those read/write signals via the command, address, and data busses taught in Mazumder in figure 6 and paragraphs 33-35. As disclosed in Chang, when a higher supply voltage occurs, the memory operates in a mode with smaller read and write margins and when a lower supply voltage occurs, the memory operates in a mode with larger read and write margins, see Chang paragraph 20 and 31. Therefore, the combination of Tran, Mazumder, and Chang reads on the claim limitations as written.
The examiner encourages the applicant to clarify this issue in the claims by stating “wherein the memory controller utilizes a control logic to determine each operation mode of the operation modes based on both (i) address, data, and control buses inputs and (ii) a DC supply level available to the voltage-adaptive SRAM,” or “wherein the memory controller utilizes a control logic to determine one single operation mode of the operation modes based on both (i) address, data, and control buses inputs and (ii) a DC supply level available to the voltage-adaptive SRAM,” or using any other analogous language.
The examiner also encourages the applicant to describe how the address, data, and control buses inputs and the DC supply level available to the voltage-adaptive SRAM interact together in the memory controller’s determination for an operation mode to distinguish between the applicant’s invention and the prior art.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Tran and Mazumder are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into Tran. Their motivation would have been to more efficiently access the memory.
Tran, Mazumder, and Chang are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, and Chang before the time of the effective filing of the claimed invention to incorporate the dynamically adjusting the pulse widths based on the supply voltage in the combination of Tran and Mazumder as taught in Chang. Their motivation would have been to ensure both Vmin reliability and Fmax performance in the SRAM (Chang, paragraph 19-20).
Thus the combination of Tran, Mazumder, and Chang is proper.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Boehm et al. (US 2020/0341847) discloses an event detection circuit that detects events that could cause a loss of data integrity such as insufficient voltage supply or an error condition for a channel of a bus among many other things and adjusting the mode of operation of the memory device in response to these events.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
