DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 4/1/2026.
Claim 2, and 12-13 have been cancelled.
New claim 21 has been added and examined.
The title and claims 1, 3, 10, 14, and 19 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran (US 7,023,761), Mazumder (US 2017/0366188), and Chang et al. (US 2024/0355374).
With respect to claim 1, Tran teaches of a voltage-adaptive static random-access memory (SRAM) comprising: at least one-bit SRAM cell (column 1, lines 13-23; SRAM data cells are arranged into an array); and
a memory controller configured to determine operation modes and control voltage to a power rail of the at least one-bit SRAM cell based on an operation mode of the operation modes (fig. 1; column 2, line 58-column 3, line 61; where the programmable switching control circuit controls the positive and negative supply switches to control the voltage to the cells of the memory groups based on if the memory is in activation mode or retention mode).
Tran fails to explicitly teach of the at least one-bit SRAM cell having address, data and control buses.
However, Mazumder teaches of the at least one-bit SRAM cell having address, data and control buses (fig. 6; paragraphs 33-35; where the SRAM memory array having a command/address/parity data bus and input/output data buffers).
The combination of Tran and Mazumder teaches of wherein the memory controller utilizes a control logic to determine the operation modes based on (i) address, data, and control buses inputs (Tran, fig. 1; column 1, line 32-40; column 2, line 58-column 3, line 61; Mazumder fig. 6; paragraphs 33-35; where in the combination, the memory is in retention mode when data is not being written to or read from the memory and in the activation mode when data is being written to and read from the memory. As when data isn’t being written to or read from the memory, the address, data and control, inputs do not contain signals telling the memory to operate, this suggests to one of ordinary skill in the art that the controller uses the control, address, and data lines of Mazumder to establish whether a R/W operation is occurring or not).
The combination of Tran and Mazumder fails to explicitly teach of wherein the memory controller utilizes a control logic to determine the operation modes based on (ii) a DC supply level available to the voltage-adaptive SRAM.
However, Chang teaches of wherein the memory controller utilizes a control logic to determine the operation modes based on (ii) a DC supply level available to the voltage-adaptive SRAM (paragraph 20, 31; where when provided with a varying supply voltage, the operation modes of the SRAM change accordingly to adjust the read and/or write WL pulse width in real-time).
Tran and Mazumder are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into Tran. Their motivation would have been to more efficiently access the memory.
Tran, Mazumder, and Chang are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, and Chang before the time of the effective filing of the claimed invention to incorporate the dynamically adjusting the pulse widths based on the supply voltage in the combination of Tran and Mazumder as taught in Chang. Their motivation would have been to more ensure both Vmin reliability and Fmax performance in the SRAM (Chang, paragraph 19-20).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, and Chang as applied to claim 1 above, and further in view of Westwick et al. (US 2009/0089599).
With respect to claim 3, Tran teaches of wherein the operation modes comprising an active mode; a retention mode (fig. 1; column 2, line 58-column 3, line 61; where the programmable switching control circuit controls the positive and negative supply switches to control the voltage to the cells of the memory groups based on if the memory is in activation mode or retention mode).
The combination of Tran, Mazumder, and Chang fails to explicitly teach of a brownout mode.
However, Westwick teaches of wherein the operation modes comprising a brownout mode (paragraph 73; where the brownout detector maintains the power management unit in a reset mode when the voltage is not stable and high enough to operate).
Tran, Mazumder, Chang, and Westwick are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, and Westwick before the time of the effective filing of the claimed invention to incorporate the brownout detector of Westwick into the combination of Tran, Mazumder, and Chang. Their motivation would have been to ensure the power is adequate for operation.
Claim(s) 4-6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, and Westwick as applied to claim 3 above, and further in view of Wong et al. (US 2018/0004276).
With respect to claim 4, Tran teaches of wherein the memory controller further comprises: an active-switch; and a retention-switch (fig. 1, 5; column 2, line 58-column 4, line 24; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups between activation and retention modes).
Westwick teaches of wherein the memory controller further comprises: a brownout detector; a safe-mode circuit (fig. 1, 26; paragraph 73, 146-147; brown-out detector and POR circuitry).
The combination of Tran, Mazumder, Chang, and Westwick fails to explicitly teach of wherein the memory controller further comprises: a check-valve.
However, Wong teaches of wherein the memory controller further comprises: a check-valve (paragraph 34, 49; power rail switching circuits).
Tran, Mazumder, Chang, Westwick, and Wong are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, and Wong before the time of the effective filing of the claimed invention to incorporate power switching circuitry of Wong into the combination of Tran, Mazumder, Chang, and Westwick. Their motivation would have been to prevent short circuit conditions when switching the voltage (Wong, paragraph 34).
With respect to claim 5, Tran teaches of wherein in an active-mode the memory controller engages the active-switch for routing a VDDdig voltage to the power rail of the at least one-bit SRAM cell to enable read-write operations (fig. 1, 5; column 2, line 58-column 4, line 24; column 4, lines 35-39; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups to activation mode where the memory groups are coupled to Vdd for reading and writing to the memory).
With respect to claim 6, Tran teaches of wherein in the retention mode the memory controller engages the retention-switch for routing a VDDaon voltage to the power rail of the at least one-bit SRAM cell to conserve energy while retaining vital information and maintaining necessary functionalities in a low DC supply level (fig. 1, 5; column 2, line 58-column 4, line 24; column 5, lines 13-18; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups to retention mode where the memory groups are coupled to the common node with voltage Vcn to retain data in the memory cells with reducing power consumption with a lower voltage potential).
With respect to claim 11, Wong teaches of wherein the check-valve prevent current flowing from the power rail to the DC supply and facilitates low voltage drop between VDDaon and the power rail (fig. 13; paragraph 101-103; where the switching circuit has a switch that is to be placed in the one-way current-flow state such that current is prevented from flowing toward the power supply rail and in the combination, the switching circuit connects a rail to Vcn of Tran to provide the second voltage).
The reasoning for obviousness is the same as indicated above with respect to claim 4.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, Westwick, and Wong as applied to claim 4 above, and further in view of Cheng et al. (US 2013/0094307).
With respect to claim 7, the combination of Tran, Mazumder, Chang, Westwick, and Wong fails to explicitly teach of wherein in a brownout-mode the memory controller blocks the at least one-bit SRAM cell to prevent current leakage and inhibit inrush current through the at least one-bit SRAM cell.
However, Cheng teaches of wherein in a brownout-mode the memory controller blocks the at least one-bit SRAM cell to prevent current leakage and inhibit inrush current through the at least one-bit SRAM cell (paragraph 7, 15, 47; where the bit lines for the cells are coupled together when in low power mode to eliminate current leakage and inrush current when switching out of low power mode).
Tran, Mazumder, Chang, Westwick, Wong, and Cheng are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, Wong, and Cheng before the time of the effective filing of the claimed invention to incorporate the tying the bit lines of the cells together when in low power mode in the combination of Tran, Mazumder, Chang, Westwick, and Wong as taught in Cheng. Their motivation would have been to eliminate current leakage (Cheng, paragraph 5).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, Westwick, and Wong as applied to claim 4 above, and further in view of Deng et al. (US 2005/0128852).
With respect to claim 9, Westwick teaches of wherein the brownout detector together with the safe mode circuit are configured to detect an unsafe voltage threshold (fig. 1, 26; paragraph 73, 146-147; brown-out detector and POR circuitry determines if the voltage supply is stable and at a level required to operate).
The combination of Tran, Mazumder, Chang, Westwick, and Wong fails to explicitly teach of wherein the brownout detector together with the safe mode circuit isolate a memory data bus once the threshold surpassed.
However, Deng teaches of wherein the brownout detector together with the safe mode circuit isolate a memory data bus once the threshold surpassed (paragraph 11, 14-15; where in sleep mode, the bit lines are isolated).
Tran, Mazumder, Chang, Westwick, Wong, and Deng are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, Wong, and Deng before the time of the effective filing of the claimed invention to incorporate the isolation of the bit lines when in low power mode in the combination of Tran, Mazumder, Chang, Westwick, and Wong as taught in Deng. Their motivation would have been to eliminate current leakage.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Chang, Westwick, and Wong as applied to claim 4 above, and further in view of Rai (US 2014/0036612).
With respect to claim 10, the combination of Tran, Mazumder, Chang, Westwick, and Wong fails to explicitly teach of wherein the memory controller further comprises a memory unsafe circuit facilitates memory retention at a DC supply level below 200 millivolts.
However, Rai teaches of wherein the memory controller further comprises a memory unsafe circuit facilitates memory retention at a DC supply level below 200 millivolts (fig. 3; paragraph 15; where the SRAM has a data retention voltage of 150 mV, thus the memory circuitry facilitates memory retention at a voltage level below 200 mV).
Tran, Mazumder, Chang, Westwick, Wong, and Rai are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, Westwick, Wong, and Rai before the time of the effective filing of the claimed invention to incorporate the retention of data with a voltage of 150 mV in the SRAM of the combination of Tran, Mazumder, Chang, Westwick, and Wong as taught in Rai. Their motivation would have been to keep the stored data valid utilizing less power.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, and Chang as applied to claim 1 above, and further in view of Bashir et al. (US 2016/0099720).
With respect to claim 21, the combination of Tran, Mazumder, and Chang fails to explicitly teach of wherein the DC supply level available to the voltage-adaptive SRAM is provided by a power supply based on radio frequency (RF) energy harvester.
However, Bashir teaches of wherein the DC supply level available to the voltage-adaptive SRAM is provided by a power supply based on radio frequency (RF) energy harvester (fig. 19; paragraph 115, 117; where the energy management circuitry converts energy from the energy harvester harvesting RF energy from the environment into voltage levels required by the circuitry. In the combination with Tran, Mazumder, and Chang, the power is supplied to the SRAM).
Tran, Mazumder, Chang, and Bashir are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Chang, and Bashir before the time of the effective filing of the claimed invention to incorporate the harvesting of energy from the environment to power the circuitry of the combination of Tran, Mazumder, and Chang as taught in Bashir. Their motivation would have been to more efficiently power the memory.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir, Tran, Mazumder, Chang, and Westwick.
With respect to claim 14, Bashir teaches of an Internet of things (loT) device, comprising: a system-on-a-chip (SoC) (fig. 19; paragraph 114-115; the IOT node is integrated as a SOC);
a transceiver supporting a short-range communication protocol for communicating with other loT devices (fig. 19; paragraph 115-117; where the transceiver uses the antenna to communicate with the other IOT nodes using a communication standard); and
a power supply based on radio frequency (RF) energy harvester (fig. 19; paragraph 115, 117; where the energy management circuitry converts energy from the energy harvester harvesting RF energy from the environment into voltage levels required by the circuitry);
wherein the SoC comprising: a processor; an input and output module (fig. 19; paragraph 114-115, 117; application processor, sensors and actuators that interact with the environment).
Bashir fails to explicitly teach of a voltage-adaptive static random-access memory (SRAM) comprising: at least one-bit SRAM cell having address, data and control buses; and a memory controller configured to determine operation modes and control voltage to a power rail of the at least one-bit SRAM cell based on an operation mode of the operation modes; wherein the memory controller utilizes a control logic to determine the operation modes based on (i) address, data, and control buses inputs and (ii) a DC supply level available to the SoC, and wherein the operation modes comprising an active mode; a retention mode; and a brownout mode.
However, the combination of Tran, Mazumder, Chang, and Westwick teaches of the limitations cited and described above with respect to claims 1 and 3 for the same reasoning as detailed with respect to claims 1 and 3.
Bashir, Tran, Mazumder, Chang, and Westwick are analogous art because they are from the same field of endeavor, as they involve memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir and Tran before the time of the effective filing of the claimed invention to incorporate the programmable switching SRAM of Tran into Bashir. Their motivation would have been to more efficiently operate the memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into the combination of Tran and Bashir. Their motivation would have been to more efficiently access the memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, and Chang before the time of the effective filing of the claimed invention to incorporate the dynamically adjusting the pulse widths based on the supply voltage in the combination of Bashir, Tran and Mazumder as taught in Chang. Their motivation would have been to more ensure both Vmin reliability and Fmax performance in the SRAM (Chang, paragraph 19-20).
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, Chang, and Westwick before the time of the effective filing of the claimed invention to incorporate the brownout detector of Westwick into the combination of Bashir, Tran, Mazumder, and Chang. Their motivation would have been to ensure the power is adequate for operation.
Claim(s) 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir, Tran, Mazumder, Chang, and Westwick as applied to claim 14 above, and further in view of Wong.
With respect to claims 15-17 and 20, the combination of Bashir, Tran, Mazumder, Chang, Westwick, and Wong teaches of the limitations cited and described in claims 4-6 and 11 for the same reasoning as described above with respect to claims 4-6 and 11.
Bashir, Tran, Mazumder, Chang, Westwick, and Wong are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, Chang, Westwick, and Wong before the time of the effective filing of the claimed invention to incorporate power switching circuitry of Wong into the combination of Bashir, Tran, Mazumder, and Westwick. Their motivation would have been to prevent short circuit conditions when switching the voltage (Wong, paragraph 34).
Allowable Subject Matter
Claims 8 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 8 and 18, the prior art of Nakai et al. (US 2008/0291754) discloses setting control signals to a high level/Vcc when the SRAM is in standby mode to reduce standby current in paragraph 28. However, this is not maintaining the address, data, and control busses at a logic zero as described in the claims.
With respect to claim 8, the prior art does not teach or suggest, “wherein the address, data and control buses are maintained at a logic zero in a brownout mode,” in the context of the claim.
With respect to claim 18, the prior art does not teach or suggest, “wherein in a brownout-mode…the address, data and control buses are maintained at a logic zero,” in the context of the claim.
Response to Arguments
Applicant's arguments with respect to independent claims 1 and 14 have been considered but are moot because of the new reference(s) being applied, in light of the amendment, to the particular limitations the arguments are referencing. Thereby the arguments no longer apply to the rejection.
Applicant's arguments filed 4/1/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that as Tran is significantly older than Mazumder, Tran cannot use anything disclosed by Mazumder, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument based upon the age of the references, contentions that the reference patents are old are not impressive absent a showing that the art tried and failed to solve the same problem notwithstanding its presumed knowledge of the references. See In re Wright, 569 F.2d 1124, 193 USPQ 332 (CCPA 1977).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
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