DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 18/405,412 filed on 1/5/2024.
Claims 1-20 have been examined.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 10 and 19 both recite the limitation "the memory unsafe circuit" in lines 1 and 3 respectively. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(1), (a)(2) as being anticipated by Bashir et al. (US 2016/0099720).
With respect to claim 12, Bashir teaches of an Internet of things (loT) device, comprising: a system-on-a-chip (SoC) (fig. 19; paragraph 114-115; the IOT node is integrated as a SOC);
a transceiver supporting a short-range communication protocol for communicating with other loT devices (fig. 19; paragraph 115-117; where the transceiver uses the antenna to communicate with the other IOT nodes using a communication standard); and
a power supply based on radio frequency (RF) energy harvester (fig. 19; paragraph 115, 117; where the energy management circuitry converts energy from the energy harvester harvesting RF energy from the environment into voltage levels required by the circuitry).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran (US 71023,761) and Mazumder (US 2017/0366188).
With respect to claim 1, Tran teaches of a voltage-adaptive static random-access memory (SRAM) comprising: at least one-bit SRAM cell (column 1, lines 13-23; SRAM data cells are arranged into an array); and
a memory controller configured to determine operation modes and control voltage to a power rail of the at least one-bit SRAM cell based on an operation mode of the operation modes (fig. 1; column 2, line 58-column 3, line 61; where the programmable switching control circuit controls the positive and negative supply switches to control the voltage to the cells of the memory groups based on if the memory is in activation mode or retention mode).
Tran fails to explicitly teach of the at least one-bit SRAM cell having address, data and control buses.
However, Mazumder teaches of the at least one-bit SRAM cell having address, data and control buses (fig. 6; paragraphs 33-35; where the SRAM memory array having a command/address/parity data bus and input/output data buffers).
Tran and Mazumder are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into Tran. Their motivation would have been to more efficiently access the memory.
With respect to claim 2 the combination of Tran and Mazumder teaches of wherein the memory controller utilizes a control logic to determine the operation modes based on address, data, and control buses inputs (Tran, fig. 1; column 1, line 32-40; column 2, line 58-column 3, line 61; Mazumder fig. 6; paragraphs 33-35; where in the combination, as the memory is in retention mode when data is not being written to or read from the memory and in the activation mode when data is being written to and read from the memory, this suggests to one of ordinary skill in the art that the controller uses the control, address, and data lines of Mazumder to establish whether a R/W operation is occurring or not); and
a DC supply level available to the voltage-adaptive SRAM (Tran, fig. 1; column 2, line 58-column 3, line 61; where Vdd is available as the positive voltage rail).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran and Mazumder as applied to claim 2 above, and further in view of Westwick et al. (US 2009/0089599).
With respect to claim 3, Tran teaches of wherein the operation modes comprising an active mode; a retention mode (fig. 1; column 2, line 58-column 3, line 61; where the programmable switching control circuit controls the positive and negative supply switches to control the voltage to the cells of the memory groups based on if the memory is in activation mode or retention mode).
Tran fails to explicitly teach of a brownout mode.
However, Westwick teaches of wherein the operation modes comprising a brownout mode (paragraph 73; where the brownout detector maintains the power management unit in a reset mode when the voltage is not stable and high enough to operate).
Tran, Mazumder, and Westwick are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, and Westwick before the time of the effective filing of the claimed invention to incorporate the brownout detector of Westwick into the combination of Tran and Mazumder. Their motivation would have been to ensure the power is adequate for operation.
Claim(s) 4-6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, and Westwick as applied to claim 3 above, and further in view of Wong et al. (US 2018/0004276).
With respect to claim 4, Tran teaches of wherein the memory controller further comprises: an active-switch; and a retention-switch (fig. 1, 5; column 2, line 58-column 4, line 24; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups between activation and retention modes).
Westwick teaches of wherein the memory controller further comprises: a brownout detector; a safe-mode circuit (fig. 1, 26; paragraph 73, 146-147; brown-out detector and POR circuitry).
The combination of Tran, Mazumder, and Westwick fails to explicitly teach of wherein the memory controller further comprises: a check-valve.
However, Wong teaches of wherein the memory controller further comprises: a check-valve (paragraph 34, 49; power rail switching circuits).
Tran, Mazumder, Westwick, and Wong are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Westwick, and Wong before the time of the effective filing of the claimed invention to incorporate power switching circuitry of Wong into the combination of Tran, Mazumder, and Westwick. Their motivation would have been to prevent short circuit conditions when switching the voltage (Wong, paragraph 34).
With respect to claim 5, Tran teaches of wherein in an active-mode the memory controller engages the active-switch for routing a VDDdig voltage to the power rail of the at least one-bit SRAM cell to enable read-write operations (fig. 1, 5; column 2, line 58-column 4, line 24; column 4, lines 35-39; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups to activation mode where the memory groups are coupled to Vdd for reading and writing to the memory).
With respect to claim 6, Tran teaches of wherein in the retention mode the memory controller engages the retention-switch for routing a VDDaon voltage to the power rail of the at least one-bit SRAM cell to conserve energy while retaining vital information and maintaining necessary functionalities in a low DC supply level (fig. 1, 5; column 2, line 58-column 4, line 24; column 5, lines 13-18; column 6, line 29-column 7, line 33; where the positive and negative supply switches are used to switch the memory groups to retention mode where the memory groups are coupled to the common node with voltage Vcn to retain data in the memory cells with reducing power consumption with a lower voltage potential).
With respect to claim 11, Wong teaches of wherein the check-valve prevent current flowing from the power rail to the DC supply and facilitates low voltage drop between VDDaon and the power rail (fig. 13; paragraph 101-103; where the switching circuit has a switch that is to be placed in the one-way current-flow state such that current is prevented from flowing toward the power supply rail and in the combination, the switching circuit connects a rail to Vcn of Tran to provide the second voltage).
The reasoning for obviousness is the same as indicated above with respect to claim 4.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Westwick, and Wong as applied to claim 4 above, and further in view of Cheng et al. (US 2013/0094307).
With respect to claim 7, the combination of Tran, Mazumder, Westwick, and Wong fails to explicitly teach of wherein in a brownout-mode the memory controller blocks the at least one-bit SRAM cell to prevent current leakage and inhibit inrush current through the at least one-bit SRAM cell.
However, Cheng teaches of wherein in a brownout-mode the memory controller blocks the at least one-bit SRAM cell to prevent current leakage and inhibit inrush current through the at least one-bit SRAM cell (paragraph 7, 15, 47; where the bit lines for the cells are coupled together when in low power mode to eliminate current leakage and inrush current when switching out of low power mode).
Tran, Mazumder, Westwick, Wong, and Cheng are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Westwick, Wong, and Cheng before the time of the effective filing of the claimed invention to incorporate the tying the bit lines of the cells together when in low power mode in the combination of Tran, Mazumder, Westwick, and Wang as taught in Cheng. Their motivation would have been to eliminate current leakage (Cheng, paragraph 5).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Westwick, and Wong as applied to claim 4 above, and further in view of Deng et al. (US 2005/0128852).
With respect to claim 9, Westwick teaches of wherein the brownout detector together with the safe mode circuit are configured to detect an unsafe voltage threshold (fig. 1, 26; paragraph 73, 146-147; brown-out detector and POR circuitry determines if the voltage supply is stable and at a level required to operate).
The combination of Tran, Mazumder, Westwick, and Wong fails to explicitly teach of wherein the brownout detector together with the safe mode circuit isolate a memory data bus once the threshold surpassed.
However, Deng teaches of wherein the brownout detector together with the safe mode circuit isolate a memory data bus once the threshold surpassed (paragraph 11, 14-15; where in sleep mode, the bit lines are isolated).
Tran, Mazumder, Westwick, Wong, and Deng are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Westwick, Wong, and Deng before the time of the effective filing of the claimed invention to incorporate the isolation of the bit lines when in low power mode in the combination of Tran, Mazumder, Westwick, and Wang as taught in Deng. Their motivation would have been to eliminate current leakage.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Mazumder, Westwick, and Wong as applied to claim 4 above, and further in view of Rai (US 2014/0036612).
With respect to claim 10, the combination of Tran, Mazumder, Westwick, and Wong fails to explicitly teach of wherein the memory unsafe circuit facilitates memory retention at a DC supply level below 200 millivolts.
However, Rai teaches of wherein the memory unsafe circuit facilitates memory retention at a DC supply level below 200 millivolts (fig. 3; paragraph 15; where the SRAM has a data retention voltage of 150 mV, thus the memory circuitry facilitates memory retention at a voltage level below 200 mV).
Tran, Mazumder, Westwick, Wong, and Rai are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Tran, Mazumder, Westwick, Wong, and Rai before the time of the effective filing of the claimed invention to incorporate the retention of data with a voltage of 150 mV in the SRAM of the combination of Tran, Mazumder, Westwick, and Wang as taught in Rai. Their motivation would have been to keep the stored data valid utilizing less power.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir as applied to claim 12 above, and further in view of Tran and Mazumder.
With respect to claim 13, Bashir teaches of wherein the SoC comprising: a processor; an input and output module (fig. 19; paragraph 114-115, 117; application processor, sensors and actuators that interact with the environment).
Bashir fails to explicitly teach of a voltage-adaptive static random-access memory (SRAM) comprising: at least one-bit SRAM cell having address, data and control buses; and a memory controller configured to determine operation modes and control voltage to a power rail of the at least one-bit SRAM cell based on an operation mode of the operation modes.
However, the combination of Tran and Mazumder teaches of this as described above with respect to claim 1 for the same reasoning as detailed in claim 1.
Bashir, Tran. and Mazumder are analogous art because they are from the same field of endeavor, as they involve memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir and Tran before the time of the effective filing of the claimed invention to incorporate the programmable switching SRAM of Tran into Bashir. Their motivation would have been to more efficiently operate the memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, and Mazumder before the time of the effective filing of the claimed invention to incorporate the CMD/ADDR/PAR bus and I/O buffers of Mazumder into the combination of Tran and Bashir. Their motivation would have been to more efficiently access the memory.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir, Tran, and Mazumder as applied to claim 13 above, and further in view of Westwick.
With respect to claim 14, the combination of Bashir, Tran, Mazumder, and Westwick teaches of the limitations cited and described in claims 2-3 for the same reasoning as described above with respect to claims 2-3.
Bashir, Tran, Mazumder, and Westwick are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, and Westwick before the time of the effective filing of the claimed invention to incorporate the brownout detector of Westwick into the combination of Bashir, Tran and Mazumder. Their motivation would have been to ensure the power is adequate for operation.
Claim(s) 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bashir, Tran, Mazumder, and Westwick as applied to claim 14 above, and further in view of Wong.
With respect to claims 15-17 and 20, the combination of Bashir, Tran, Mazumder, Westwick, and Wong teaches of the limitations cited and described in claims 4-6 and 11 for the same reasoning as described above with respect to claims 4-6 and 11.
Bashir, Tran, Mazumder, Westwick, and Wong are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Bashir, Tran, Mazumder, Westwick, and Wong before the time of the effective filing of the claimed invention to incorporate power switching circuitry of Wong into the combination of Bashir, Tran, Mazumder, and Westwick. Their motivation would have been to prevent short circuit conditions when switching the voltage (Wong, paragraph 34).
Allowable Subject Matter
Claims 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 8 and 18, the prior art of Nakai et al. (US 2008/0291754) discloses setting control signals to a high level/Vcc when the SRAM is in standby mode to reduce standby current in paragraph 28. However, this is not maintaining the address, data, and control busses at a logic zero as described in the claims.
With respect to claim 8, the prior art does not teach or suggest, “wherein the address, data and control buses are maintained at a logic zero in a brownout mode,” in the context of the claim.
With respect to claim 18, the prior art does not teach or suggest, “wherein in a brownout-mode…the address, data and control buses are maintained at a logic zero,” in the context of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Caragiulo et al. (US 2024/0062787) discloses performing SRAM power switching between an active and deep retention state.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138