Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to amendment filed on 5/28/2025, claims 1, 10, 12 have been amended, no claims have been cancelled. Claims 1-20 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement filed 2/1/2024 (one of IDS) fails to comply with 37 CFR 1.98(a)(1), which requires the following: (1) a list of all patents, publications, applications, or other information submitted for consideration by the Office; (2) U.S. patents and U.S. patent application publications listed in a section separately from citations of other documents; (3) the application number of the application in which the information disclosure statement is being submitted on each page of the list; (4) a column that provides a blank space next to each document to be considered, for the examiner’s initials; and (5) a heading that clearly indicates that the list is an information disclosure statement. The information disclosure statement has been placed in the application file, but the information referred to therein has not been considered.
Response to applicant’s Arguments
Applicant’s arguments, see page 1-4, filed 5/28/2025, with respect to the rejection(s) of claim(s) 1-5, 7-13, 15-18 and 20 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of YIM et al., US 2009/0235014 A1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-13, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al., US 2020/0042459 A1, in view of YIM et al., US 2009/0235014 A1.
Regarding claim 1, BAE teaches a system comprising:
a processing device (Fig.2 and Fig.22; it is taught as the processor 110 or 2100); and
memory storing instructions which, when executed, cause the processing device (Fig.22 and section 0149-0150) to:
store first data in the first memory device (section 0045; The virtual memory controller 230 of the storage device 200 may use a byte accessible address space of a larger size than the host-dedicated memory region HDMR to provide the MMIO interface 30 to the host device 100, for allowing access in units of bytes with respect to the data stored in the host-dedicated memory region HDMR);
maintain data associated with operation of the first memory device (section 0072; it is taught as the dynamic mapping table DMT and the static mapping table SMT including the mapping relations between the virtual addresses VA1?VAn of the virtual memory region VMR and the logic block addresses LBA1?LBAn of the flushing memory region FMR and the occupation state information OCS indicating whether data are stored at each logic block address that is mapped to a corresponding virtual address); and
move, based on the maintained data, the first data from the first memory device to the second memory device (section 0072-0073; The internal transfer manager 234 may control a data transfer between the first memory device MEM1 210 and the second memory device MEM2 220 based on the dynamic mapping table DMT and the static mapping able SMT including the mapping relations between the virtual addresses VA1?VAn of the virtual memory region VMR and the logic block addresses LBA1?LBAn of the flushing memory region FMR and the occupation state information OCS indicating whether data are stored at each logic block address that is mapped to a corresponding virtual address).
BAE teaches the mapping manager 232 and the internal transfer manager 234 may be implemented with combinations of an address translation unit (ATU), a memory management unit (MMU), a multiplexer for data redirection. The mapping manager 232 and the internal transfer manager 234 which is located in the virtual memory controller 230 which is in the Fig.2 (hos device connected to the first memory device 210 and the second memory device 220).
BAE does not clearly teach a processing device connected to both of a first memory device and a second memory device via a multiplexer.
However, YIM teaches a processing device connected to both of a first memory device and a second memory device via a multiplexer (section 0060; the host 110 may store data in the DRAM or non-volatile memory 130, or read data from the DRAM or non-volatile memory 130 using a multiplexer or de-multiplexer controlled based on the flag).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings YIM into BAE such as a processing device connected to both of a first memory device and a second memory device via a multiplexer because the host may access the DRAM or non-volatile memory using the converted physical address without an interference of the OS (section 0060 of YIM).
Regarding claim 2, BAE teaches the maintained data is stored in an access table (section 0071-0072; the dynamic mapping table DMT including mapping relations between the real addresses RA1?RAm of the host-dedicated memory region HDMR and the virtual addresses VA1?VAn of the virtual memory region VMR).
Regarding claim 3, BAE teaches the maintained data maps memory access to different types of memory (section 0004; a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface).
Regarding claim 4, BAE teaches the maintained data is updated as read or write access operations are performed (section 0121-0122; when the virtual address VAi is accessed, the storage device 200 may determine, based on the occupation state information OCS, whether to perform the loading operation to store the data of the logic block address mapped to the virtual address VAi to the real address RAj mapped to the virtual address VAi; after the access operation is completed, the storage device 200 may update the occupation state information OCS corresponding to the virtual address VAi).
Regarding claim 5, BAE teaches the maintained data includes a context of the first memory device (section 0091; As a result, the storage device 200 may support nonvolatility or persistency of the virtual memory region VMR such that all of data stored in the virtual memory region VMR are maintained even though the power of the storage device 200 is blocked; Fig.3).
Regarding claim 7, BAE teaches the maintained data includes a voltage of a bus (section 0136-0140; it is taught as voltages for the first and second node in Fig.20).
Regarding claim 8, BAE teaches the maintained data includes timing data (Fig.5 and 10; the dynamic mapping table DMT may include mapping relations between real address RAD of the host-dedicated memory region HDMR and virtual address VAD of the virtual memory region VMR; at time point T1, the real addresses RA1, RA2, RA2, and RA4 may be mapped to the virtual addresses VAa, VAb, VAc, and VAd, respectively; at time point T2 different from time point T1, the real addresses RA1, RA2, RA2, RA4, and RAm may be mapped to the virtual addresses VAf, VAg, Vah, VAi, and VAj, respectively).
Regarding claim 9, BAE teaches the maintained data includes a type of data used by an application (section 0129; The storage device 200 may provide each of the plurality of the sub virtual memory regions VMR1 and VMR2 exclusively to each of a plurality of applications APP1 and APP2 of the host device 100).
Regarding claim 10, BAE teaches a system comprising: a first memory device (Fig.2; section 0047); a second memory device (Fig.2 and section 0048); and a processing device (Fig.2 and Fig.22; it is taught as the processor 110 or 2100) configured to: store data in the first memory device (section 0045; The virtual memory controller 230 of the storage device 200 may use a byte accessible address space of a larger size than the host-dedicated memory region HDMR to provide the MMIO interface 30 to the host device 100, for allowing access in units of bytes with respect to the data stored in the host-dedicated memory region HDMR); and move the stored data from the first memory device to the second memory device by updating a page table (section 0071-0073; The internal transfer manager 234 may control a data transfer between the first memory device MEM1 210 and the second memory device MEM2 220 based on the dynamic mapping table DMT and the static mapping table SMT including the mapping relations between the virtual addresses VA1?VAn of the virtual memory region VMR and the logic block addresses LBA1?LBAn of the flushing memory region FMR and the occupation state information OCS indicating whether data are stored at each logic block address that is mapped to a corresponding virtual address; the mapping manager 232 may dynamically change the mapping relations of the dynamic mapping table DMT according to progression of an access operation by the host device 100 with respect to the virtual memory region VMR).
BAE does not clearly teach the page table comprising a first virtual page corresponding to first virtual addresses in the first memory device and a second virtual page corresponding to second virtual addresses in the second memory device.
However, YIM teaches the page table comprising a first virtual page corresponding to first virtual addresses in the first memory device and a second virtual page corresponding to second virtual addresses in the second memory device (section 0141; the controller 510 receives a virtual address from an external host. The controller 510 may convert the virtual address into a physical address of the volatile memory 520, that is, a physical address 1, or convert the virtual address into a physical address of the non-volatile address 530, that is, a physical address 2, based on temporal locality of the received virtual address).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings YIM into BAE such as the page table comprising a first virtual page corresponding to first virtual addresses in the first memory device and a second virtual page corresponding to second virtual addresses in the second memory device because it improves the memory management efficiency (section 0143 of YIM).
Regarding claim 11, BAE teaches a latency of the second memory device is different from a latency of the first memory device (Fig.2 and section 0047-0048; the first memory device MEM1 210 may be a volatile memory device having a rapid operation speed such as dynamic random access memory (DRAM), static random access memory (SRAM), or the like; the second memory device MEM2 220 may be a nonvolatile memory device such as electrically erasable programmable read only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or the like).
Regarding claim 12, BAE teaches a first namespace of the page table is bound to the first memory device and a second namespace of the page table is bound to the second memory device (section 0066; one virtual address VAD may correspond to one logic block address LBAD. In other words, the virtual addresses VA1, VA2, VA3, and VAn may be mapped to the logic block addresses LBA1, LBA2, LBA3, and LBAn, respectively).
Regarding claim 13, BAE teaches the stored data is moved based on use of the first memory device by an application (section 0071-0072 and 0086; the mapping manager 232 may dynamically change the mapping relations of the dynamic mapping table DMT according to progression of an access operation by the host device 100 with respect to the virtual memory region VMR).
Regarding claim 15, BAE teaches the page table is updated to map a namespace based on a memory type of the second memory device (section 0072-0073; it is taught as a flushing operation or a loading operation).
Regarding claim 16, BAE teaches updating the page table comprises changing a memory type for data used by an application (section 0119; it is taught as the internal transfer manager 234 may load the data of the logic block address mapped to the virtual address VAi to the real address RAj of the host-dedicated memory region HDMR from the flushing memory region FMR of the second memory device MEM2 220 (S550) and then the virtual memory controller 230 may perform the access operation with respect to the real address RAj (S560). Accordingly, the read operation and/or the overwrite operation may be performed while maintaining consistency of the already stored data).
Regarding claim 17, BAE teaches the memory type is stored in a translation lookaside buffer (section 0115; the storage device 200 may receive a virtual address VAi as an access address from the host device 100 (S510). The virtual address VAi may be a write address for a write operation or a read address for a read operation).
Regarding claim 18, BAE teaches a system comprising: a first memory device (Fig.1; first memory device 210); a second memory device (Fig.2; the second memory device 220); and a processing device (Fig.2; CPU 110) configured to: store data at a first virtual address allocated to an application, the first virtual address corresponding to the first memory device (section 0051; The virtual memory region VMR is mapped to the host-dedicated memory region HDMR of the first memory device MEM1 210), the second virtual address corresponding to the second memory device (Fig.2-3 and section 0040; selectively perform access in units of bytes with respect to the first memory device MEM1 210 or access in units of blocks with respect to the second memory device MEM2 220).
BAE does not clearly teach in response to determining a use of the stored data by the application, store the data at a second virtual address allocated to the application, the second virtual address corresponding to the second memory device.
However, YIM teaches in response to determining a use of the stored data by the application, store the data at a second virtual address allocated to the application (section 0113-0114; section 0124 The controller 230 receives an RA of the data requested from the external host during a time interval 410. The controller 230 searches data blocks or pages corresponding to the RA of the data, requested from the external host, from among data blocks or pages stored in a first memory 210; As a result of the searching, where the data blocks or pages corresponding to the RA of the data, requested from the external host, are not stored in the first memory 210, the controller 230 may transmit the RA to the second memory 220).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings YIM into BAE such as in response to determining a use of the stored data by the application, store the data at a second virtual address allocated to the application, the second virtual address corresponding to the second memory device because it may reduce latency spent for transmitting the data to the external host (section 0124 of YIM).
Regarding claim 20, BAE teaches storing the data at the second virtual address is further in response to determining a reliability of memory cells in the first memory device (section 0080; the dynamic mapping table DMT indicates that the first and second virtual addresses VA1 and VA2 are mapped sequentially to the first and second real addresses RA1 and RA2).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over BAE et al., US 2020/0042459 A1and YIM et al., US 2009/0235014 A1, in view of Rencs., US 9,983,558 B2
Regarding claim 6, BAE and YIM teach the claimed inventions as shown above, BAE and YIM do not clearly teach the system further comprises a sensor, and the context is data collected by the sensor. However, Rencs teaches the system further comprises a sensor, and the context is data collected by the sensor (col.3, lines 19-26; a customized architecture of an embedded machine vision system on mobile platforms utilizing System on Chip (SOC) technologies that accurately collects vast amounts of sensor data (inertial, positional and image, radar data), calculates the position and pose of the sensors and system body and distributes this accurately collected sensor and control data to a system of coprocessors located on the SOC).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings Rencs into BAE and YIM such as system further comprises a sensor, and the context is data collected by the sensor because knowledge of the sensor orientation and position in relative time and space is very computationally advantageous to solve the generic machine vision problems existent with moving platforms. The addition of absolute positional knowledge significantly improves capability of the mobile platform (col.3, lines 26-34 of Rencs).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over BAE et al., US 2020/0042459 A1and YIM et al., US 2009/0235014 A1, in view of Kaushik., US 2016/0283140 A1.
Regarding claim 14, BAE and YIM teach the claimed inventions as shown above, BAE and YIM do not clearly teach the processing device is further configured to monitor an access pattern of an application, and the stored data is moved based on the access pattern. However, Kaushik teaches the processing device is further configured to monitor an access pattern of an application, and the stored data is moved based on the access pattern (section 0061; the storage module monitors the access patterns to the data and moves data that is getting accessed frequently to the high performance flash tier (i.e., flash memory).). It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings Kaushik into BAE and YIM such as the processing device is further configured to monitor an access pattern of an application, and the stored data is moved based on the access pattern because it leverages faster and randomly accessible storage mediums (section 0061 of Kaushik).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over BAE et al., US 2020/0042459 A1and YIM et al., US 2009/0235014 A1, in view of Dodke et al., US 10,079,835 B1.
Regarding claim 19, BAE and YIM teach the claimed inventions as shown above, BAE and YIM do not clearly teach determining the use comprises determining that the use of the stored data by the application will be greater than a threshold. However, Dodke teaches determining the use comprises determining that the use of the stored data by the application will be greater than a threshold (col.12, lines 11-15; flagging module 108 may determine that the amount of sensitive data accessed by application 230 is greater than the predefined threshold (which may be zero or some other nonzero amount of arbitrary size)). It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings Dodke into BAE and YIM such as determining the use comprises determining that the use of the stored data by the application will be greater than a threshold because flagging the application as having accessed the sensitive data that is protected by the data loss prevention policy (col.2, lines 29-31 of Dodke).
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133