DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 8/6/2026. Claims 1-5, 7-13 and 21 are under examination. Claims 14-20 have been withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-9, 11-13 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (USP 10,762,868) in view of Yuan et al. (US 2021/0335269).
Regarding claim 1, Chen et al.’s figure 3 shows A driving circuit comprising a data writing module (20), a first inverter (M1, M2) and a second inverter (M3, M4) connected in a latch configuration, wherein the data writing module (20), the first inverter (M1, M2) and the second inverter (M3, M4) are free of storage capacitor (noted the capacitor Cst belongs to a memory in pixel 30. It is also noted that the latch circuit 10, the switch circuit 30 and the selection circuit 30 are respective functional units (see column 7, line 5-15), thus, clearly the latch circuit is free of capacitor which belongs to the selection circuit 30), wherein: an output terminal of the data writing module (20) is connected to a first node (Q); a first terminal of the first inverter is connected to a first power supply terminal (VDD), a second terminal of the first inverter is connected to a second power supply terminal (VSS), an input terminal of the first inverter is connected to the first node (Q), and an output terminal of the first inverter is connected to a second node (Q/); and a first terminal of the second inverter (M3, M4) is connected to the first power supply terminal (VDD), a second terminal of the second inverter is connected to the second power supply terminal (VSS), an input terminal of the second inverter is connected to the second node (Q/), and an output terminal of the second inverter is connected to the input terminal of the first inverter.
Chen et al. suggests that the width to length ratio of the third transistor (M2) is at least 5 times bigger than the width to length ratio of the second transistor (M1) (see column 12, lines 8-20).
Chen et al.’s does not suggest the width to length ratio of the third transistor (M2) is at least 10 times the width to length ratio of the second transistor (M1) as called for in claim 1. However, it is known in the art that the drain current (Id) in a MOSFET is directly proportional to the channel width and inversely proportional to the channel length (Id ∝ W/L). This means that increasing the channel width while keeping the length constant will increase the drain current, and conversely, decreasing the channel length will also increase the drain current (Yuan et al. (US 2021/0335269, “the driving current I output by the driving transistor DT is (μWCox/2 L) (Vgs−Vth).sup.2, where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is a width of a channel of the driving transistor, L is a length of a channel of the driving transistor, Vgs is a gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor”; paragraph 0046). Thus, dependent upon a particular load current required, it is desirable to have Chen et al.’s driving current (drain current) of the third transistor larger than the second transistor by having the width to be greater than 5 or possible equal to 10 to ensure that its driving capability to the load is met. Thus, it would have been obvious to person skilled in the art before the effective filing date of the invention to having the width to length ratio of the third transistor (M2) is at least 10 times the width to length ratio of the second transistor (M1) in order to meet a load current requirement as taught by Yuan et al. reference.
Noted, when the third transistor (M2) is turned on, an impedance of the second transistor (M1) is greater than an impedance of the third transistor (M2) (on impedance of larger channel width third transistor (M2) when it is on has lower impedance than a smaller channel width (M1), and when the third transistor is turned off, the impedance of the second transistor is less than the impedance of the third transistor (larger channel width third transistor (M2) when it is off has a larger off impedance than the second transistor (M1) with a smaller channel width; ID=12μCoxWL(VGS−VTH)2) is also met.
Regarding claim 2, Chen et al.’s figure 3 shows a driving signal (Q, Q/) to a driving electrode in a microfluidic driving device (30), wherein: the output terminal of the second inverter serves as an output terminal of the driving circuit and is electrically connected to the driving electrode; or signals at the first node (Q) and the second node (Q/) are configured as control signals to control a signal output at an output terminal of the driving circuit.
Regarding claim 3, wherein the data writing module, the first inverter and the second inverter all include transistors of a same type.
Regarding claim 4, wherein the data writing module includes a first transistor (M5), a gate of the first transistor is connected to a control signal line (GL), a first pole of the first transistor is connected to a data signal line (DL), and a second pole of the first transistor is connected to the first node (Q).
Regarding claim 5, the first inverter includes a second transistor and a third transistor; a gate and a first pole of the second transistor are both connected to the first power supply terminal, and a second pole of the second transistor is connected to the second node; and a gate of the third transistor is connected to the first node, a first pole of the third transistor is connected to the second power supply terminal, and a second pole of the third transistor is connected to the second node.
Regarding claim 7, the second inverter includes a fourth transistor (M3) and a fifth transistor (M4) ; a gate and a first pole of the fourth transistor (M3) are both connected to the first power supply terminal (VDD), and a second pole of the fourth transistor is connected to the first node (Q); and a gate of the fifth transistor (M4) is connected to the second node (Q/), the first pole of the fifth transistor is connected to the second power supply terminal (Vss), and a second pole of the fifth transistor is connected to the first node (Q).
Regarding claim 8, Chen et al.’s figure 3 shows a driving circuit comprising all the aspects of the present invention including the width to length ratio of the fifth transistor (M4) is at least 5 times the width to length ratio of the fourth transistor (M3) (see column 12, lines 8-20).
Chen et al.’s does not suggest the width to length ratio of the fifth transistor (M4) is at least 10 times the width to length ratio of the fourth transistor (M3) as called for in claim 8. However, it is known in the art that the drain current (Id) in a MOSFET is directly proportional to the channel width and inversely proportional to the channel length (Id ∝ W/L). This means that increasing the channel width while keeping the length constant will increase the drain current, and conversely, decreasing the channel length will also increase the drain current (Yuan et al. (US 2021/0335269) paragraph 0046; “the driving current I output by the driving transistor DT is (μWCox/2 L) (Vgs−Vth).sup.2, where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is a width of a channel of the driving transistor, L is a length of a channel of the driving transistor, Vgs is a gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor”). Thus, dependent upon a particular load current required, it is desirable to have Chen et al.’s driving current (drain current) of the fifth transistor larger than the fourth transistor as large as possible to ensure that its driving capability to the load is met. Thus, it would have been obvious to person skilled in the art before the effective filing date of the invention to having the width to length ratio of the fifth transistor (M4) is at least 10 times the width to length ratio of the fourth transistor (M1) in order to meet a load current requirement as taught by Yuan et al. reference.
Noted, when the fifth transistor (M4) is turned on, an impedance of the fourth transistor (M3) is greater than an impedance of the fifth transistor (M4) (on impedance of larger channel width transistor (M4) when it is on has lower impedance than a smaller channel width transistor (M3)), and when the fifth transistor (M4) is turned off, the impedance of the fourth transistor (M3) is less than the impedance of the fifth transistor (larger channel width fifth transistor (M4) when it is off has a larger off impedance than the fourth transistor (M3) with a smaller channel width; ID=12μCoxWL(VGS−VTH)2) is also met.
Regarding claim 9, wherein the transistors are all N-type transistors, the first power supply terminal is a positive power supply terminal, and the second power supply terminal is a negative power supply terminal.
Regarding claim 11, Chen’s figure 1 further comprising a gating module (M6, M7), wherein: the gating module includes a first gating unit (M6) and a second gating unit (M7), a control terminal of the first gating unit (M6) is connected to the first node (Q), a control terminal of the second gating unit (M7) is connected to the second node (Q/), a first terminal of the first gating unit (M6) is connected to the first level terminal (FRP), and a second end of the first gating unit is connected to the output terminal of the driving circuit; and a first terminal of the second gating unit (M7) is connected to a second level terminal (XFRP), and a second terminal of the second gating unit is connected to the output terminal of the driving circuit.
Regarding claim 12, the first gating unit includes a sixth transistor, the second gating unit includes a seventh transistor, transistors included in the first gating unit, the second gating unit, the data writing module, the first inverter and the second inverter are of a same type.
Regarding claim 13, Chen et al.’s figure 3 shows among the first level terminal and the second level terminal, one transmits an AC signal, and the other transmits also an AC signal. The choice of voltages being applied at the first and second terminal levels determines the type of an output signal. When complementary signals being applied to the first and second level terminals as in Chen et al. (FRP and XFRP), output signal has is a pulse has high logic level and low logic level. It is noted that when one of the terminal is AC signal and the other is DC signal, the output signal is also a pulse has a high logic level and a low logic level. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention in either case of signals being applied to the first and second level terminal, the results unchanged Therefore, outside of any non-obvious results, the obviousness of applying one of the terminal with an AC signal and the other is with DC signal will not be patentable under 35USC 103.
Note, the recited limitations “such that the driving circuit is configured to provide AC driving to a driving electrode to reduce a hysteresis effect caused by charge accumulation during a driving process” is also present in the combination of Chen et al. (USP 10,762,868) in view of Yuan et al. (US 2021/0335269). That is, the functional limitations of " such that the driving circuit is configured to provide AC driving to a driving electrode to reduce a hysteresis effect caused by charge accumulation during a driving process " does not add or modify any structural limitations to the driving circuit of the claim; they are simply a manner of operation of the driving circuit. According to MPEP 2114 (II), the manner of operating the device does not differentiate apparatus claims from the prior art. "Apparatus claim cover what a device is, not what a device does." Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claim 21, The driving circuit according to claim 8, wherein A2=A4 and A3=A5, such that the second transistor and the fourth transistor are formed with identical specifications and the third transistor and the fifth transistor are formed with identical specifications (W2=W4;5W1=5W3).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (USP 10,762,868) in view of Yuan et al. (US 2021/0335269) and further in view of Otose et al. (US 2009/0290677).
Regarding claim 10, the combination of Chen et al. and Yuan et al. shows a driving circuit comprised of transistors of N type instead of P type transistors as called for in claim 10. Chen et al. also suggests the driving circuit can all be made of all P type transistors (paragraph 0042). Furthermore, Otose et al. teaches that driving circuit can be made with either N type transistors or P type transistors (see figures 5 and 8) without altering the circuit operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Chen et al.’s driver circuit made with all P type transistors as taught by Otose et al. reference.
Response to Arguments
Applicant's arguments filed 8/6/2026 have been fully considered but they are not persuasive. Applicant argues that The Examiner's leap from Yuan's general formula to a specific kl>10 ratio between the load transistor and switching transistor in a latch inverter constitutes impermissible hindsight reconstruction, using the present application's teaching to select a motivation from Yuan's general formula. Without knowledge of the present invention, a person of ordinary skill in the art would have no reason from Yuan to select a k>10 ratio (as opposed to k=5 as Chen discloses, or any other ratio) for the specific purpose of reliable impedance-based latch state discrimination as now recited in amended claim 1, found not persuasive. Chen et al. reference suggests that the W/L of the third transistor (M2) at 5 times W/L ratio of the second transistor (M1), the latch state discrimination of (M1-M4) is already strong (column 9, lines 65-67 states “because” (emphasis) the channel width W3/W1 of the transistor M3/M1 is smaller than the channel width W4/W2 of the transistor M4/M2, a potential of third nod A or Q/ “still” (emphasis) pulled down to the second potential V2). Furthermore, Yuan et al.’s paragraph 0046 stated “the driving current I output by the driving transistor DT is (μWCox/2 L) (Vgs−Vth).sup.2, where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is a width of a channel of the driving transistor, L is a length of a channel of the driving transistor, Vgs is a gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor”. This suggests the drain current of a transistor would be in direct relation with W/L of a transistor. Thus, with the W/L of the third transistor (M2) at least 10 times W/L ratio of the second transistor (M1) would have had a stronger drain current than the already strong/large drain current when the W/L of the third transistor (M2) at least 5 times W/L ratio of the second transistor (M1). Therefore, outside of any non-obvious results, the obvious of having the W/L of the third transistor (M2) at least 10 times W/L ratio of the second transistor (M1) in order to provide a stronger and bigger drain current in a latch arrangement will not be patentable under 35USC 103. The rejection is deemed proper, thus, claims 1-5 and 7-13 remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 9/26/2026
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