DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/06/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
5. Claims 1, 10 and 16 are objected to because of the following informalities:
Claim 1 lines 2, 9 and 11 recites “a second P channel…”. However, it appears that it should recite “a second P-channel…”.
Claim 1 lines 10 - 11 recites “… from a drain of the second P channel transistor to the current mirror to the collector of the second bipolar transistor…”. However, it appears that it should recite “… from a drain of the second P channel transistor of the current mirror to the collector of the second bipolar transistor…”.
Claim 1 line 13 recites “a delta VBE sense resistor…”. However, it appears that it should recite “a sense resistor…”.
Claim 1 line 17 recites “an Rtail resistor circuit…” . However, it appears that it should recite “a tail resistor circuit…”.
Claims 10 and 11 line 1 recites “wherein the Rtail resistor circuit…”. However, it appears that it should recite “wherein the tail resistor circuit…”.
Claim 16 line 8 recites “a delta VBE sense resistor…”. However, it appears that it should recite “a sense resistor…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim(s) 1, 3, 9, 12, 14 - 17 and 19 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2014/0015504 A1 in view of US Pub. No. 2021/0135658 A1; (hereinafter Sano et al and Tai).
Regarding claim 1, Sano et al [e.g., Fig. 48] a voltage reference circuit [e.g., reference voltage generating circuit 11], comprising: a current mirror formed of a first P-channel transistor and a second P channel transistor [e.g., current mirror formed with MOS transistors MP13 and MP14], wherein a gate of the first P-channel transistor is coupled to a gate of the second P-channel transistor [e.g., gate of MP13 coupled to gate of MP14]; a first bipolar transistor having a base, emitter and collector [e.g., bipolar transistor Q1]; a second bipolar transistor having a base, emitter and collector [e.g., bipolar transistor Q2], wherein the base of the second bipolar transistor is coupled to the base of the first bipolar transistor at a base node [e.g., base of Q1 coupled to base of Q2]; a first current leg extending from a drain of the first P channel transistor of the current mirror to the collector of the first bipolar transistor [e.g., first current leg extending from drain of MP14 to collector of Q1]; a second current leg extending from a drain of the second P channel transistor to the current mirror to the collector of the second bipolar transistor [e.g., second current leg extending from drain of MP13 to collector of Q2]; a delta VBE sense resistor coupled between the emitter of the second bipolar transistor and the emitter of the first bipolar transistor [e.g., resistor R20 coupled to emitter of Q2 and the emitter of Q1], wherein the emitter of the first bipolar transistor is part of a tail resistor node [e.g., emitter of Q1 part of node share between R20 and resistors R23A and R23B]; a ground conductor [e.g., grounding conductor from bottom terminal of resistor R23B]; an Rtail resistor circuit coupled to conduct current from the tail resistor node to the ground conductor [e.g., resistors R23A and R23B, p. 0414 recites “a resistance R23 that is divided into a resistance R23A and a resistance R23B and is provided between the emitter terminals of the bipolar transistors Q1 and Q2 and the ground node”].
Sano et al does not disclose a current redistribution circuit coupled to conduct a first base resupply current from the first current leg and to supply that current onto the base node, and coupled to conduct a second base resupply current from the second current leg and to supply that current onto the base node.
Tai [e.g., Figs. 1, 6 and 9] teaches a current redistribution circuit [e.g., signal generating device 600] coupled to conduct a first base resupply current from the first current leg [e.g., first adjusting current Ia1”] and to supply that current onto the base node [e.g., supply current to differential amplifier 6102], and coupled to conduct a second base resupply current from the second current leg [e.g., second adjusting current Ia2”] and to supply that current onto the base node [e.g., supply current to differential amplifier 6102].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with a current redistribution circuit coupled to conduct a first base resupply current from the first current leg and to supply that current onto the base node, and coupled to conduct a second base resupply current from the second current leg and to supply that current onto the base node as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 3, Sano et al discloses the claimed invention except for the first base resupply current is directly proportional to the second base resupply current.
Tai [e.g., Figs. 1, 6and 9] teaches the first base resupply current [e.g., first adjusting current Ia1”] is directly proportional to the second base resupply current [e.g., currents correspond to each other as differential amplifier 6102 control the gates of X8” and X9” as a result of V3 and V4, p. 0018 recites “The differential amplifier 1090 is arranged to compare the base signal V3 and the base signal V4 to generate a control signal Sc. The control signal Sc may be differential output signals, in which the positive signal of the differential output signals is coupled to the first active device 1082, and the negative signal of the differential output signals is coupled to the second active device 1084. The differential amplifier 1090 may be implemented by an operational transconductance amplifier (OTA) that generates an output current according to differential input voltages. The active device 1082 is coupled between the terminals N1 and N3 for generating the first adjusting current Ia1 according to the control signal Sc. The active device 1084 is coupled between the terminals N5 and N4 for generating the second adjusting current Ia2 according to the control signal Sc”. It continues on p.0050 - 0052 recites “In operation 902, a first circuit (e.g. 102) and a second circuit (e.g. 104) are arranged to generate a first current (e.g. Ir1) and a second current (e.g. Ir2) respectively. The first current substantially equals the second current. The first circuit comprises a first p-type BJT (e.g. Q1) for receiving the first current. The second circuit comprises a second p-type BJT (e.g. Q2) for receiving the second current. In operation 904, a first n-type FET (e.g. X3) and a second n-type FET (e.g. X4) are arranged to generate a first adjusting current (e.g. Ia1) and a second adjusting current (e.g. Ia2) to the emitters of the first p-type BJT and the second p-type BJT respectively.”. Finally, p. 0053 recites “In operation 908, a differential amplifier (e.g. 1090) is arranged to control the gates of the first n-type FET (e.g. X3) and the second n-type FET (e.g. X4) according to the voltages on the bases of the first p-type BJT and the second p-type BJT such that the voltage on the base of the first p-type BJT equals the voltage on the base of the second p-type BJT.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with the first base resupply current is directly proportional to the second base resupply current as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 9, Sano et al discloses the claimed invention except for the first current leg comprises a first N-channel cascode transistor, wherein the second current leg comprises a second N- channel cascode transistor, and wherein a gate of the first N-channel cascode transistor is coupled to a gate of the second N-channel cascode transistor.
Tai [e.g., Figs. 1, 6 and 9] teaches the first current leg comprises a first N-channel cascode transistor [e.g., first current leg comprises n-type FET X3”], wherein the second current leg comprises a second N- channel cascode transistor [e.g., second current leg comprises n-type FET X4”], and wherein a gate of the first N-channel cascode transistor is coupled to a gate of the second N-channel cascode transistor [e.g., gate of n-type FET X3”coupled to gate of n-type FET X4”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with the first current leg comprises a first N-channel cascode transistor, wherein the second current leg comprises a second N- channel cascode transistor, and wherein a gate of the first N-channel cascode transistor is coupled to a gate of the second N-channel cascode transistor as suggested by Tai to create a higher output impedance and improve linearity of the current mirror circuit.
Regarding claim 12, Sano et al [e.g., Fig. 48] discloses a method, comprising the steps of:(a) conducting a current from a drain of a first P-channel transistor of a current mirror [e.g., current I from drain of MP14], and through a first current leg, and to a collector of a first bipolar transistor [e.g., through the first current leg to collector of bipolar transistor Q1]; (b) conducting a current from a drain of a second P-channel transistor of the current mirror [e.g., current I from drain of MP13], and through a second current leg, and to a collector of a second bipolar transistor [e.g., through the second current leg to collector of bipolar transistor Q2], wherein a base of the first bipolar transistor is coupled at a base node to a base of the second bipolar transistor [e.g., base of Q1 coupled to base of Q2], wherein an emitter of the first bipolar transistor [e.g., emitter of Q1] is coupled at a tail resistor node [e.g., coupled to resistors R23A and R23B] via a delta VBE sense resistor [e.g., via resistor 20] to an emitter of the second bipolar transistor [e.g., coupled to emitter of Q2]; (c) conducting a current from the tail resistor node through a tail resistor circuit to a ground conductor [e.g., conducting current IR23A to ground].
Sano does not discloses (d) drawing a first base resupply current from the first current leg and supplying the first base resupply current onto the base node; and (e) drawing a second base resupply current from the second current leg and supplying the second base result current onto the base node, wherein the first base resupply current is directly proportional to the second base resupply current.
Tai [e.g., Figs. 1, 6 and 9] teaches (d) drawing a first base resupply current from the first current leg [e.g., first adjusting current Ia1”] and supplying the first base resupply current onto the base node [e.g., supply current to differential amplifier 6102]; and (e) drawing a second base resupply current from the second current leg [e.g., second adjusting current Ia2”] and supplying the second base result current onto the base node [e.g., supply current to differential amplifier 6102], wherein the first base resupply current is directly proportional to the second base resupply current [e.g., currents correspond to each other as differential amplifier 6102 control the gates of X8” and X9” as a result of V3 and V4, p. 0018 recites “The differential amplifier 1090 is arranged to compare the base signal V3 and the base signal V4 to generate a control signal Sc. The control signal Sc may be differential output signals, in which the positive signal of the differential output signals is coupled to the first active device 1082, and the negative signal of the differential output signals is coupled to the second active device 1084. The differential amplifier 1090 may be implemented by an operational transconductance amplifier (OTA) that generates an output current according to differential input voltages. The active device 1082 is coupled between the terminals N1 and N3 for generating the first adjusting current Ia1 according to the control signal Sc. The active device 1084 is coupled between the terminals N5 and N4 for generating the second adjusting current Ia2 according to the control signal Sc”. It continues on p.0050 - 0052 recites “In operation 902, a first circuit (e.g. 102) and a second circuit (e.g. 104) are arranged to generate a first current (e.g. Ir1) and a second current (e.g. Ir2) respectively. The first current substantially equals the second current. The first circuit comprises a first p-type BJT (e.g. Q1) for receiving the first current. The second circuit comprises a second p-type BJT (e.g. Q2) for receiving the second current. In operation 904, a first n-type FET (e.g. X3) and a second n-type FET (e.g. X4) are arranged to generate a first adjusting current (e.g. Ia1) and a second adjusting current (e.g. Ia2) to the emitters of the first p-type BJT and the second p-type BJT respectively.”. Finally, p. 0053 recites “In operation 908, a differential amplifier (e.g. 1090) is arranged to control the gates of the first n-type FET (e.g. X3) and the second n-type FET (e.g. X4) according to the voltages on the bases of the first p-type BJT and the second p-type BJT such that the voltage on the base of the first p-type BJT equals the voltage on the base of the second p-type BJT.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with (d) drawing a first base resupply current from the first current leg and supplying the first base resupply current onto the base node; and (e) drawing a second base resupply current from the second current leg and supplying the second base result current onto the base node, wherein the first base resupply current is directly proportional to the second base resupply current as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 14, Sano et al discloses the claimed invention except for wherein the first base resupply current is drawn in (d) from the first current leg at a drain of the first P-channel transistor, and wherein the second base resupply current is drawn in (e) from the second current leg at a drain of the second P-channel transistor.
Tai [e.g., Figs. 1, 6 and 9] teaches wherein the first base resupply current [e.g., first adjusting current Ia1”] is drawn in (d) from the first current leg at a drain of the first P-channel transistor [e.g., drawn from first p-type FET X1”], and wherein the second base resupply current [e.g., second adjusting current Ia2”] is drawn in (e) from the second current leg at a drain of the second P-channel transistor [e.g., drawn from second p-type FET X2”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with wherein the first base resupply current is drawn in (d) from the first current leg at a drain of the first P-channel transistor, and wherein the second base resupply current is drawn in (e) from the second current leg at a drain of the second P-channel transistor as suggested by Tai to supply the adjusting currents to the control circuit to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 15, Sano et al discloses the claimed invention except for the first base resupply current is drawn in (d) from the first current leg at the drain of the first P-channel transistor, and flows through a first cascode transistor on its way to the collector of the first bipolar transistor, and wherein the second base resupply current is drawn in (e) from the second current leg at the drain of the second P-channel transistor, and flows through a second cascode transistor on its way to the collector of the second bipolar transistor.
Tai [e.g., Figs. 1, 6 and 9] teaches the first base resupply current [e.g., first adjusting current Ia1”] is drawn in (d) from the first current leg at the drain of the first P-channel transistor [e.g., drawn from drain of p-type FET X1”], and flows through a first cascode transistor on its way to the collector of the first bipolar transistor [e.g., flows through n-type FET X8” on its way to Q1”], and wherein the second base resupply current [e.g., second adjusting current Ia2”] is drawn in (e) from the second current leg at the drain of the second P-channel transistor [e.g., drawn from drain of p-type FET X2”], and flows through a second cascode transistor on its way to the collector of the second bipolar transistor [e.g., flows through n-type FET X9” on its way to Q2”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with the first base resupply current is drawn in (d) from the first current leg at the drain of the first P-channel transistor, and flows through a first cascode transistor on its way to the collector of the first bipolar transistor, and wherein the second base resupply current is drawn in (e) from the second current leg at the drain of the second P-channel transistor, and flows through a second cascode transistor on its way to the collector of the second bipolar transistor as suggested by Tai to supply the adjusting current to the control circuit to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 16, Sano et al discloses a reference voltage circuit [e.g., reference voltage generating circuit 11] comprising: a tail resistor circuit [e.g., resistors R23A and R23B] coupled to conduct a current between a first node and a second node [e.g., conducts current between first node (node V1) and second node (node shared between R20, R23A and Q2)]; a first bipolar transistor having a base, emitter and collector [e.g., bipolar transistor Q1]; a second bipolar transistor having a base, emitter and collector [e.g., bipolar transistor Q2], wherein the base of the second bipolar transistor is coupled to the base of the first bipolar transistor at a third node [e.g., base of Q1 coupled to base of Q2]; a delta VBE sense resistor coupled between the emitter of the second bipolar transistor and the emitter of the first bipolar transistor [e.g., resistor R20 coupled to emitter of Q2 and the emitter of Q1], wherein the emitter of the first bipolar transistor is part of the second node [e.g., emitter of Q1 part of second node (node shared between R20, R23A and Q2)]; a current mirror having a first current mirror leg and a second current mirror leg [e.g., MOS transistors MP13 and MP14]; a first current leg extending from the first current mirror leg of the current mirror to the collector of the first bipolar transistor [e.g., first current leg extending from drain of MP14 to collector of Q1]; a second current leg extending from the second current mirror leg of the current mirror to the collector of the second bipolar transistor [e.g., second current leg extending from drain of MP13 to collector of Q2].
Sano et al does not discloses a current redistribution circuit coupled to conduct a first base resupply current between a fourth node on the first current leg and the third node and also coupled to conduct a second base resupply current between a fifth node on the second current leg and the third node, wherein the first base resupply current is directly proportional to the second base resupply current.
Tai [e.g., Figs. 1, 6 and 9] teaches a current redistribution circuit [e.g., signal generating device 600] coupled to conduct a first base resupply current [e.g., first adjusting current Ia1”] between a fourth node on the first current leg [e.g., node shared between X3”, X8” and Q1”] and the third node [e.g., node shared between V3”, V4” and differential amplifier 6102] and also coupled to conduct a second base resupply current [e.g., second adjusting current Ia2”] between a fifth node on the second current leg [e.g., node shared between X4”, X9” and Q2”] and the third node [e.g., node shared between V3”, V4” and differential amplifier 6102], wherein the first base resupply current is directly proportional to the second base resupply current [e.g., currents correspond to each other as differential amplifier 6102 control the gates of X8” and X9” as a result of V3 and V4, p. 0018 recites “The differential amplifier 1090 is arranged to compare the base signal V3 and the base signal V4 to generate a control signal Sc. The control signal Sc may be differential output signals, in which the positive signal of the differential output signals is coupled to the first active device 1082, and the negative signal of the differential output signals is coupled to the second active device 1084. The differential amplifier 1090 may be implemented by an operational transconductance amplifier (OTA) that generates an output current according to differential input voltages. The active device 1082 is coupled between the terminals N1 and N3 for generating the first adjusting current Ia1 according to the control signal Sc. The active device 1084 is coupled between the terminals N5 and N4 for generating the second adjusting current Ia2 according to the control signal Sc”. It continues on p.0050 - 0052 recites “In operation 902, a first circuit (e.g. 102) and a second circuit (e.g. 104) are arranged to generate a first current (e.g. Ir1) and a second current (e.g. Ir2) respectively. The first current substantially equals the second current. The first circuit comprises a first p-type BJT (e.g. Q1) for receiving the first current. The second circuit comprises a second p-type BJT (e.g. Q2) for receiving the second current. In operation 904, a first n-type FET (e.g. X3) and a second n-type FET (e.g. X4) are arranged to generate a first adjusting current (e.g. Ia1) and a second adjusting current (e.g. Ia2) to the emitters of the first p-type BJT and the second p-type BJT respectively.”. Finally, p. 0053 recites “In operation 908, a differential amplifier (e.g. 1090) is arranged to control the gates of the first n-type FET (e.g. X3) and the second n-type FET (e.g. X4) according to the voltages on the bases of the first p-type BJT and the second p-type BJT such that the voltage on the base of the first p-type BJT equals the voltage on the base of the second p-type BJT.”]
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with a current redistribution circuit coupled to conduct a first base resupply current between a fourth node on the first current leg and the third node and also coupled to conduct a second base resupply current between a fifth node on the second current leg and the third node, wherein the first base resupply current is directly proportional to the second base resupply current as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 17, Sano et al discloses the claimed invention except for the first current mirror leg of the current mirror comprises a first current leg transistor, wherein the first current leg transistor has a drain, wherein the fourth node and the drain of the first current leg transistor are the same node; wherein the second current mirror leg of the current mirror comprises a second current leg transistor, wherein the second current leg transistor has a drain, and wherein the fifth node and the drain of the second current leg transistor are the same node.
Tai [e.g., Figs. 1, 6 and 9] teaches the first current mirror leg of the current mirror comprises a first current leg transistor [e.g., leg corresponding to drain of X1” comprising n-type FET X8”], wherein the first current leg transistor has a drain [e.g., drain of n-type FET X8”], wherein the fourth node and the drain of the first current leg transistor are the same node [e.g., node shared between drain of X3”, drain of X8” and Q1”]; wherein the second current mirror leg of the current mirror comprises a second current leg transistor [e.g., leg corresponding to drain of X2” comprises n-type FET X9”], wherein the second current leg transistor has a drain [e.g., drain of X9”], and wherein the fifth node and the drain of the second current leg transistor are the same node [e.g., node shared between drain of X4”, drain of X9” and Q2”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with the first current mirror leg of the current mirror comprises a first current leg transistor, wherein the first current leg transistor has a drain, wherein the fourth node and the drain of the first current leg transistor are the same node; wherein the second current mirror leg of the current mirror comprises a second current leg transistor, wherein the second current leg transistor has a drain, and wherein the fifth node and the drain of the second current leg transistor are the same node as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 19, Sano et al discloses the claimed invention except for the current redistribution circuit comprises: a third transistor through which the first base resupply current flows and none of the second base resupply current flows; and a fourth transistor through which the second base resupply current flows and none of the first base resupply current flows, wherein a gate of the fourth transistor is coupled to a gate of the third transistor.
Tai [e.g., Figs. 1, 6 and 9] teaches the current redistribution circuit [e.g., signal generating device 600] comprises: a third transistor [e.g., n-type FET X8”] through which the first base resupply current flows [e.g., first adjusting current Ia1”] and none of the second base resupply current flows [e.g., second adjusting current Ia2” does not flow through X8”]; and a fourth transistor [e.g., n-type FET X9”] through which the second base resupply current flows [e.g., second adjusting current Ia2”] and none of the first base resupply current flows [e.g., first adjusting current Ia1” does not flow through X9”], wherein a gate of the fourth transistor is coupled to a gate of the third transistor [e.g., gates of X8” and X9” coupled together].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with the current redistribution circuit comprises: a third transistor through which the first base resupply current flows and none of the second base resupply current flows; and a fourth transistor through which the second base resupply current flows and none of the first base resupply current flows, wherein a gate of the fourth transistor is coupled to a gate of the third transistor as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
Regarding claim 20, Sano et al discloses the claimed invention except for the current redistribution circuit conducts a current to or from the third node, and wherein the current conducted by the current redistribution circuit to or from the third node is the sum of the first and second base resupply currents.
Tai [e.g., Figs. 1, 6 and 9] teaches wherein the current redistribution circuit [e.g., signal generating device 600] conducts a current to or from the third node [e.g., generates control signal Sc from node shared between V3, V4 and differential amplifier 1090], and wherein the current conducted by the current redistribution circuit to or from the third node is the sum of the first and second base resupply currents [e.g., p. 0018 recites “The differential amplifier 1090 is arranged to compare the base signal V3 and the base signal V4 to generate a control signal Sc. The control signal Sc may be differential output signals, in which the positive signal of the differential output signals is coupled to the first active device 6102, and the negative signal of the differential output signals is coupled to the second active device 6104. The differential amplifier 1090 may be implemented by an operational transconductance amplifier (OTA) that generates an output current according to differential input voltages. The active device 6102 is coupled between the terminals N1 and N3 for generating the first adjusting current Ia1” according to the control signal Sc. The active device 6104 is coupled between the terminals N5 and N4 for generating the second adjusting current Ia2” according to the control signal Sc”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with wherein the current redistribution circuit conducts a current to or from the third node, and wherein the current conducted by the current redistribution circuit to or from the third node is the sum of the first and second base resupply currents as suggested by Tai to improve the linearity of the reference voltage in response to the temperature.
9. Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al in view of Tai and US Patent No. 5,684,394; (hereinafter Sano et al, Tai and Marshall).
Regarding claim 8, Sano et al discloses the claimed invention except for the first current leg comprises a first P-channel cascode transistor, wherein the second current leg comprises a second P- channel cascode transistor, and wherein a gate of the first P-channel cascode transistor is coupled to a gate of the second P-channel cascode transistor.
Marshall [e.g., Fig. 2] teaches the first current leg comprises a first P-channel cascode transistor [e.g., first current leg corresponding to P-channel transistor MP1 with cascode P-channel transistor MP3], wherein the second current leg comprises a second P- channel cascode transistor [e.g., second current leg corresponding to P-channel transistor MP2 with cascode P-channel transistor MP4], and wherein a gate of the first P-channel cascode transistor is coupled to a gate of the second P-channel cascode transistor [e.g., gates of MP3 and MP4 coupled].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Sano et al with the first current leg comprises a first P-channel cascode transistor, wherein the second current leg comprises a second P- channel cascode transistor, and wherein a gate of the first P-channel cascode transistor is coupled to a gate of the second P-channel cascode transistor as suggested by Marshall to create a higher output impedance and improve linearity of the current mirror circuit as commonly known and understood in the art.
Examiner’s Note
10. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
11. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Allowable Subject Matter
12. Claims 2, 4 - 7, 10, 11, 13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 2 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “the first and second base resupply currents are identical currents”.
The primary reason for the indication of the allowability of claim 4 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the current redistribution circuit comprises: a third transistor having source and a drain and a gate, wherein the first base resupply current flows into the drain of the third transistor; a first resistor coupled between the source of the third transistor and the base node; a fourth transistor having source and a drain and a gate, wherein the second base resupply current flows into the drain of the fourth transistor, wherein the gate of the fourth transistor is coupled to the gate of the third transistor; and a second resistor coupled between the source of the fourth transistor and the base node”.
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the Rtail resistor circuit comprises: a resistor string having a plurality of tap nodes; and an analog demultiplexer switch that has an input lead, wherein the analog demultiplexer switch can programmably couple the input lead to a selected one of the plurality of tap nodes”.
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the Rtail resistor circuit comprises: a first resistor string having a plurality of first tap nodes; a first analog demultiplexer switch that has an input lead, wherein the first analog demultiplexer switch can programmably couple the input lead of the first analog demultiplexer switch to a selected one of the plurality of first tap nodes; a second resistor string having an end node and a plurality of second tap nodes, wherein the end node of the second resistor string is coupled to one of the first tap nodes first resistor string; and a second analog demultiplexer switch that has an input lead, wherein the second analog demultiplexer switch can programmably couple the input lead of the second analog demultiplexer switch to a selected one of the plurality of second tap nodes”.
The primary reason for the indication of the allowability of claim 13 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “the first and second base resupply currents are identical to one another”.
The primary reason for the indication of the allowability of claim 18 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “the first current mirror leg of the current mirror comprises a first current leg transistor, wherein the first current leg transistor has a drain, wherein the fourth node and the drain of the first current leg transistor are not the same node [e.g., node shared between drain of X1, drain of 6102 and Q1]; wherein the second current mirror leg of the current mirror comprises a second current leg transistor, wherein the second current leg transistor has a drain, and wherein the fifth node and the drain of the second current leg transistor are not the same node”.
Conclusion
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838