DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 3/9/2026 has been entered. Claims 1-22 remain pending in the application. Applicant’s amendments to Claims have overcome the 112(b) rejection previously set forth in the Non-Final Office Action mailed on 12/18/2025.
Response to Arguments
Applicant’s arguments on pages 6-9 with respect to claims 1 and 22 have been considered but are moot upon a further consideration and a new ground of rejection made under 35 U.S.C. 102(a)(2) as being anticipated by Edblad (US Patent 5,327,468).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Edblad (US Patent 5,327,468).
Regarding claims 1 and 22, Edblad teaches a system (Edblad, see abstract, a counter rotating ring network of a distributed processing system), comprising:
a plurality of compute nodes (Edblad, see figure 1 and column 4 lines 15-16, FIG. 1 illustrates a distributed processing network system 1 having a plurality of stations 3a-d);
clock connections to connect at least some of the compute nodes and to distribute a master clock among the at least some compute nodes (Edblad, see column 5 lines 14-17, The present invention achieves use synchronization between station clocks with the required accuracy by providing in each network interface a free running counter 19 with a latch 21); and
processing circuitry to discover a clock distribution topology formed by the at least some compute nodes and the clock connections (Edblad, see column 6 lines 10-16, the station management level of the FDDI network determines the current topology of the network), wherein the processing circuitry is to:
cause the at least some compute nodes to send out test signals along the clock connections (Edblad, see column 7 lines 1-7, each of the stations upon the receipt of the time-of-day message containing the timekeeper time of day. The routine begins by reading at 53 the current values of the free-running counter and the operating system time-of-day clock, and also the latched count);
selectively disable output of clock signals generated by the at least some compute nodes to yield the test signals (Edblad, see column 6 lines 10-16, Clock synchronization must be temporarily suspended when the network reconfigures. Clock synchronization is resumed when the topology of the network has been established. As mentioned the station management level of the FDDI network determines the current topology of the network); and
discover the clock distribution topology based on detected receipt of the test signals (Edblad, see column 7 lines 9-20, The network delay from this station to the timekeeper station is then calculated at 57 based upon the network topology. That is, the repeater delay for each of the intermediate stations is added to the total delay for the length of communications media between the timekeeper station and local station for the path taken by the message. An adjustment is then calculated at 59 by first subtracting the network delay from the timekeeper's time of delay and then subtracting the reception time calculated in 55. This adjustment is then used to adjust the local time-of-day clock at 61 before the routine is exited at 63).
Regarding claim 2, Edblad teaches wherein the processing circuitry is to identify the discovered clock distribution topology as including a loop topology wherein the clock connections connect the compute nodes in a loop such that the compute nodes are configured to distribute the master clock around the loop from one of the compute nodes to another one of the compute nodes (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 3, Edblad teaches wherein the processing circuitry is to identify the discovered topology as including a chain topology wherein the clock connections connect the compute nodes in a chain such that the compute nodes are configured to distribute the master clock along the chain from one of the compute nodes to another one of the compute nodes (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 4, Edblad teaches wherein the processing circuitry is to identify the discovered topology as including a tree topology wherein the clock connections connect the compute nodes from a root node of the compute nodes to other ones of the compute nodes (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 5, Edblad teaches wherein the processing circuitry is to identify the discovered topology as including a tree topology, a chain topology, and a loop topology (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 6, Edblad teaches wherein the processing circuitry is to validate the discovered clock distribution topology as being the same as an expected clock distribution topology (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 7, Edblad teaches wherein the processing circuitry is to check that the discovered topology allows distribution of the master clock from one of the compute nodes to all remaining ones of the compute nodes (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 8, Edblad teaches wherein the processing circuitry is to identify one of the compute nodes that cannot receive the master clock from a root node of the compute nodes (Edblad, see column 4 lines 23-34, the FDDI network standard is used. In such a network, the two rings 7 and 9 include optic fibers for the communications media. In other networks, coaxial cable or a twisted wire pair could be used for the communications media. The FDDI network has an open network architecture. The FDDI network includes a station management standard, which among other things, controls the configuration of the network. Under normal conditions, when the station 3 transmits a message, the message is carried by one of the rings to each station in sequence which repeats the message for the next station).
Regarding claim 9, Edblad teaches wherein:
the processing circuitry is to cause the compute nodes to send out the test signals along the clock connections (Edblad, see column 7 lines 1-7, each of the stations upon the receipt of the time-of-day message containing the timekeeper time of day. The routine begins by reading at 53 the current values of the free-running counter and the operating system time-of-day clock, and also the latched count);
the compute nodes are to detect receipt of the test signals (Edblad, see column 6 lines 10-16, Clock synchronization must be temporarily suspended when the network reconfigures. Clock synchronization is resumed when the topology of the network has been established. As mentioned the station management level of the FDDI network determines the current topology of the network); and
the processing circuitry is to discover the topology based on the detected receipt of the test signals (Edblad, see column 7 lines 9-20, The network delay from this station to the timekeeper station is then calculated at 57 based upon the network topology. That is, the repeater delay for each of the intermediate stations is added to the total delay for the length of communications media between the timekeeper station and local station for the path taken by the message. An adjustment is then calculated at 59 by first subtracting the network delay from the timekeeper's time of delay and then subtracting the reception time calculated in 55. This adjustment is then used to adjust the local time-of-day clock at 61 before the routine is exited at 63).
Regarding claim 10, Edblad teaches wherein the processing circuitry is to:
identify source and destination compute nodes of the test signals based on the detected receipt of the test signals (Edblad, see column 7 lines 1-7, each of the stations upon the receipt of the time-of-day message containing the timekeeper time of day. The routine begins by reading at 53 the current values of the free-running counter and the operating system time-of-day clock, and also the latched count);
find at least one route along the clock connections from a root node of the compute nodes to all remaining ones of the compute nodes based on the identified source and destination compute nodes of the test signals (Edblad, see column 6 lines 10-16, Clock synchronization must be temporarily suspended when the network reconfigures. Clock synchronization is resumed when the topology of the network has been established. As mentioned the station management level of the FDDI network determines the current topology of the network); and
discover the topology based on the found at least one route (Edblad, see column 7 lines 9-20, The network delay from this station to the timekeeper station is then calculated at 57 based upon the network topology. That is, the repeater delay for each of the intermediate stations is added to the total delay for the length of communications media between the timekeeper station and local station for the path taken by the message. An adjustment is then calculated at 59 by first subtracting the network delay from the timekeeper's time of delay and then subtracting the reception time calculated in 55. This adjustment is then used to adjust the local time-of-day clock at 61 before the routine is exited at 63).
Regarding claim 11, Edbald teaches wherein the processing circuitry is to selectively disable output of clock signals generated by the compute nodes in order to enable the compute nodes to output the clock signals one at a time to yield the test signals (Edblad, see column 6 lines 10-16, Clock synchronization must be temporarily suspended when the network reconfigures. Clock synchronization is resumed when the topology of the network has been established. As mentioned the station management level of the FDDI network determines the current topology of the network).
Regarding claim 12, Edbald teaches wherein the clock signals include pulses that indicate clock time (Edblad, see column 5 lines 22-25, one of the stations is designated as the timekeeper station. This station periodically transmits a timing signal over the network 5 to each of the other stations).
Regarding claim 13, Edbald teaches wherein the clock signals are n pulse per second (PPS) signals, wherein n is a positive integer (Edblad, see column 5 lines 22-25, one of the stations is designated as the timekeeper station. This station periodically transmits a timing signal over the network 5 to each of the other stations).
Regarding claim 14, Edbald teaches wherein the clock signals have a frequency indicative of clock frequency (Edblad, see column 5 lines 22-25, one of the stations is designated as the timekeeper station. This station periodically transmits a timing signal over the network 5 to each of the other stations).
Regarding claim 15, Edbald teaches wherein each of the compute nodes includes hardware logic to determine receipt, or lack of receipt, of one of the test signals (Edblad, see figure 1 and column 4 lines 15-16, FIG. 1 illustrates a distributed processing network system 1 having a plurality of stations 3a-d).
Regarding claim 16, Edbald teaches where the distributed master clock is indicative of a frequency of a master clock (Edblad, see column 5 lines 22-25, one of the stations is designated as the timekeeper station. This station periodically transmits a timing signal over the network 5 to each of the other stations).
Regarding claim 17, Edbald teaches wherein the distributed master clock is indicative of a time of a master clock (Edblad, see column 5 lines 22-25, one of the stations is designated as the timekeeper station. This station periodically transmits a timing signal over the network 5 to each of the other stations).
Regarding claim 18, Edbald teaches wherein the compute nodes include corresponding network interface controllers (Edblad, see figure 1 and column 4 lines 15-16, FIG. 1 illustrates a distributed processing network system 1 having a plurality of stations 3a-d).
Regarding claim 19, Edbald teaches wherein the compute nodes include corresponding central processing units (Edblad, see column 4 lines 29-31, The FDDI network includes a station management standard, which among other things, controls the configuration of the network).
Regarding claim 20, Edbald teaches wherein the compute nodes include corresponding graphic processing units (Edblad, see column 4 lines 29-31, The FDDI network includes a station management standard, which among other things, controls the configuration of the network).
Regarding claim 21, Edbald teaches wherein the compute nodes include corresponding network switches (Edblad, see figure 1 and column 4 lines 15-16, FIG. 1 illustrates a distributed processing network system 1 having a plurality of stations 3a-d).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHONG G KIM whose telephone number is (571)270-0619. The examiner can normally be reached Mon-Fri @ 9am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nicholas R. Taylor can be reached at 571-272-3889. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHONG G KIM/Examiner, Art Unit 2443
/NICHOLAS R TAYLOR/Supervisory Patent Examiner, Art Unit 2443
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