Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This is the initial office action based on the application filed on January 08th, 2024, which claims 1-20 are presented for examination.
Status of Claims
3. Claims 1-20 are pending, of which claims, of which claim 1 and 11 are in independent form.
Priority
4. No priority has been considered for this application.
Information Disclosure Statement
5. Information disclosure statement filed on 04/09/2024, has been reviewed and considered by Examiner.
The Office's Note:
6. The Office has cited particular paragraphs / columns and line numbers in the reference(s) applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim(s), other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the cited passages as taught by the prior art or relied upon by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 1-20 rejected under 35 U.S.C. 103(a) as being unpatentable over Wang US 20240045672 (hereinafter Wang) and further in view Kandula US 20240329130 (hereinafter Kandula).
Claim 1 rejected, Wang teaches a system, comprising a computing device, including (Wang, abstract and summary):
a data interface to connect to and share data with configuration space registers of a silicon chip via an external physical interface of the silicon chip (Wang, US 20240045672, fig. 1, Integrated development environment, Embedded terminal, Cloud forwarding platform and para [0085-0092], In terms of the functions of all parts, the RO-IDE software architecture on the general-purpose computer, as the main site for development, is typically divided into three parts: basic functions, core functions and extended functions. Wherein, the basic functions mainly include code editing, program compilation and memory reading/writing; the core functions mainly include program updating and software debugging; the extended functions complete the access of additional functions by means of extended function interfaces. The cloud forwarding program of the cloud forwarding platform, as the bridge between the RO-IDE and the BIOS program of the terminal node, and is mainly responsible for transmitting information between these two when memory reading/writing, program updating and software debugging are carried out remotely. The BIOS program in the terminal node is reserved with an interface for interaction with the RO-IDE to assist the RO-IDE to perform memory reading/writing, program updating and software debugging for the user program.); and
a processing unit to (Wang, fig. 1, Integrated development environment and para [0088-0092]):
execute a procedure to update parts of firmware source code configured to access the configuration space registers from a firmware processor embedded on the silicon chip via an internal physical interface of the silicon chip to access the configuration space registers via the data interface and via the external physical interface of the silicon chip, yielding modified firmware source code (Wang, 3.2 Basic Functional Design of RO-IDE, para [0093-0099], Memory reading/writing is a practical tool for developers to check the storage space of the current embedded terminal and is also a simple application of dynamic commands. The main operating logic of memory reading/wiring is as follows: after a connection between software on the general-purpose computer and the BIOS program of the embedded terminal is established, the software on the upper computer sends a dynamic command package for memory reading/writing to the BIOS program and requests an address range of the currently accessible memory space of the embedded terminal to the BIOS program, which is received by the upper computer and fed back in the graphical interface. At this point, the users start issue a reading/writing request to check or modify the contents of the corresponding memory space. Wang, 3.3 Core Functional Design of the RO-IDE and para [0100-0106], The core functions of RO-IDE include remote updating and debugging of embedded terminal software.); and
execute a software compiler to compile the modified firmware source code yielding compiled software (Wang, para [0012-0016], the IDE module has functions of code editing, code analysis, program compilation, software debugging, software updating, and memory reading/writing. Para [0037], IDE: the IDE is the main site for software development of embedded terminals and generally has the functions such as code editing, code analysis, program compilation, software debugging and program updating. Under the background of remote online development, the functions such as software debugging and program updating need to establish a communication connection with the cloud forwarding platform to transmit data to the embedded terminals to complete the corresponding functions. Wang, 2. Program Compilation and para [0096-0100], The RO-IDE uses a GCC (GNU Compiler Collection) compiler, which supports multiple languages and target device extension, as a tool to complete program compilation in a GNU cross-compilation mode. In order to improve efficiency, a GNU suite provides a Make tool to shield GCC instructions and to rely on Makefile. The Makefile defines compilation and connection rules, specifies the order in which different files are compiled, and controls the generation process of an underlying program from a source code file to an executable file. The Makefile also specifies target files, dependency files and corresponding control instructions generated by compilation.).
The Office would like to use prior art Kandula to back up Wang to further to teach limitation
configuration space registers (Kandula, US 20240329130, fig. 2 SOC 200 and para [0041-0044], FIG. 2 illustrates examples of an architecture for allowing access to a TAP network by an external debugger and infield firmware. As shown, there are two register spaces that may be accessible to a debugger 221—a TAP accessible register space 209 and an infield testing FW accessible register space 207. In some examples, the infield testing FW accessible register space 207 includes IFT control registers and debug/status registers. The IFT control registers are used to control a debug and the IFT debug/status registers are used to indicate the progress of infield tests. In some examples, both types of registers can be accessed by the infield testing FW 205 alone and/or by external debugger 221 alone or simultaneously by both. Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration.)
It would have obvious to one having ordinary skill in the art before the effecting filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effecting filing date of the claimed invention would have been motivated to incorporate Kandula into Wang to enable performing infield testing to allow to detect faults in an autonomous driving system prior to its usage and while in the field, that ensures proper behavior of an automotive SoC in an efficient manner as suggested by Kandula (See abstract and summary).
Claim 2 is rejected for the reasons set forth hereinabove for claim 1, Wang and Kandula teach the system according to claim 1, wherein the processing unit is to execute the compiled software to cause the data interface to read from, and write to,the configuration space registers of the silicon chip via the external physical interface of the silicon chip(Wang, 3.2 Basic Functional Design of RO-IDE, para [0093-0099], Memory reading/writing is a practical tool for developers to check the storage space of the current embedded terminal and is also a simple application of dynamic commands. The main operating logic of memory reading/wiring is as follows: after a connection between software on the general-purpose computer and the BIOS program of the embedded terminal is established, the software on the upper computer sends a dynamic command package for memory reading/writing to the BIOS program and requests an address range of the currently accessible memory space of the embedded terminal to the BIOS program, which is received by the upper computer and fed back in the graphical interface. At this point, the users start issue a reading/writing request to check or modify the contents of the corresponding memory space. Wang, 3.3 Core Functional Design of the RO-IDE and para [0100-0106], The core functions of RO-IDE include remote updating and debugging of embedded terminal software. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration).
Claim 3 is rejected for the reasons set forth hereinabove for claim 2, Wang and Kandula teach the system according to claim 2, wherein the processing unit is to execute the compiled software to perform computations based on the configuration space registers (Wang, para [0017], Further, the IDE module is capable of entering remote updating of embedded terminal software, comprising: [0018] Sending dynamic command data to a user port, and writing the dynamic command data by a user program; [0019] Sending a system instruction for program jumping to the user port, and jumping to BIOS after the user program receives the system instruction; [0020] Calling a dynamic command function by default during a BIOS starting process; modifying a program running state in a dynamic command first to complete a stay in BIOS; then, completing initialization and interrupt enable of the user port; setting an address of an interrupt service routine corresponding to the user port in a BIOS program interrupt vector table as the dynamic command function; finally, informing an upper computer that relevant initialization steps have been executed and a program update is to be started; [0021] Starting to send data frames of the user program to the user port by the upper computer, and receiving, checking and writing the data frames of the user program by the terminal by means of the dynamic command from the user port; and [0022] When the dynamic command from the user port finishes processing the last frame of data, modifying the program running state, resetting BIOS, and completing subsequent guidance on the user program by means of a BIOS basic process. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration ).
Claim 4 is rejected for the reasons set forth hereinabove for claim 3, Wang and Kandula teach the system according to claim 3, further comprising the silicon chip, which includes:
hardware logic to operate based on data stored in the configuration space registers(Wang, para [0035-0040], Embedded terminal: a hardware platform of the embedded terminal typically consists of a master chip minimal system, a communication module and a peripheral circuit thereof, a power conversion circuit and other auxiliary circuits, and constitutes a hardware entity with an information collection and control function, together with an access sensor. The software part of the embedded terminal is used by developers to design and fulfill specific functions with an MCU as the core, and completes the functions of data collection, transmission, storage, control and operation in combination with hardware. Para [0095-100], For the main window of code writing, the invention modifies the functions such as text finding and replacing and jumping between variable/function declarations and definitions based on the use of an open source control ICSharpCode, in terms of the background requirements of embedded application development. Considering the nesting of micro definitions of a large number of embedded registers during embedded application development, multi-threading is used to improve the finding efficiency when specific texts are to be found, and regular expressions are used to fulfill the functions such as case-sensitive and full-word matching finding. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration); and
the embedded firmware processor (Wang, fig. 2 and para [0059-0065], Embedded terminal: a hardware platform of the embedded terminal typically consists of a master chip minimal system, a communication module and a peripheral circuit thereof, a power conversion circuit and other auxiliary circuits, and constitutes a hardware entity with an information collection and control function, together with an access sensor. The software part of the embedded terminal is used by developers to design and fulfill specific functions with an MCU as the core, and completes the functions of data collection, transmission, storage, control and operation in combination with hardware.).
Claim 5 is rejected for the reasons set forth hereinabove for claim 4, Wang and Kandula teach the system according to claim 4, wherein:
the processing unit is to execute a firmware compiler to compile the firmware source code to yield compiled firmware(Wang, para [0037-0042], IDE: the IDE is the main site for software development of embedded terminals and generally has the functions such as code editing, code analysis, program compilation, software debugging and program updating. Under the background of remote online development, the functions such as software debugging and program updating need to establish a communication connection with the cloud forwarding platform to transmit data to the embedded terminals to complete the corresponding functions. Wang, 2. Program Compilation and para [0096-0100], The RO-IDE uses a GCC (GNU Compiler Collection) compiler, which supports multiple languages and target device extension, as a tool to complete program compilation in a GNU cross-compilation mode. In order to improve efficiency, a GNU suite provides a Make tool to shield GCC instructions and to rely on Makefile. The Makefile defines compilation and connection rules, specifies the order in which different files are compiled, and controls the generation process of an underlying program from a source code file to an executable file. The Makefile also specifies target files, dependency files and corresponding control instructions generated by compilation.); and
the embedded firmware processor of the silicon chip is to execute the compiled firmware (Wang, 3. Function Division of the GEC Software Architecture. Para [0067-0076] The function division of the GEC architecture is performed mainly in two aspects: the BIOS project and the User project.).
Claim 6 is rejected for the reasons set forth hereinabove for claim 5, Wang and Kandula teach the system according to claim 5, wherein:
the processing unit is to write the compiled firmware on a memory (Wang, para [0068-0069], The updating of the local programs of the User project means that BIOS obtains a machine code of the User project through a certain communication method (generally serial communication) and writes the machine code into Flash from a start address of a specified User program area after erasing an old version of the project. In most cases, the program cannot update itself while running, so when there is a need to update the User project, the running environment of the system will be switched from the User project to the BIOS project, and the BIOS project is responsible for subsequent reception, verification and writing of the machine code. Taking the GEC architecture of STM 32 as an example, the main steps for updating the local programs of the User project are as follows:); and
the embedded firmware processor is to load the compiled firmware from the memory(Wang, para [0071-0072], First, jump and stay in BIOS: when the IDE sends main update information to the chip, a variable marking the update state in BIOS will be modified within a serial port interrupt, and a soft reset function of a core is called to pull the chip back to BIOS. Before a regular User program jump is executed, a gcUpdateFlag variable will be detected, so that the User program will not jump and will stay in BIOS to run.).
Claim 7 is rejected for the reasons set forth hereinabove for claim 5, Wang and Kandula teach the system according to claim 5, wherein the compiled firmware is to:
cause the embedded firmware processor to read from, and write to, the configuration space registers of the silicon chip via the internal physical interface of the silicon chip (Wang, fig. 2, 3. Memory Reading/Writing and para [0099], Memory reading/writing is a practical tool for developers to check the storage space of the current embedded terminal and is also a simple application of dynamic commands. The main operating logic of memory reading/wiring is as follows: after a connection between software on the general-purpose computer and the BIOS program of the embedded terminal is established, the software on the upper computer sends a dynamic command package for memory reading/writing to the BIOS program and requests an address range of the currently accessible memory space of the embedded terminal to the BIOS program, which is received by the upper computer and fed back in the graphical interface. At this point, the users start issue a reading/writing request to check or modify the contents of the corresponding memory space. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration); and
cause the embedded firmware processor to perform computations based on data stored in the configuration space registers (Wang, para [0100-0107], A method for remote updating of the embedded terminal software comprises: [0102] Sending dynamic command data to a user port and writing the dynamic data by a user program; [0103] Sending a system command for program jumping to the user port, and jumping to BIOS when the user program receives the system command; [0104] Calling a dynamic command function by default during a BIOS starting process; modifying a program running state in a dynamic command first to complete a sta in BIOS; then, completing initialization and interrupt enable of the user port; setting an address of an interrupt service routine, corresponding to the user serial port, in a BIOS program interrupt vector table as a dynamic command function; finally, informing an upper computer that relevant initialization steps have been executed and a program update is to be started; [0105] Starting to send user program data frames to the user port by the upper computer, and complecting receiving, checking and writing by a terminal through a dynamic command from the user port; and [0106] When the dynamic command from the user port finishes processing the last frame of data, modifying the running state of the program, resetting BIOS, and completing subsequent guidance on the user program through a BIOS base running process. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration).
Claim 8 is rejected for the reasons set forth hereinabove for claim 2, Wang and Kandula teach the system according to claim 2, wherein the processing unit is to:
execute the procedure to update parts of a new version of the firmware source code configured to access the configuration space registers from the embedded firmware processor via the internal physical interface to access the configuration space registers via the data interface and via the external physical interface of the silicon chip, yielding a modified version of the new version of the firmware source code(Wang, 3.2 Basic Functional Design of RO-IDE, para [0093-0099], Memory reading/writing is a practical tool for developers to check the storage space of the current embedded terminal and is also a simple application of dynamic commands. The main operating logic of memory reading/wiring is as follows: after a connection between software on the general-purpose computer and the BIOS program of the embedded terminal is established, the software on the upper computer sends a dynamic command package for memory reading/writing to the BIOS program and requests an address range of the currently accessible memory space of the embedded terminal to the BIOS program, which is received by the upper computer and fed back in the graphical interface. At this point, the users start issue a reading/writing request to check or modify the contents of the corresponding memory space. Wang, 3.3 Core Functional Design of the RO-IDE and para [0100-0106], The core functions of RO-IDE include remote updating and debugging of embedded terminal software. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration);
execute the software compiler to compile the modified version of the new version of the firmware source code yielding newly compiled software (Wang, para [0037-0042], IDE: the IDE is the main site for software development of embedded terminals and generally has the functions such as code editing, code analysis, program compilation, software debugging and program updating. Under the background of remote online development, the functions such as software debugging and program updating need to establish a communication connection with the cloud forwarding platform to transmit data to the embedded terminals to complete the corresponding functions. Wang, 2. Program Compilation and para [0096-0100], The RO-IDE uses a GCC (GNU Compiler Collection) compiler, which supports multiple languages and target device extension, as a tool to complete program compilation in a GNU cross-compilation mode. In order to improve efficiency, a GNU suite provides a Make tool to shield GCC instructions and to rely on Makefile. The Makefile defines compilation and connection rules, specifies the order in which different files are compiled, and controls the generation process of an underlying program from a source code file to an executable file. The Makefile also specifies target files, dependency files and corresponding control instructions generated by compilation.); and
execute the newly compiled software to cause the data interface to read from, and write to, the configuration space registers of the silicon chip via the external physical interface of the silicon chip(Wang, 3.2 Basic Functional Design of RO-IDE, para [0093-0099], Memory reading/writing is a practical tool for developers to check the storage space of the current embedded terminal and is also a simple application of dynamic commands. The main operating logic of memory reading/wiring is as follows: after a connection between software on the general-purpose computer and the BIOS program of the embedded terminal is established, the software on the upper computer sends a dynamic command package for memory reading/writing to the BIOS program and requests an address range of the currently accessible memory space of the embedded terminal to the BIOS program, which is received by the upper computer and fed back in the graphical interface. At this point, the users start issue a reading/writing request to check or modify the contents of the corresponding memory space. Wang, 3.3 Core Functional Design of the RO-IDE and para [0100-0106], The core functions of RO-IDE include remote updating and debugging of embedded terminal software. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration).
Claim 9 is rejected for the reasons set forth hereinabove for claim 8, Wang and Kandula teach the system according to claim 8, wherein the processing unit is to:
run at least one debug method of the compiled software (Wang, para [0092-0099], In terms of the functions of all parts, the RO-IDE software architecture on the general-purpose computer, as the main site for development, is typically divided into three parts: basic functions, core functions and extended functions. Wherein, the basic functions mainly include code editing, program compilation and memory reading/writing; the core functions mainly include program updating and software debugging; the extended functions complete the access of additional functions by means of extended function interfaces. The cloud forwarding program of the cloud forwarding platform, as the bridge between the RO-IDE and the BIOS program of the terminal node, and is mainly responsible for transmitting information between these two when memory reading/writing, program updating and software debugging are carried out remotely. The BIOS program in the terminal node is reserved with an interface for interaction with the RO-IDE to assist the RO-IDE to perform memory reading/writing, program updating and software debugging for the user program.); and
receive a correction to the firmware source code yielding the new version of the firmware source code (Wang, para [0071-0072], First, jump and stay in BIOS: when the IDE sends main update information to the chip, a variable marking the update state in BIOS will be modified within a serial port interrupt, and a soft reset function of a core is called to pull the chip back to BIOS. Before a regular User program jump is executed, a gcUpdateFlag variable will be detected, so that the User program will not jump and will stay in BIOS to run.).
Claim 10 is rejected for the reasons set forth hereinabove for claim 1, Wang and Kandula teach the system according to claim 1,
wherein the processing unit is to execute the compiled software to cause the data interface to read from, and write to, other configuration space registers of another silicon chip, which does not have an embedded firmware processor, via an external physical interface of the other silicon chip (Wang, para [0084-0099], The network principle for using FRP intranet traversal may be understood with reference to FIG. 4. Developers can install the cloud forwarding program on their own computer and also install an FRP client software on this computer, and the FRP client software establishes a connection with an FRP server software on the cloud server. The FRP server software maps the cloud forwarding program on an intranet to a public IP of the cloud server. The developer computer accessing the extranet, and the cloud server together form a new cloud forwarding platform to provide services for the embedded terminal and the IDE. At this point, both the embedded terminal and the IDE can access the cloud forwarding program running on the developer computer in the same way as accessing the public IP. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration.).
As per claim 11, this is the method claim to system claim 1. Therefore, it is rejected for the same reasons as above.
As per claim 12, this is the method claim to system claim 2. Therefore, it is rejected for the same reasons as above.
As per claim 13, this is the method claim to system claim 3. Therefore, it is rejected for the same reasons as above.
Claim 14 is rejected for the reasons set forth hereinabove for claim 13, Wang and Kandula teach the method according to claim 13, further comprising hardware logic of the silicon chip operating based on data stored in the configuration space registers(Wang, para [0035-0040], Embedded terminal: a hardware platform of the embedded terminal typically consists of a master chip minimal system, a communication module and a peripheral circuit thereof, a power conversion circuit and other auxiliary circuits, and constitutes a hardware entity with an information collection and control function, together with an access sensor. The software part of the embedded terminal is used by developers to design and fulfill specific functions with an MCU as the core, and completes the functions of data collection, transmission, storage, control and operation in combination with hardware. Para [0095-100], For the main window of code writing, the invention modifies the functions such as text finding and replacing and jumping between variable/function declarations and definitions based on the use of an open source control ICSharpCode, in terms of the background requirements of embedded application development. Considering the nesting of micro definitions of a large number of embedded registers during embedded application development, multi-threading is used to improve the finding efficiency when specific texts are to be found, and regular expressions are used to fulfill the functions such as case-sensitive and full-word matching finding. Kandula, Fig. 3 and para [0045-0046], This illustration shows the infield accessible control and debug/status registers 301 as being mapped (shown as path 1) into the infield testing FW (memory mapped (MMIO)) register space 207 accessible by the infield microcontroller 205. Fig. 7 and para [0060-0065], FIG. 7 illustrates examples of a method of using configurable IFT register allocation. At 701 control and debug/status registers accessibility is configured. For example, an external debugger may be used to configure how the registers are configured (where they are stored or duplicated). In some examples, this is a selection of a pre-programmed configuration); and
As per claim 15, this is the method claim to system claim 5. Therefore, it is rejected for the same reasons as above.
As per claim 16, this is the method claim to system claim 6. Therefore, it is rejected for the same reasons as above.
As per claim 17, this is the method claim to system claim 7. Therefore, it is rejected for the same reasons as above.
As per claim 18, this is the method claim to system claim 8. Therefore, it is rejected for the same reasons as above.
As per claim 19, this is the method claim to system claim 9. Therefore, it is rejected for the same reasons as above.
As per claim 20, this is the method claim to system claim 10. Therefore, it is rejected for the same reasons as above.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY KHUONG THANH NGUYEN whose telephone number is (571)270-7139. The examiner can normally be reached M-F 8 to 5.
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/DUY KHUONG T NGUYEN/Primary Examiner, Art Unit 2199
Prosecution Insights