Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to the original filing of 01/08/2024. Claims 1-13 are pending and have been considered below.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al (US 2020/0160146) in view of Valentian et al. (US 2020/0019850 A1).
Claim 1. Oh discloses a spiking neural network circuit comprising:
an axon circuit configured to generate an input spike signal ([0021], circuit 100, fig. 1);
a synapse circuit configured to output a current based on the input spike signal and a weight ([0027]-[0028], fig. 2 CS1/MP1);
a capacitor configured to form a membrane voltage based on the current ([0037]); and
a neuron circuit configured to generate an output spike signal based on the membrane voltage ([0006]-[0007], abstract), and wherein the neuron circuit includes: a first comparator configured to generate an intermediate spike signal (conditional bias current) based on the membrane voltage and a first reference voltage ([0034]-[0035]);
Oh does not explicitly disclose a second comparator configured to generate the output spike signal based on the intermediate spike signal, the membrane voltage, and a second reference voltage that is different from the first reference voltage.
However, Valentian discloses a second comparator configured to generate the output spike signal based on the intermediate spike signal, the membrane voltage, and a second reference voltage that is different from the first reference voltage (second regulation comparator and a same low threshold comparator to constitute the second action comparator and the first regulation comparator) ([0042])….( Vthreshold_low and Vthreshold_high…Threshold-exceed register/regulator supplies the control relationship) (abstract, [0016], [0026]-[0028, [0032]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify OH with Valentian features. One would have been motivated to employ a lower-threshold comparator to identify a membrane-voltage excursion before enabling a higher-threshold comparison would have been a predictable implementation of the conditional comparator operation, using the known multiple-threshold architecture of Valentian, with a reasonable expectation of achieving controlled and reduced comparator operation.
Claim 2. Oh and Valentian disclose the spiking neural network circuit of claim 1, Valentian further discloses wherein the first reference voltage is lower than the second reference voltage (identifies a lower regulation threshold (Vthreshold_low) and a higher action threshold (Vthreshold_high). The lower threshold is associated with the regulation comparator, while the higher threshold is associated with the action comparator) (abstract). One would have been motivated to achieve controlled and reduced comparator operation.
Claim 3. Oh and Valentian disclose the spiking neural network circuit of claim 1, Oh further discloses wherein the first comparator includes a first input transistor having a first width and a first length, the second comparator includes a second input transistor having a second width and a second length, the second width is ‘n’ times the first width, and the second length is ‘n’ times the first length, and where ‘n’ is any natural number ([0043]-[0045]) [extensive transistor-level comparator disclosure—e.g., MN4/MN5 forming the comparison stage and MN6/MP6 forming a second stage—but the portions verified here do not establish the claimed proportional W/L relationship between two comparator input transistors].
Claim 4. Oh and Valentian disclose the spiking neural network circuit of claim 2, Oh further discloses comprising: a latch circuit configured to generate a high-precision comparator enable signal based on the intermediate spike signal, and wherein the second comparator operates only when a logic value of the high-precision comparator enable signal is ‘1’ (conditional comparator operation. Its bias circuit supplies comparator bias only when membrane voltage reaches the relevant operating condition. The reference expressly states that bias is not continuously supplied and that comparator operation is conditional on membrane voltage) ([0034]-[0035]).
Claim 5. Oh and Valentian disclose the spiking neural network circuit of claim 4, Valentian further discloses wherein, when the membrane voltage is greater than the first reference voltage, the first comparator outputs a logic value of the intermediate spike signal as ‘1’, the latch circuit outputs the logic value of the high-precision comparator enable signal as ‘1’ based on the logic value of the intermediate spike signal being ‘1’, and the second comparator compares the membrane voltage with the second reference voltage based on the logic value of the high-precision comparator enable signal being ‘1’ (..essentially this functional sequence using its lower regulation threshold and higher action threshold. The membrane voltage first exceeds the lower regulation threshold, which modifies the threshold-exceed state; when the higher action threshold is exceeded, the regulator uses the stored threshold-exceed state to determine whether to generate the action potential) ([0027]-[0042]). One would have been motivated to achieve controlled and reduced comparator operation.
Claim 11. Oh and Valentian disclose the method of claim 10, Valentian further discloses wherein the first reference voltage is lower than the second reference voltage (identifies a lower regulation threshold (Vthreshold_low) and a higher action threshold (Vthreshold_high). The lower threshold is associated with the regulation comparator, while the higher threshold is associated with the action comparator) (abstract). One would have been motivated to achieve controlled and reduced comparator operation.
Claim 12. Oh and Valentian disclose the method of claim 10, Oh further discloses wherein the generating, by the second comparator, of the output spike signal based on the intermediate spike signal, the membrane voltage, and the second reference voltage that is different from the first reference voltage includes: generating a high-precision comparator enable signal based on the intermediate spike signal; and when the logic value of the high-precision comparator enable signal is ‘1’, comparing, by the second comparator, the membrane voltage with the second reference voltage to generate the output spike signal (conditional comparator operation. Its bias circuit supplies comparator bias only when membrane voltage reaches the relevant operating condition. The reference expressly states that bias is not continuously supplied and that comparator operation is conditional on membrane voltage) ([0034]-[0035]).
Claim 13. Oh and Valentian disclose the method of claim 12, wherein the generating, by the first comparator, of the intermediate spike signal based on the membrane voltage and the first reference voltage includes: outputting, by the first comparator, a logic value of the intermediate spike signal as ‘1’ when the membrane voltage is greater than the first reference voltage, and wherein the generating of the high-precision comparator enable signal based on the intermediate spike signal ([0034]-[0035]) [first comparator outputs 1 when Vm >] includes: when the logic value of the intermediate spike signal is ‘1’, outputting the logic value of the high-precision comparator enable signal as ‘1’(second regulation comparator and a same low threshold comparator to constitute the second action comparator and the first regulation comparator) ([0042])….( Vthreshold_low and Vthreshold_high…Threshold-exceed register/regulator supplies the control relationship) (abstract, [0016], [0026]-[0028, [0032]) [high-precision enable = 1 when intermediate spike = 1]. One would have been motivated to employ a lower-threshold comparator to identify a membrane-voltage excursion before enabling a higher-threshold comparison to achieve controlled and reduced comparator operation.
Claim 10 is similar in scope as claim 1; therefore, the claim is rejected under the same rationale.
5. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al (US 2020/0160146) in view of Valentian et al. (US 2020/0019850 A1) and further in view of Young (KR 20200132444 A).
Claim 6. Oh and Valentian disclose the spiking neural network circuit of claim 1, Oh further discloses wherein the input spike signal is a first input spike signal, the axon circuit is a first axon circuit, and further comprising: a second axon circuit configured to generate a second input spike signal ([0021]-[0022]) [teach multiple axons and multiple input spikes. It explains that axon circuit 110 contains axons generating input spike signals and that the synaptic circuit can receive multiple input spike signals]. But fail to explicitly disclose an address encoder configured to receive an input address signal indicating one of the first axon circuit and the second axon circuit and a raw input signal, and to transfer the raw input signal to one of the first axon circuit and the second axon circuit in response to the input address signal.
However, Young discloses an address encoder configured to receive an input address signal indicating one of the first axon circuit and the second axon circuit and a raw input signal, and to transfer the raw input signal to one of the first axon circuit and the second axon circuit in response to the input address signal (p. 4 paragraph 2). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify OH with Young features. One would have been motivated to output the determined address of the target neuron.
Claim 7. Oh Valentian and Young disclose the spiking neural network circuit of claim 6, Young further discloses wherein the address encoder generates a comparator enable signal based on the raw input signal, and wherein the first comparator and the second comparator do not operate when a logic value of the comparator enable signal is ‘0’ (p. 11, para. 3, 4 ,6 and p. 12). One would have been motivated to output the determined address of the target neuron.
6. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al (US 2020/0160146) in view of Valentian et al. (US 2020/0019850 A1) and further in view of Lee et al. (KR 20220059292 A).
Claim 8. Oh and Valentian disclose the spiking neural network circuit of claim 1, Oh further discloses wherein the membrane voltage is a first membrane voltage, the capacitor is a first capacitor, the output spike signal is a first output spike signal, the neuron circuit is a first neuron circuit, and further comprising: a second capacitor configured to form a second membrane voltage; a second neuron circuit configured to generate a second output spike signal based on the second membrane voltage (figs. 1-3); and Oh and Valentian fail to explicitly disclose a WTA device configured to decrease the first membrane voltage and the second membrane voltage to a potential level of a ground power supply when one of the first output spike signal and the second output spike signal is received.
However, Lee discloses a WTA device configured to decrease the first membrane voltage and the second membrane voltage to a potential level of a ground power supply when one of the first output spike signal and the second output spike signal is received (p. 3 paragraph 7-8 and claim 2). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify OH with Young features. One would have been motivated to mitigate the problem of low integration and high power consumption.
Claim 9. Oh Valentian and Lee disclose the spiking neural network circuit of claim 8, Lee further discloses comprising: an address encoder, and wherein the address encoder is configured to: when the WTA device receives the first output spike signal, output an output address signal indicating the first neuron circuit, and when the WTA device circuit receives the second output spike signal, output an output address signal indicating the second neuron circuit(p. 3 paragraph 7-8 and claims 2, 9). One would have been motivated to mitigate the problem of low integration and high power consumption.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (See PTO-892).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phenuel S. Salomon whose telephone number is (571) 270-1699. The examiner can normally be reached on Mon-Fri 7:00 A.M. to 4:00 P.M. (Alternate Friday Off) EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Usmaan Saeed can be reached on (571) 272-4046. The fax phone number for the organization where this application or proceeding is assigned is 571-273-3800.
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/PHENUEL S SALOMON/Primary Examiner, Art Unit 2146
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