Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments / Arguments
Regarding the rejection(s) of claims under 35 USC 102:
Applicant’s arguments, filed 11/06/2025, have been fully considered and are partially persuasive. Applicant argues that "the first circuit block 203 and the second circuit block 204 of the present application are circuits that operate functions other than storing and running BIOS (for example, an auto-drive function for a vehicle)" and therefore differ from Noll's BIOS ROMs. This argument is not persuasive. The claim language "first circuit block" and "second circuit block" are broad terms that encompass any circuitry coupled to a CPU, regardless of specific function. Noll's primary BIOS ROM 22 with its associated circuitry (AND gate 44) and secondary BIOS ROM 30 with its associated circuitry (inverter 48 and AND gate 50) satisfy the requirements of "circuit blocks coupled to the CPU." The specific functions performed by these circuit blocks, whether BIOS operations or auto-drive control, are not claimed limitations and do not distinguish the invention from Noll.
Applicant argues that "the low state of ROMSEL2 is regarded as equivalent to both the second state...and the first state...of HNONSEC" creating a contradiction. However, this argument focuses on implementation details rather than functional correspondence. The essence of both systems is CPU-controlled access to backup firmware storage, not specific signal logic levels. Noll clearly teaches a CPU that controls access to different firmware storage devices through control signals (ROMSEL1 and ROMSEL2).
Applicant argues that the "security access signal" serves a different purpose than Noll's chip enable signals because "the access to the first circuit block, which is irrelevant to security, is irrelevant to the state of HNONSEC." The term "security access signal" in the context of the claimed invention encompasses any CPU-controlled access signal that regulates access to circuit blocks. Noll's ROMSEL signals serve precisely this access control function by enabling and disabling access to the primary and secondary BIOS ROMs based on error detection and system state. The fact that Noll's signals aren't specifically labeled "security" signals does not distinguish them functionally from the claimed security access signal.
However, applicants amendments to the claim are persuasive therefore the rejection is withdrawn, however it is further maintained under Marr et al. (US 20160019050 A1).
DETAILED ACTION
This is a reply to the application filed on 11/06/2025, in which, claims 1-10 are pending. Claims 1, and 6 are independent.
When making claim amendments, the applicant is encouraged to consider the references in their entireties, including those portions that have not been cited by the examiner and their equivalents as they may most broadly and appropriately apply to any particular anticipated claim amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Noll et al. (US 6185696 B1, referred to as Noll) in view of Marr et al. (US 20160019050 A1, referred to as Marr)
In reference to claim 1, An electronic device comprising: a storage device configured to store a plurality of firmware (Noll: Fig. 1 Col. 3 Lines 5-40 Provides for a computer (electronic device) with storage devices (primary BIOS ROM 22 and secondary BIOS ROM 30) that store multiple firmware (BIOS) programs.)
a central processing unit (CPU) coupled to the storage device and configured to output a security access signal (Noll: Col. 2 Lines 49-62 and Col. 3 Lines 54-65 Provides for a CPU coupled to the storage devices.)
a first circuit block coupled to the CPU (Noll: Fig. 1 Col. 3 Lines 5-40 Provides for the BIOS ROM 22 and its associated circuitry (AND gate 44) (first circuit block) that is coupled to the CPU.)
a second circuit block coupled to the CPU, wherein when the security access signal is in a first state, the first circuit block is allowed to be accessed by the CPU and the second circuit block is forbidden to be accessed by the CPU (Noll: Col. 3 Lines 5-54 and Col. 5 Lines 29-45 Provides for the secondary BIOS ROM 30 and its associated circuity (inverter 48 and AND gate 50) (second circuit block), when the ROMSEL2 control line is in a low state (second state of the security access signal), the secondary BIOS ROM is enabled and can be accessed by the CPU. Noll Col. 3 lines 20 - 55 Provides for normal state has primary BIOS enabled and secondary BIOS disabled, directly teaching the first circuit block accessible and second circuit block forbidden.)
a security protection circuit coupled between the CPU and the second circuit block, wherein: when the electronic device updates the plurality of firmware, a first firmware of the storage device is refreshed, and a second firmware is preserved (Noll: Col. 6 Line 5 – Col. 7 Line 51 Provides for reprogramming (refreshing) the primary BIOS ROM while preserving the secondary BIOS ROM during a firmware update process.)
after the firmware of the electronic device is updated, the updated first firmware is operated (Noll: Col. 7 Lines 30-51 Provides that after reprogramming the primary BIOS ROM, the system would continue to operate using the reprogrammed primary BIOS on subsequent boots.)
when the updated first firmware is unable to be operated, the first firmware is switched to the second firmware, and the security protection circuit is activated to enter a security mode (Noll: Col. 5 Lines 29-45 Provides for switching from the primary BIOS to the secondary BIOS when the primary BIOS has errors and cannot operate properly.)
when the security protection circuit is activated, the security access signal received by the second circuit block is set to the first state (Noll: Col. 5 Lines 29-45 Provides for when the chip enable circuit (security protection circuit) is activated due to errors in the primary BIOS, it sets the ROMSEL2 control line to a low logic level (first state of the security access signal). This signal, after going through the inverter, enables the secondary BIOS ROM.)
Noll does not explicitly teach when the security access signal is in a second state both the first circuit block and the second circuit block are allowed to be accessed by the CPU and receiving a firmware update message through over the air (OTA) when the security access signal is in a second state both the first circuit block and the second circuit block are allowed to be accessed by the CPU (Marr: [0068]-[0074] Provides for different access states during boot/mutability period both blocks could be accessible, but later access is restricted.) receiving a firmware update message through over the air (OTA) (Marr: [0051]-[0055] and [0082] Provides for firmware updates over networks.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Noll, which provides an electronic device with multiple firmware storage blocks and security protection circuits that enable firmware switching and preservation during updates, with the teachings of Marr, which introduces a state where both firmware blocks can be simultaneously accessible and over-the-air (OTA) firmware update capabilities. One of ordinary skill in the art would recognize the ability to incorporate Marr's dual-access state and OTA update mechanism into Noll's firmware protection system to enhance flexibility and modernize the update process. One of ordinary skill in the art would be motivated to make this modification in order to enable more efficient firmware update operations by allowing temporary simultaneous access to both firmware blocks during the update process and to provide modern wireless update capabilities.
In reference to claim 2, The electronic device according to claim 1, wherein the security protection circuit comprises: an error detection circuit configured to detect an operation error to determine whether to enter the security mode (Noll: Col. 3 Lines 65 – Col. 4 Line 24 Provides for an error detection circuit that detects operation errors in the primary BIOS ROM.)
A first logic gate including a first end, a second end and an output end, wherein the first end of the first logic gate receives the security access signal outputted by the CPU, the second end of the first logic gate is coupled to the error detection circuit, and the output end of the first logic gate is coupled to the second circuit block (Noll: Col. 3 Line 29 – Line 54 Provides for gate 50 (first logic gate) ites first end received the ROMSEL1 control line signal (security access signal), its second end is connected to circuitry that is influenced by the error detection circuit (via the inverter 48 and ROMSEL2 line), and its output end is coupled to the secondary BIOS ROM (second circuit block).)
Wherein when the error detection circuit enters the security mode, the second end of the first logic gate receives a preservation signal outputted by the error detection circuit, and the output end of the first logic gate outputs the security access signal of the first state (Noll: Col. 5 Lines 29-54 Provides for when the error detection circuit detects and error (enters security mode), it causes the ROMSEL2 line to go low, which through the inverter 48 sends a high signal (preservation signal) to the gate 50.)
In reference to claim 6, A firmware switching method for maintaining system security for protecting an electronic device, comprising: arranging a security protection circuit between a central processing unit and a security circuit block, wherein when a security access signal outputted by the CPU is detected to be in a second state, the security circuit block is allowed to be accessed (Noll: Fig. 1 Col. 3 Lines 5-40 Provides for a computer (electronic device) with storage devices (primary BIOS ROM 22 and secondary BIOS ROM 30) that store multiple firmware (BIOS) programs.) Noll: Col. 2 Lines 49-62 and Col. 3 Lines 54-65 Provides for a CPU coupled to the storage devices.) Noll: Fig. 1 Col. 3 Lines 5-40 Provides for the BIOS ROM 22 and its associated circuitry (AND gate 44) (first circuit block) that is coupled to the CPU.) Noll: Col. 3 Lines 5-54 and Col. 5 Lines 29-45 Provides for the secondary BIOS ROM 30 and its associated circuity (inverter 48 and AND gate 50) (second circuit block), when the ROMSEL2 control line is in a low state (second state of the security access signal), the secondary BIOS ROM is enabled and can be accessed by the CPU.)
when the security access signal is in a first state, the first circuit block is allowed to be accessed by the CPU and the second circuit block is forbidden to be accessed by the CPU (Noll: Col. 3 Lines 5-54 and Col. 5 Lines 29-45 Provides for the secondary BIOS ROM 30 and its associated circuity (inverter 48 and AND gate 50) (second circuit block), when the ROMSEL2 control line is in a low state (second state of the security access signal), the secondary BIOS ROM is enabled and can be accessed by the CPU. Noll Col. 3 lines 20 - 55 Provides for normal state has primary BIOS enabled and secondary BIOS disabled, directly teaching the first circuit block accessible and second circuit block forbidden.)
a security protection circuit coupled between the CPU and the second circuit block, wherein: when the electronic device updates the plurality of firmware, a first firmware of the storage device is refreshed, and a second firmware is preserved (Noll: Col. 6 Line 5 – Col. 7 Line 51 Provides for reprogramming (refreshing) the primary BIOS ROM while preserving the secondary BIOS ROM during a firmware update process.)
after the firmware of the electronic device is updated, the updated first firmware is operated (Noll: Col. 7 Lines 30-51 Provides that after reprogramming the primary BIOS ROM, the system would continue to operate using the reprogrammed primary BIOS on subsequent boots.)
when the updated first firmware is unable to be operated, the first firmware is switched to the second firmware, and the security protection circuit is activated to enter a security mode (Noll: Col. 5 Lines 29-45 Provides for switching from the primary BIOS to the secondary BIOS when the primary BIOS has errors and cannot operate properly.)
when the security protection circuit is activated, the security access signal received by the second circuit block is set to the first state (Noll: Col. 5 Lines 29-45 Provides for when the chip enable circuit (security protection circuit) is activated due to errors in the primary BIOS, it sets the ROMSEL2 control line to a low logic level (first state of the security access signal). This signal, after going through the inverter, enables the secondary BIOS ROM.)
Noll does not explicitly teach when the security access signal is in a second state both the first circuit block and the second circuit block are allowed to be accessed by the CPU and receiving a firmware update message through over the air (OTA) when the security access signal is in a second state both the first circuit block and the second circuit block are allowed to be accessed by the CPU (Marr: [0068]-[0074] Provides for different access states during boot/mutability period both blocks could be accessible, but later access is restricted.) receiving a firmware update message through over the air (OTA) (Marr: [0051]-[0055] and [0082] Provides for firmware updates over networks.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Noll, which provides an electronic device with multiple firmware storage blocks and security protection circuits that enable firmware switching and preservation during updates, with the teachings of Marr, which introduces a state where both firmware blocks can be simultaneously accessible and over-the-air (OTA) firmware update capabilities. One of ordinary skill in the art would recognize the ability to incorporate Marr's dual-access state and OTA update mechanism into Noll's firmware protection system to enhance flexibility and modernize the update process. One of ordinary skill in the art would be motivated to make this modification in order to enable more efficient firmware update operations by allowing temporary simultaneous access to both firmware blocks during the update process and to provide modern wireless update capabilities.
In reference to claim 7, The firmware switching method for maintaining system security according to claim 6, wherein the security protection circuit comprises: an error detection circuit for detecting an operation error, to determine whether to enter the security mode (Noll: Col. 3 Lines 65 – Col. 4 Line 24 Provides for an error detection circuit that detects operation errors in the primary BIOS ROM.)
a first logic gate including a first end, a second end and an output end, wherein the first end of the first logic gate receives the security access signal outputted by the CPU, the second end of the first logic gate is coupled to the error detection circuit, and the output end of the first logic gate is coupled to the security circuit block (Noll: Col. 3 Line 29 – Line 54 Provides for gate 50 (first logic gate) ites first end received the ROMSEL1 control line signal (security access signal), its second end is connected to circuitry that is influenced by the error detection circuit (via the inverter 48 and ROMSEL2 line), and its output end is coupled to the secondary BIOS ROM (second circuit block).)
wherein when the error detection circuit enters the security mode, the second end of the first logic gate receives a preservation signal outputted by the error detection circuit, and the output end of the first logic gate outputs the security access signal of the first state (Noll: Col. 5 Lines 29-54 Provides for when the error detection circuit detects and error (enters security mode), it causes the ROMSEL2 line to go low, which through the inverter 48 sends a high signal (preservation signal) to the gate 50.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Noll et al. (US 6185696 B1, referred to as Noll), in view of Marr et al. (US 20160019050 A1, referred to as Marr) in further view of Critelli et al. (US 20190354726 A1, referred to as Critellil).
In reference to claim 3, The electronic device according to claim 2, wherein the first logic gate is an OR gate, and the preservation signal outputted by the error detection circuit is a logic-high voltage (Critelli: [0100]-[0101] Provides for OR gates 1112 that combine security-related signals. The OR gate implementation ensures that once a bit is set to logic-high (corresponding to a security/lock condition), it maintains that state regardless of other input changes.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Noll, which provides an electronic device with security protection circuits including error detection and logic gates for firmware protection and switching, with the teachings of Critelli, which introduces OR gate implementations for security related signal processing with logic high preservation signals. One of ordinary skill in the art would recognize the ability to incorporate Critelli’s OR gate configuration into Noll’s security protections system to enhance the reliability of security signal processing. One of ordinary skill in the art would be motivated to make this modification in order to ensure that security conditions are maintained once activated regardless of other input changes.
In reference to claim 4, The electronic device according to claim 2, wherein the first logic gate is a multiplexer, and the second end and a selection control end of the multiplexer receive the preservation signal outputted by the error detection circuit, and when the preservation signal outputted by the error detection circuit is a logic-high voltage, the output end of the multiplexer outputs a logic-high voltage (Critelli: [0119]-[0120] and [0128]-[0130] Provides for multiplexers used for signal selection based on control signals (register selection signals WR_REG0 … WR_REGn), and a switch SW controlled by the FSM 1128 that selectively routes signals.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Noll, which provides an electronic device with security protection circuits including error detection and logic gates for firmware protection and switching, with the teachings of Critelli, which introduces multiplexer implementations for signal selection and routing based on control signals. One of ordinary skill in the art would recognize the ability to incorporate Critelli’s multiplexer configuration into Noll’s security protections system to enhance the reliability of security signal processing. One of ordinary skill in the art would be motivated to make this modification in order to enable flexible signal management by allowing the preservation signal to control both selection and output of the multiplexer.
In reference to claim 5, The electronic device according to claim 1, wherein the second circuit block is an attack detection circuit, and when the security mode is entered, the CPU is unable to turn off the attack detection circuit (Critelli: [0113]-[0114] and [0135] Provides for a tamper detection circuit that functions as a attack detection mechanism, and the monitoring circuit 1116/FSM 1128 that detects brute force attacks through incorrect configuration attempts.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Noll, which provides an electronic device with security protection circuits including error detection and logic gates for firmware protection and switching, with the teachings of Critelli, which introduces tamper detection circuits and attack monitoring mechanisms that cannot be disabled once activated.. One of ordinary skill in the art would recognize the ability to incorporate Critelli’s attack detection functionality into Noll’s security protections system to enhance the reliability of firmware protection system. One of ordinary skill in the art would be motivated to make this modification in order to provide active security monitoring that can detect malicious attacks on the firmware system.
In reference to claim 8, The firmware switching method for maintaining system security according to claim 7, wherein the first logic gate is an OR gate, and the preservation signal outputted by the error detection circuit is a logic-high voltage (Critelli: [0100]-[0101] Provides for OR gates 1112 that combine security-related signals. The OR gate implementation ensures that once a bit is set to logic-high (corresponding to a security/lock condition), it maintains that state regardless of other input changes.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Noll, which provides an electronic device with security protection circuits including error detection and logic gates for firmware protection and switching, with the teachings of Critelli, which introduces OR gate implementations for security related signal processing with logic high preservation signals. One of ordinary skill in the art would recognize the ability to incorporate Critelli’s OR gate configuration into Noll’s security protections system to enhance the reliability of security signal processing. One of ordinary skill in the art would be motivated to make this modification in order to ensure that security conditions are maintained once activated regardless of other input changes.
In reference to claim 9, The firmware switching method for maintaining system security according to claim 7, wherein the first logic gate is a multiplexer; and the second end and the selection control end of the multiplexer receive the preservation signal outputted by the error detection circuit, and when the preservation signal outputted by the error detection circuit is a logic-high voltage, the output end of the multiplexer outputs a logic-high voltage (Critelli: [0119]-[0120] and [0128]-[0130] Provides for multiplexers used for signal selection based on control signals (register selection signals WR_REG0 … WR_REGn), and a switch SW controlled by the FSM 1128 that selectively routes signals.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Noll, which provides an electronic device with security protection circuits including error detection and logic gates for firmware protection and switching, with the teachings of Critelli, which introduces multiplexer implementations for signal selection and routing based on control signals. One of ordinary skill in the art would recognize the ability to incorporate Critelli’s multiplexer configuration into Noll’s security protections system to enhance the reliability of security signal processing. One of ordinary skill in the art would be motivated to make this modification in order to enable flexible signal management by allowing the preservation signal to control both selection and output of the multiplexer.
In reference to claim 10, The firmware switching method for maintaining system security according to claim 6, wherein the security circuit block is an attack detection circuit, and when the security mode is entered, the CPU cannot turn off the attack detection circuit (Critelli: [0113]-[0114] and [0135] Provides for a tamper detection circuit that functions as a attack detection mechanism, and the monitoring circuit 1116/FSM 1128 that detects brute force attacks through incorrect configuration attempts.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Noll, which provides an electronic device with security protection circuits including error detection and logic gates for firmware protection and switching, with the teachings of Critelli, which introduces tamper detection circuits and attack monitoring mechanisms that cannot be disabled once activated.. One of ordinary skill in the art would recognize the ability to incorporate Critelli’s attack detection functionality into Noll’s security protections system to enhance the reliability of firmware protection system. One of ordinary skill in the art would be motivated to make this modification in order to provide active security monitoring that can detect malicious attacks on the firmware system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Applicant’s amendment necessitated the new ground(s) of rejection presented in this office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E.S./Examiner, Art Unit 2432
/Jeffrey Nickerson/Supervisory Patent Examiner, Art Unit 2432