DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 2020/0235246) in view of Song (US 2020/0227519) further in view of Velliantis (US 2022/0336675) and further in view of Yang (US 2005/0099551).
[claim 1] Sharma discloses a method for manufacturing a transparent thin film transistor (fig. 3A-3F), comprising: preparing a semiconductor substrate (310, fig. 3A, [0025]) unit including a gate electrode layer; forming a gate insulator layer (320,fig. 3A, [0025]) by depositing a high dielectric constant material [0028] using atomic layer deposition [0025] to cover the gate electrode layer; forming a channel layer (330, fig. 3B, [0033]) made of an indium oxide-based material (IZO, [0033]) on the gate insulator layer in a position corresponding to the gate electrode layer by sputtering [0031],; and forming a source electrode (350, fig. 3F) and a drain electrode (350, fig. 3F) on two opposite end portions of the sensing channel layer, respectively. Sharma, however, does not expressly disclose that that the IZO channel layer is nitrogen doped, that the ALD process is plasma enhanced, that the channel layer is a photosensitive channel layer, or that the gate insulator layer acts as a protective layer to the sides of the gate electrode (e.g. fig. 8 shows a separate ILD bordering the side of the gate electrode) .
Song discloses a method of making a TFT device [0049] wherein the IZO channel layer (114, fig. 4, [0085]) is in-situ nitrogen doped during formation of the channel layer or by nitrogen implantation [0087].
It would have been obvious to one of ordinary skill in the art before the time of filing to have made Sharma’s IZO channel layer nitrogen doped in order to enhance performance and reliability of the TFT by reducing defect density, threshold voltage control, and improve thermal stability.
Velliantis discloses a method of making a TFT device (title) wherein the ALD process to make the gate dielectric layer is plasma enhanced [0034].
It would have been obvious to one of ordinary skill in the art before the time of filing to have made Sharma’s ALD gate dielectric layer use a plasma enhanced ALD process nitrogen doped in order to enhance performance and reliability of the TFT by reducing defect density, threshold voltage control, and improve thermal stability.
Yang discloses a method of making a TFT device (title) wherein the gate insulator (120, fig. 5A, [0046]) acts as protective layer to the sides of the gate electrode (110, fig. 5A, [0046]).
It would have been obvious to one of ordinary skill in the art before the time of filing to used Yang’s TFT configuration in Sharma’s TFT device in order to provide for a means to protect the sides of the gate electrode without the need for further deposition of insulation layers/ ILDS to protect the gate).
With this modification Sharma discloses:
[claim 1] a photosensitive device with a sensing channel layer (since the materials of the device are the same the device and channel layer are capable of being used as a photosensor), wherein the gate insulator layer is formed to include a first gate insulator portion (portion of 120 above gate electrode 110, fig. 5A, of Yang) which laterally covers the gate electrode layer and a second gate insulator portion (portion of 120 to the sides of gate electrode 110, fig. 5A, of Yang) which is disposed on the first gate insulator portion and in a position corresponding to the gate electrode layer.
[claim 2] The method as claimed in claim 1, wherein the sensing channel layer is doped with nitrogen by in-situ introduction of nitrogen when the sensing channel layer is formed (see [0087] of Song).
[claim 3] The method as claimed in claim 1, wherein the sensing channel layer is doped with nitrogen by subjecting the sensing channel layer to nitrogen annealing after being formed (ion implanting the nitrogen causes heat in the sensing channel which anneals the channel when nitrogen is present).
[claim 4] The method as claimed in claim 1, wherein the gate insulator layer includes hafnium dioxide [0028], aluminum oxide [0028], zirconium dioxide, hafnium zirconium oxide, titanium dioxide, tantalum pentoxide, or combinations thereof.
[claim 5] The method as claimed in claim 1, wherein the sensing channel layer includes amorphous indium oxide [0032], amorphous indium zinc oxide, amorphous indium tungsten oxide, amorphous indium tungsten zinc oxide, amorphous indium tin oxide, amorphous indium tin zinc oxide, or combinations thereof.
[claim 6] The method as claimed in claim 1, wherein the gate insulator layer includes hafnium dioxide [0028].
[claim 10] The method as claimed in claim 1, wherein the semiconductor substrate unit further includes a substrate and a buffer layer disposed on the substrate, the gate electrode layer being disposed on the buffer layer.
[claim 11] The method as claimed in claim 1, wherein the sensing channel layer is formed to include: a first sensing channel portion which is disposed on the first gate insulator portion and which laterally covers the second gate insulator portion (upon modification, e.g. the channel layer in Yang is 130); and a second sensing channel portion which is disposed on the first sensing channel portion and in a position corresponding to the gate electrode layer (upon modification, e.g. the channel layer in Yang is 130).
[claim 12] The method as claimed in claim 11, wherein the source electrode is formed to include: a first source portion (e.g. lower left half of 170a, fig. 5a, Yang) which is disposed on the (lateral side) of the first gate insulator portion and which laterally covers the first sensing channel portion (Yang, fig. 5A); a second source portion (lower right half of 170a, fig. 5a, Yang) which is disposed on (the side of) the first source portion and which laterally covers the second sensing channel portion (fig. 5A); and a third source portion (upper portion of 170A, fig. 5A) which is disposed on the second source portion.
[claim 13] The method as claimed in claim 12, wherein the drain electrode is formed to include: a first drain portion (e.g. lower left half of 170b, fig. 5a, Yang) which is disposed on the (lateral) first gate insulator portion and which laterally covers the first sensing channel portion; a second drain portion (e.g. lower right half of 170a, fig. 5a, Yang) which is disposed on the first drain portion and which laterally covers the second sensing channel portion; and a third drain portion (upper portion of 170b, fig. 5a, Yang) which is disposed on the second drain portion and which is spaced apart from the third source portion.
[claim 14] The method as claimed in claim 13, wherein the semiconductor substrate unit further includes a substrate (layer on which gate 310 is deposited on, fig. 3F, see also for example fig. 8, ILD 342 is a substrate) on which the gate electrode layer is disposed, and a projection of one of the source electrode and the drain electrode (projection of 350 extending downwards, fig. 3F) on the substrate partially overlaps a projection of the gate electrode layer (310 extends upward from the underlying layer, fig. 3F) on the substrate .
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 2020/0235246) in view of Song (US 2020/0227519) further in view of Velliantis (US 2022/0336675) and further in view of Kimura (US 2006/0232601).
Sharma/Song/Velliantis discloses the TFT method of claim 6 but does not expressly disclose that the channel is formed by indium zinc oxide target through sputtering, the indium zinc oxide target having a ratio of In2O3 to ZnO of 9:1.
Kimura discloses a method of making a TFT device wherein the channel is formed by indium zinc oxide target through sputtering [0314], the indium zinc oxide target having a ratio of In2O3 to ZnO of 9:1 ([0314], wherein sputtering ITO and ZnO mixture to form IZO is such that ZnO is 2 to 20 percent weight which equates to a 9:1 ratio).
It would have been obvious to one of ordinary skill in the art to have used Kimura target sputtering method in the claimed ratio of 9:1 InO:ZnO in order to provide a means to manufacture the IZO layer.
Separately it would have been obvious to one of ordinary skill before the time of filing to have made the indium zinc oxide target ratio of InO to ZnO 9:1 since it has been held that where the general conditions of a claim are disclosed in prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It also been held that the normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages. In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003). The claimed range is a result-effective variable since the InO to ZnO ratio affects the electrical conductivity, optical transparency, and band gap of the IZO layer.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 2020/0235246) in view of Song (US 2020/0227519) further in view of Velliantis (US 2022/0336675).
Sharma/Song/Velliantis discloses the TFT method of claim 1 but does not expressly disclose that channel layer has a thickness ranging from 2 nm to 10 nm.
Nevertheless it would have been obvious to one of ordinary skill before the time of filing to have made the channel layer thickness of 2 to 10 nm since it has been held that where the general conditions of a claim are disclosed in prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It also been held that the normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages. In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003). The claimed range is a result-effective variable since the thickness of the channel is affects the amount current in the channel region as well as the amount of space the device takes up.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 2020/0235246) in view of Song (US 2020/0227519) further in view of Velliantis (US 2022/0336675) and further in view of Wei (“Supercritical Dieletric Fluids for High Power Density Applications”).
Sharma/Song/Velliantis discloses the TFT method of claim 1 but does not expressly disclose that channel layer oxide and dielectric constant material of the gate insulator is subjected to supercritical carbon fluid to enhance dielectric properties.
Wei discloses a means to enhance dielectric properties by using supercritical carbon dioxide since it has high dielectric strength, is non-toxic, and has low global warming temperature (page 41).
It would have been obvious to one of ordinary skill in the art before the time of filing to have made the channel layer oxide and dielectric constant material of the gate insulator subjected to supercritical carbon fluid to enhance dielectric properties in order to ensure dielectric proprieties with high dielectric strength, is non-toxic, and has low global warming temperature (page 41).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any interpretation applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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