Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 01/08/2024. These drawings are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 16 are rejected 35 U.S.C. 103 as being unpatentable over Choudhary et al. (USPGPUB No. 2020/0327084 A1, hereinafter referred as Choudhary) in view of Pappachan et al. (USPGPUB No. 2024/0104226 A1, hereinafter referred to as Pappachan) and further in view of Raman et al. (USPGPUB No. 2022/0091754 A1, hereinafter referred to as Raman).
Referring to claim 1, Choudhary discloses a method for processing packets {interconnects that facilitate packet processing “interfaces with a Flex Bus physical layer (e.g., 430a-b). Flex Bus may be implemented as a flexible high-speed port that is statically configured to support either PCIe or CXL”, see Fig. 4 [0045]} for distribution over a host bus {“ interconnects have grown from more traditional multi-drop buses”, see Fig. [0005]}, comprising:
receiving, from an interconnect, a packet {“recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance”, see Fig. 4 [0029], last sentence} comprising a header {“ header signal (HDR) size is variable and is based on the protocol that is being transported over the UFI interface. When multiple protocols are carried over the UFI interface, the HDR width is sized for the maximum size of the HDR being transported over the interface, or to the largest headers size of the multiple supported protocols” including PCIe, see Fig. 4 [0052]} and a data field {“convert Load/Store protocols like PCIe to unordered [DATA FIELD] protocols like IDI/UPI while maintaining the system requirements that allow producer/consumer work flows to function”, see Fig. 2, [0036], last two sentences}
determining that the packet matches a packet format {“FLOW CONTROL” which “identifies [matches] between protocol [packet format]” such as UFI, PCIe, CXL, see Table 6, after [0051]} of a context {context within “UFI REQ layer carries [context] requests from agent-to-fabric and fabric to agent”, see Figs. 2 and 4 [0051], 1st sentence} by comparing a first subset of bits of the header to a format match value {the same Table 6 signal class “FLOW CONTROL” having example first subset of bits “4 bits” width for Upstream/Downstream port over CXL.mem, CXL.cache and so on to name a few.};
determining a context index value {“architecture [context index value] states/contexts are capable of being stored for logical processor 1501a and logical processor 1501b”, see Fig. 15 [0106]} based on a second subset of bits extracted from the header {“packet (and its corresponding data and [second subset of bits] header flits`)”, see Fig. 6, [0069], 1st sentence};
Choudhary does not appear to explicitly disclose receiving, from an interconnect, a packet comprising a header and a data field, the packet associated with a virtual function;
obtaining a context base value and a context range value from a lookup table based on an identifier of the virtual function;
generating a context identifier using the context index value, the context base value, and the context range value;
associating the context identifier with the packet;
and sending the packet with the context identifier over the host bus for distribution to resources of the context.
However, Pappachan discloses receiving, from an interconnect, a packet comprising a header {“header of the PCI Express TLP”, see Fig. 3a, [0042], last sentence} and a data field {data field consisting “local memory access request from a host 300” in other words “originated the access request 302” ([0042], see Fig. 3a}, the packet associated with a virtual function {“determination regarding whether the PF or VF that originated the access [and corresponding TLP]”, see Figs. 2 and 3B, [0045]};
obtaining a context base value {“each protection domain”, see Fig. 2, [0038]} and a context range value {“[context range value] correct key ID selection … accessible by the device memory management unit (MMU)”, see Fig. 2 [0040]} from a lookup table {“ stored in a [lookup] table that is accessible by the device memory management unit (MMU)”, see Fig. 2 [0040]} based on an identifier of the virtual function {“[identifier] based on the respective VF# from the key ID selector table 362”, see Fig. 3B [0046]};
generating a context identifier {“encryption engine (MKTME) selects a [context identifier] key”, see Fig. 3a [0043], last sentence} using the context index value {“using the key ID received” as claimed, see Fig. 3a [0043], last sentence}, the context base value {“ physical address is in the VF LMEM (Local Memory) [context] BAR (Base Address Registers) region”, see Fig. 1 [0032], 2nd and 3rd sentences}, and the context range value {“[context range] Each physical page in local memory that is allocated to a VF assigned to a TD has an entry in the GMPT. Each entry in the GMPT records a VF#”, see Fig. 1 [0023], last two sentences};
associating the context identifier {associating “The Key ID assignments”, [0041]} with the packet {“ accesses originating from a TD, is a bit in the header of the PCI Express TLP Translation Layer Packet”, see Fig. 3a [0042], last sentence};
Choudhary and Pappuchan are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Choudhary and Pappuchan before him or her, to modify Choudhary’s “UFI REQ layer carries requests from agent-to-fabric and fabric to agent” and appropriate circuitry/hardware (see Figs. 2 and 4) incorporating Pappuchan’s “GPU 230”’s “encryption engine supporting multiple keys for encryption 244” (MKTME, see Fig. 2, [0038]).
The suggestion/motivation for doing so would have been to implement secure acceleration of workloads that are offloaded from host TEEs to the virtualized GPU, it is essential to protect compute kernels and data that is within the local memory of the GPU (Pappuchan [0004]).
Therefore, it would have been obvious to combine Pappuchan with Choudhary to obtain the invention as specified in the instant claim(s).
Neither Chodhary or Pappuchan appears to explicitly disclose sending the packet with the context identifier over the host bus for distribution to resources of the context
Furthermore, Raman discloses sending the packet {“ Control traffic (e.g., in the form of packets)”, see Fig. 1 [0042]} with the context identifier {“ packets with certain contexts (e.g. specific fabric PDUs, transactions with a specific NAS, etc.)… the network traffic flows and storage transactions”, see Fig. 8 [0096], 4th sentence} over the host bus for distribution to resources of the context {over the bus “NVMe interface policies 806 can select which” to resources “NAS appliances VF’s attach to, maintain lists of NAS appliances”, see Fig. 8, [0095] last sentence}.
Choudhary/Pappuchan and Raman are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Choudhary/Pappuchan and Raman before him or her, to modify Choudhary/Pappuchan’s system incorporating “NAS appliances” performing “interface policies 806” (see Fig. 8).
The suggestion/motivation for doing so would have been to perform dynamic scaling of the numbers of hosts and VMs running a workload which further involve behind all those hosts and VMs (the compute elements), the storage namespaces are provided by mirrored NAS appliances (the storage elements), thereby increasing the aggregate storage bandwidth between the compute elements and the storage elements (Raman [0002] paraphrased).
Therefore, it would have been obvious to combine Raman with Choudhary/Pappuchan to obtain the invention as specified in the instant claim(s).
Referring to claim 16 is a system claim reciting claim functional language corresponding to computer readable to the device claim of claim 1, thereby rejected under the same rationale as claim 1 recited above.
Claims 2, 3, 4, and 10 are rejected 35 U.S.C. 103 as being unpatentable over Choudhary in view of Pappachan and further in view of Raman and further in view of Regula (USPGPUB No. 2012/0166690).
As per claim 2, the rejection of claim 1 is incorporated however neither one of the group consisting of Choudhary, Pappuchan, and Raman appears to explicitly disclose any limitation in this dependent claim.
Additionally, Regula discloses the context identifier for the packet is generated by applying a modular arithmetic function {applying “Modulo 2.sup.16.”, see Fig. 5, [0084], 1st sentence} to the context index value {“[context index value] PF Routing ID…”, see Fig. 5 [0084], 1st sentence}, the context base value {“use contiguous segments of VF BARs”, see Fig. 5 [0084], 1st sentence}, and the context range value {“[context range] VF Stride”, see Fig. 5 [0084], last sentence}; and the lookup table does not include discrete context identifier values {“ If the Stride is greater than 1, we require that the same value of Stride be used in both domains” thereby lacking discrete context identifier values as claimed, see Fig. 5 [0086], last sentence}.
Choudhary/Pappuchan/Raman and Regula are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Choudhary/Pappuchan/Raman and Regula before him or her, to modify Choudhary/Pappuchan/Raman’s system incorporating Regula’s “virtual hierarchy” and “upstream route table” ([0078], [0053], see Fig. 5).
The suggestion/motivation for doing so would have been to implement a solution that allows the multi-root sharing of endpoint functions using the existing SR-IOV standard that is in use by a large number of devices, thus having the advantages of MR-IOV without needing to actually implement MR-IOV ([0016]).
Therefore, it would have been obvious to combine Regula with Choudhary/Pappuchan/Raman to obtain the invention as specified in the instant claim(s).
As per claim 3, the rejection of claim 1 is incorporated however the combination of references Choudhary, Pappachan, and Raman does not appear to disclose any limitation in this dependent claim.
Furthermore, Regula discloses wherein: the lookup table comprises multiple pairs of context base values and context range values {such virtual functions map to a lookup table includes context base “use contiguous segments of VF BARs” (see Fig. 5 [0084], 1st sentence) and range values “VF Stride” (see Fig. 5 [0084], last sentence)} associated with the virtual function {“identify dependent pairs of VFs”, see Fig. [0087], last sentence};
the context base value and the context range value are a first pair of context base values {“[context base values] BARs of virtual functions assigned to any particular host, segments of its virtual physical function's VF BARs, fit within the virtualized downstream port of its host's virtual switch”, see Fig. 4 [0070]} and context range values associated with the virtual function {“Each host still gets its share of VFs in blocks of at least Stride in size”, see Fig. 5 [0088]};
the determination that the packet matches the packet format of the context {“ the [packet format] redirection criterion defined above”, see Fig. [0056], 2nd sentence} is performed by a first instance {“switch’s ingress pipeline”, see Fig. [0078]} of multiple instances {at least two instances “pipeline”, a first instance “ingress pipeline” and second instance “downstream port of a virtual switch” or colloquially “egress” pipeline, see Fig. [0083], 2nd sentence} of packet match logic {“[packet match logic] virtual switch hierarchy created via CSR redirection”, see Fig. [0083], 1st sentence};
and the method further comprises selecting the first pair of context base values and context range values {such virtual functions map to a lookup table includes context base “use contiguous segments of VF BARs” (see Fig. 5 [0084], 1st sentence) and range values “VF Stride” (see Fig. 5 [0084], last sentence)} based on the match being determined by the first instance of packet match logic {“using the [the match being determined] address in the redirection pointer register and appends the TLP to it as its payload” by the packet match logic “virtual switch”, see Fig. [0056], 3rd sentence}.
The 103 motivation for this dependent claim is relied upon as recited in claim 2.
As per claim 4, the rejection of claim 1 is incorporated however the combination of references Choudhary, Pappachan, and Raman does not appear to disclose any limitation in this dependent claim.
Furthermore, Regula discloses further comprising:
extracting the first subset of bits {the same Table 6 signal class “FLOW CONTROL” having example first subset of bits “4 bits” width for Upstream/Downstream port over CXL.mem, CXL.cache and so on to name a few.} from the header of the packet {“by [extracting] supporting the MR prefix”, [0047]} based on a first offset value {“[first offset value] Local to Global Requester ID Offset… the requisite address (VF BAR mapping) and requester ID translations can be performed and then the packet can be forwarded to the associated downstream port”, see Fig. 4 [0066], last sentence};
or extracting the second subset of bits from the header of the packet based on a second offset value {Examiner’s note: recitation “or extracting the second subset”, said “or” renders this dependent claim as a Markush claim, thus the references needs only disclose one group member to address the claim.}.
The 103 motivation for this dependent claim is relied upon as recited in claim 2.
As per claim 10, the rejection of claim 1 is incorporated however the combination of references Choudhary, Pappachan, and Raman does not appear to disclose any limitation in this dependent claim.
Furthermore, Regula discloses wherein the header of the packet is formatted in compliance with a protocol {Examiner’s note: recitation “or extracting the second subset”, said “or” renders this dependent claim as a Markush claim, thus the references needs only disclose one group member to address the claim.} that includes one of Fibre Channel, Ethernet {“single root function such as a single Ethernet port”, see Fig. 1 [0010]}, peripheral component interconnect express (PCI Express) {“PCIe TLP”, see Fig. 1 [0042], 1ST sentence}, compute express link (CXL), InfiniBand, or a custom protocol {“These [packet] policies or templates can be customized for use in individual implementations to provide the most efficient distribution of resources”, [0050]}.
The 103 motivation for this dependent claim is relied upon as recited in claim 2.
Claim 11 is rejected 35 U.S.C. 103 as being unpatentable over Choudhary in view of Regula and further in view of Dalal).
Referring to claim 11, Choudhary discloses an integrated circuit comprising {interconnects that facilitate packet processing “interfaces with a Flex Bus physical layer (e.g., 430a-b). Flex Bus may be implemented as a flexible high-speed port that is statically configured to support either PCIe or CXL”, see Fig. 4 [0045]}:
packet match logic comprising {packet match logic performing “FLOW CONTROL” which “identifies [matches] between protocol [packet format]” such as UFI, PCIe, CXL, see Table 6, after [0051]}:
a register configured to receive {“recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology [and respective register(s), and packetized protocol to deliver new levels of performance”, see Fig. 4 [0029], last sentence} a header of a packet {“ header signal (HDR) size is variable and is based on the protocol that is being transported over the UFI interface. When multiple protocols are carried over the UFI interface, the HDR width is sized for the maximum size of the HDR being transported over the interface, or to the largest headers size of the multiple supported protocols” including PCIe, see Fig. 4 [0052]};
Choudhary does not appear to explicitly disclose a first configurable register to store a first offset value by which a first subset of bits is extracted from the header of the packet;
a second configurable register to store a match value;
a comparator configured to generate a match indicator in response to the first subset of bits extracted from the header matching the match value;
and a circuit configured to:
obtain, based on a virtual function identifier associated with the packet and from a lookup table, the respective pair of the base context value and the context range value that corresponds to the virtual function of the packet;
and generate a context identifier for the packet based on the context index value, the base context value, and the context range value;
Furthermore, Regula discloses the packet match logic comprising: a first configurable register to store a first offset value {“[first offset value] Local to Global Requester ID Offset… the requisite address (VF BAR mapping) and requester ID translations can be performed and then the packet can be forwarded to the associated downstream port”, see Fig. 4 [0066], last sentence} by which a first subset of bits is extracted {the same Table 6 signal class “FLOW CONTROL” having example first subset of bits “4 bits” width for Upstream/Downstream port over CXL.mem, CXL.cache and so on to name a few.} from the header of the packet {“by [extracting] supporting the MR prefix” from a packet header as claimed, [0047]};
a second configurable register to store a match value {“ the [packet format] redirection criterion defined above”, see Fig. [0056], 2nd sentence};
a comparator configured to generate a match indicator {match indicators “use contiguous segments of VF BARs” (see Fig. 5 [0084], 1st sentence) and range values “VF Stride” (see Fig. 5 [0084], last sentence)} in response to the first subset of bits extracted from the header matching the match value {“requester ID translations can be performed and then the [header] packet can be [matched and] forwarded to the associated downstream port”, see Fig. 4 [0066], last sentence};
and a circuit configured to:
obtain, based on a virtual function identifier {“Each host still gets its share of [virtual functions] VFs in blocks of at least Stride in size”, see Fig. 5 [0088]} associated with the packet {“ the [packet format] redirection”, see Fig. [0056], 2nd sentence} and from a lookup table {such virtual functions map to a lookup table includes context base “use contiguous segments of VF BARs” (see Fig. 5 [0084], 1st sentence), the respective pair of the base context value and the context range value that corresponds to the virtual function of the packet {pair of context base “use contiguous segments of VF BARs” (see Fig. 5 [0084], 1st sentence) and range values “VF Stride” (see Fig. 5 [0084], last sentence)};
Choudhary and Regula are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Choudhary and Regula before him or her, to modify Choudhary’s “UFI REQ layer carries requests from agent-to-fabric and fabric to agent” and appropriate circuitry/hardware (see Figs. 2 and 4) incorporating Regula’s “virtual hierarchy” and “upstream route table” ([0078], [0053], see Fig. 5).
The suggestion/motivation for doing so would have been to implement a solution that allows the multi-root sharing of endpoint functions using the existing SR-IOV standard that is in use by a large number of devices, thus having the advantages of MR-IOV without needing to actually implement MR-IOV ([0016]).
Therefore, it would have been obvious to combine Regula with Choudhary to obtain the invention as specified in the instant claim(s).
Neither Choudhary or Regula appears to explicitly disclose wherein the circuit is a modular arithmetic circuit configured to:
a third configurable register to store a second offset value by which a second subset of bits are extracted from the header of the packet;
and index generation logic configured to generate a context index value based on the second subset of bits of the header of the packet;
and context generation logic comprising:
an encoder with inputs operably coupled with an output of the comparator of the packet match logic and an output of at least one other instance of packet match logic;
a multiplexor having an input coupled to an output of the index generation logic and configured to select the index value based on an output of the encoder;
a context table configured to store, in association with virtual functions, respective pairs of base context values and context range values;
and generate a context identifier for the packet based on the context index value, the base context value, and the context range value;
Furthermore, Dalal discloses wherein the circuit is a modular arithmetic circuit configured to {“data structure may be… a ring structure 5902a or [modulo/modular arithmetic] hash table”, [0281]; other examples “on the index they hash to in the physically indexed cache”, [0444]}:
a third configurable register to store a second offset value {“such [offset value] metadata” with a respective register, [0265]} by which a second subset of bits are extracted from the header of the packet {“From extracted [a subset of bits] metadata, scheduler 6216 can create a processing schedule”, see Fig. 62-0 [0339]};
and index generation logic configured to generate a context index value {“The entire cache context [and respective context index value] is saved beginning at the session boundary”, see Fig. [0459]} based on the second subset of bits of the header of the packet {“From extracted [a subset of bits] metadata, scheduler 6216 6216 can create a processing schedule”, see Fig. 62-0 [0339]};
and context generation logic comprising {“[Context] Sessions can be prioritized and queued by an [generation logic] arbiter circuit at step 7706 ”, see Fig. 77 [0392], 3rd and 4th sentences}:
an encoder with inputs operably coupled {encoder “the [VF] driver employs a means to mask”, see Fig. 79, [0403], last three sentences} with an output of the comparator of the packet match logic and an output of at least one other instance of packet match logic {“ global space at which the physical instances of the registers [and packet match logic] are located”, see Fig. 8 [0098]};
a multiplexor having an input coupled {“Simple passive optical mux/demux-ing can separate high bandwidth ports” having coupling as claimed, see Fig. 6, [0117], last sentence} to an output of the index generation logic {“processor cache is physically indexed” (see Fig. 84a [0441]) via multiplexor} and configured to select the index value based on an output of the encoder {“physical representation of the [index value] fields encoded into any protocol from the program ”, see Fig. 51 [0206]};
a context table configured to store {“allocator for session [table] heap and stack”, see Fig. 59-0 [0306]}, in association with virtual functions {“descriptor queue (7908) of the [associated] VF 7904”, see Fig. 79 [0402]}, respective pairs of base context values {“base index of the session.”, see Fig. 59a [0459]} and context range values {“[range values] Pages of a [context] session are accessible by”, see Fig. 59-0 [0459]};
and generate a context identifier {“packets pertaining to a [context identifier] session directly into a buffer”, see Fig. 85 [0454]} for the packet based on the context index value {packets pertaining to a [context identifier] session directly into a buffer”, see Fig. 85 [0454]; the register contents are loaded by the kernel upon resuming the thread, [0456]}, the base context value {“[base context] extend the coherency domain of sessions”, see Fig. 59-0 [0455]}, and the context range value {“multiple address translations would be required to access multiple [range values] pages of the same [context] session”, see Fig. 59-0 [0457] last sentence};
Choudhary/Regula and Dalal are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Choudhary/Regula before him or her, to modify Choudhary/Regula’s system incorporating Dalal’s “offload processor 6008” and “enabling processor contexts” (see Fig. 60-0, [0317]).
The suggestion/motivation for doing so would have been to implement Server-to-server connections mediation by Xockets DIMMs acting as intelligent switches to offload the TOR switch (Dalal [0002]) along with supported fast structured queues constructed from metadata via said Xockets DIMMs (Dalal [0233] paraphrased) for the purpose run structured queries in concert with fast and big data analytics on the same platform. (Dalal [0230], 1st sentence).
Therefore, it would have been obvious to combine Dalal with Choudhary/Regula to obtain the invention as specified in the instant claim(s).
Claims 5, 6, 7, 8, 9, 12, 13, 14, 15, 17, 18, 19, and 20 are rejected 35 U.S.C. 103 as being unpatentable over Choudhary in view of Pappachan and further in view of Raman and further in view of Regula and further in view of Dalal (USPGPUB No. 2023/0231811).
As per claim 5, the rejection of claim 4 is incorporated however the combination of references does not appear to explicitly disclose any limitation in this dependent claim.
Furthermore, Dalal discloses wherein the format match value is a first format match value {“the OS can determine if the packet is [format matched] for the same session or for a different session 8610”, see Fig. 86, [0463], last sentence} and the method further comprises:
extracting a third subset of bits {“one or more [bits] fields of a”, [0265]} from the header of the packet based {“header for the packet, or a header encapsulated”, [0265]} on a third offset value {“such [offset value] metadata”, [0265]};
and determining that the packet matches the packet format of the context {“’Metadata’, as used herein, can be any information embedded at one or more predetermined locations of a block of write data”, see Fig. 60, [0321], 4th sentence} by comparing the first subset of bits of the header to the first format match value {“Header services 6510 can process header data”, see Fig. 65, [0354], last two sentences} and comparing the third subset of bits of the header to the second format match value {“converting protocols of [first format] IPV4 (contain IPv6 protocol packets as payload) into [second format] protocols of IPv6”}.
Choudhary/Pappuchan/Raman/Regula and Dalal are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Choudhary/Pappuchan/Raman/Regula and Dalal before him or her, to modify Choudhary/Pappuchan/Raman/Dalal’s system incorporating Dalal’s “offload processor 6008” and “enabling processor contexts” (see Fig. 60-0, [0317]).
The suggestion/motivation for doing so would have been to implement Server-to-server connections mediation by Xockets DIMMs acting as intelligent switches to offload the TOR switch (Dalal [0002]) along with supported fast structured queues constructed from metadata via said Xockets DIMMs (Dalal [0233] paraphrased) for the purpose run structured queries in concert with fast and big data analytics on the same platform. (Dalal [0230], 1st sentence).
Therefore, it would have been obvious to combine Dalal with Choudhary/Pappuchan/Raman/Regula to obtain the invention as specified in the instant claim(s).
As per claim 6, the rejection of claim 5 is incorporated and Dalal discloses further comprising determining that the packet matches the packet format of the context {“the OS can determine if the packet is [format matched] for the same session or for a different session 8610”, see Fig. 86, [0463], last sentence} by comparing a type of the packet with a packet type value {“where a session corresponds to a data packet source, network traffic type, target application, target socket, or the like”, see Fig. 83, [0437]}.
As per claim 7, the rejection of claim 4 is incorporated however the combination of references does not appear to explicitly disclose any limitation in this dependent claim.
Furthermore, Dalal discloses applying a bit mask {“the [VF] driver employs a means to mask”, see Fig. 79, [0403], last three sentences} to the first subset of bits to provide a subset of masked bits of the header {“a filtering of [subset of masked bits] possible signatures is performed at the header level for Suricata”, see Fig. [0212]};
and determining that the packet matches the packet format of the context by comparing {“the OS can determine if the packet is [format matched] for the same session or for a different session 8610”, see Fig. 86, [0463], last sentence} the subset of masked bits of the header to the format match value {“where a session corresponds to a data packet source, network traffic type, target application, target socket, or the like [such as masked bits]” as claimed, see Fig. 83, [0437]}.
The 103 motivation for this dependent claim relied upon as recited in claim 5 above.
As per claim 8, the rejection of claim 4 is incorporated however the combination of references does not appear to explicitly disclose any limitation in this dependent claim.
Furthermore, Dalal discloses further comprising extracting the second subset of bits from the header of the packet {“From extracted [a subset of bits] metadata, scheduler 6216 can create a processing schedule”, see Fig. 62-0 [0339]} based on the second offset value {“such [offset value] metadata”, [0265]} and a field-width value {“can include one or more fields [and respective width] of a header for”, see Fig. 59a [0265]}.
The 103 motivation for this dependent claim relied upon as recited in claim 5 above.
As per claim 9, the rejection of claim 8 is incorporated and Dalal discloses wherein the field-width value is a first field-width value {“can include one or more fields [and respective width] of a header for”, see Fig. 59a [0265]}, and the method further comprises:
extracting a third subset of bits {“data evaluator 6014 can extract “metadata” from write data”, see Fig. 60-0 [0321]} from the header of the packet based on a third offset value {“such [offset value] metadata”, [0265]} and a second field-width value {“can include one or more fields [and respective width] of a header for”, see Fig. 59a [0265]};
and determining the context index value of the packet {“The entire cache context [and respective context index value] is saved beginning at the session boundary”, see Fig. [0459]} based on the second subset of bits {“From extracted [a subset of bits] metadata, scheduler 6216 can create a processing schedule”, see Fig. 62-0 [0339]} and the third subset of bits extracted from the header {“data evaluator 6014 can extract “metadata” from write data”, see Fig. 60-0 [0321]}.
As per claims 12-15 are device claims reciting claim functional language corresponding to the apparatus claims of claims 5-9, respectively, thereby rejected under the same rationale as claims 5-9 recited above.
As per claims 17-20 are system claims reciting claim functional language corresponding to the apparatus claims of claims 5-9, respectively, thereby rejected under the same rationale as claims 5-9 recited above, inter alia, per claim 20, Dalal discloses wherein the SoC is configured as a host bus adapter {Examiner’s note: recitation “or extracting the second subset”, said “or” renders this dependent claim as a Markush claim, thus the references needs only disclose one group member to address the claim.}, a communication transceiver, a memory controller, a storage controller, a network switch device, a switch telemetry device, an artificial intelligence accelerator {“including a single SoC type IC.”, see Fig. 60-1, [0329], , or an accelerator SoC {“having hardware accelerator modules”, [0005]}.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding in claim 1’s “PACKET FORMAT”, “HEADER”, or “context base value”: US 20260046317 A1, US 12445541 B1, US 12432211 B2, US 12405843, B2, US 20240419616 A1, US 20240244001 A1, US 20240211583 A1, US 11824799 B2, US 20230325225 A1, US 11711305 B2,US 11477119 B1, US 11343358 B2, US 20220085916 A1, US 20210058367 A1, US 10764410 B2, , US 20200125501 A1, US 20190158605 A1, US 8943201 B2, US 20140201417 A1, US 20110106981 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184