DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on August 20, 2025, in response to PTO Office Action mailed on July 2, 2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1-3 and 7 have been amended. Claim 6 has been cancelled. As a result, claims 1-5 and 7-10 are now pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Response to Arguments
Applicant's arguments filed on August 20, 2025, in response to PTO Office Action mailed on July 2, 2025, have been fully considered but are not persuasive.
Applicant argued that none of the prior arts of record (Huang et al. (Publication Number US 2019/0235592 A1) and Hashemi (Patent Number US 5,491,787)) discloses feature A which refers to, as defined by the Applicant, “the technical features of the signal received and processed by the device to be controlled.” Examiner notes that claims are given the broadest reasonable interpretation consistent with the specification (See In re Morris, 127 F.3d 1048, 44 USPQ2d 1023 (Fed. Cir. 1997). See MPEP § 2111 – § 2116.01 for case law pertinent to claim analysis).
“Feature A” as defined by the Applicant in the argument is so broad that it can be interpreted as including any process of inputting a signal by a device so that the device can be controlled. In the context of the instant application, as interpreted by the Examiner, the claims disclose that the device to be controlled contains “a programmable logic component (see module 202 that works in conjunction with fan 206 in [FIG. 2] of Huang et al.), and the programmable logic component comprises: a first register connected to the first control component and the arbitration component (with arbitration disclosed by Huang et al. in [Paragraphs 0033 and 0036-0037]) through a first inter-integrated circuit a second register connected to the second control component and the arbitration component through a second inter-integrated circuit (Hashimi et al. discloses the presence of several registers as used in error reporting/handling module 38 in [Column 7, lines 11-50]) and a comparator connected to the first register and the second register, and configured to compare a first pulse width modulation of the first register with a second pulse width modulation of the second register, and use a larger one of the first pulse width modulation and the second pulse width modulation as a control signal of the device to be controlled (there are two fan control signals (PWM_1, PWM_2) that can be pulse-width modulated (PWM) signals indicating a duty cycle as output to an arbitrator circuit 250 as disclosed by Huang et al. in [Paragraph 0035]. There also exists sequences of pulses defining some other duty cycle, as disclosed by Huang et al. in [Paragraph 0043]).”
Furthermore, in response to the Applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Hashimi et al. is directed to the presence of several registers [Column 7, lines 11-50] with arbitration disclosed by Huang et al. in [Paragraphs 0033 and 0036-0037].
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-5 and 8-9 are rejected under 35 U.S.C. 103(a) as being unpatentable over Huang et al. (Publication Number US 2019/0235592 A1) in view of Hashemi (Patent Number US 5,491,787).
As per claim 1, Huang et al. discloses “A server motherboard control system, comprising: a device to be controlled (a fan 206 is controlled through a main board 202; FIG. 2).” Huang et al. discloses “an arbitration component connected to the device to be controlled (PWM arbitrator 250; FIG. 2).” Huang et al. discloses “a first control component (through controller 212; FIG. 2) connected to the arbitration component and configured to control the device to be controlled through the arbitration component, and the first control component having a first pin (Paragraphs 0033 and 0036-0037).”
Huang et al. discloses “and a comparator connected to the first register and the second register, and configured to compare a first pulse width modulation of the first register with a second pulse width modulation of the second register, and use a larger one of the first pulse width modulation and the second pulse width modulation as a control signal of the device to be controlled (there are two fan control signals (PWM_1, PWM_2) that can be pulse-width modulated (PWM) signals indicating a duty cycle as output to an arbitrator circuit 250 [Paragraph 0035]. There also exists sequences of pulses defining some other duty cycle; Paragraph 0043).” However, Huang et al. does not disclose the presence of a second control component connected directly to the first control component in the manner as disclosed in the limitation “a second control component connected to the arbitration component and configured to control the device to be controlled through the arbitration component, and the second control component having a second pin, wherein the first control component and the second control component are connected to each other through the first pin and the second pin, the first control component is configured to have access to the arbitration component when determining that the second control component is in a hung state through the first pin, and the second control component is configured to have access to the arbitration component when determining that the first control component is in a hung state through the second pin,” “wherein the device to be controlled comprises a programmable logic component, and the programmable logic component comprises: a first register connected to the first control component and the arbitration component through a first inter-integrated circuit,” and “a second register connected to the second control component and the arbitration component through a second inter-integrated circuit.”
Hashemi discloses the presence of a second control component connected directly to the first control component in the manner as disclosed in the limitation “a second control component connected to the arbitration component and configured to control the device to be controlled through the arbitration component (there exists Proc 1 and Proc 2 [FIG. 2]. The bus request input allows other masters to arbitrate for control of the processor channel; Column 11, lines 62-63), and the second control component having a second pin, wherein the first control component and the second control component are connected to each other through the first pin and the second pin (through the ERR1 and ERR2 lines; FIG. 2), the first control component is configured to have access to the arbitration component when determining that the second control component is in a hung state through the first pin, and the second control component is configured to have access to the arbitration component when determining that the first control component is in a hung state through the second pin (in the event that a current master processor is hung [Column 7, lines 61-64]. See also the use of ERR1 and ERR2 where there are circumstances where the processor is relinquishing control of the channel [Column 11, lines 50-66]).”
Hashemi discloses “wherein the device to be controlled comprises a programmable logic component, and the programmable logic component comprises: a first register connected to the first control component and the arbitration component through a first inter-integrated circuit (the presence of several registers as used in error reporting/handling module 38 [Column 7, lines 11-50], with arbitration disclosed by Huang et al. in [Paragraphs 0033 and 0036-0037]).” Hashemi discloses “a second register connected to the second control component and the arbitration component through a second inter-integrated circuit (the presence of several registers as used in error reporting/handling module 38 [Column 7, lines 11-50], with arbitration disclosed by Huang et al. in [Paragraphs 0033 and 0036-0037]).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Huang et al. and Hashemi in order to provide a fault-tolerant processor configuration [Column 3, lines 31-33].
As per claim 2, Huang et al. discloses “The server motherboard control system of claim 1 (as disclosed by Huang et al. and Hashemi above), wherein the device to be controlled comprises a fan (fan 206; FIG. 2), and the arbitration component is connected to a power supply unit of the fan (PWM source [FIG. 2]. Note power usage and status; Paragraphs 0096-0097).”
As per claim 3, Huang et al. discloses “The server motherboard control system of claim 1 (as disclosed by Huang et al. and Hashemi above), wherein the first control component is connected to the arbitration component through a first inter-integrated circuit (I2C/SMBus and the PWM_1 and PWM_2 buses; FIG. 2), the second control component is connected to the arbitration component through a second inter-integrated circuit (there presence of a second controller is disclosed by Hashemi in [FIG. 2] while Huang et al. is directed to the inter-integrated circuits/wiring in [FIG. 2]), and the arbitration component is connected to the device to be controlled through a third inter-integrated circuit (through PWM_Out; FIG. 2).”
As per claim 4, Huang et al. discloses “The server motherboard control system of claim 1 (as disclosed by Huang et al. and Hashemi above), further comprising: a plurality of sensors (Paragraph 0097).” Huang et al. discloses “and a switching component connected to the plurality of sensors and the arbitration component (specifically SEL 460 which inputs signals from fan control unit 410 and Alive Detect Circuit 454; FIG. 4B), wherein the first control component and the second control component are further configured to switch a plurality of connection pins of the switching component according to a specified signal to obtain a sensing signal of one of the plurality of sensors (focus on the actions of SEL 460; Paragraphs 0063 and 0066-0067).”
As per claim 5, Huang et al. discloses “The server motherboard control system of claim 4 (as disclosed by Huang et al. and Hashemi above), wherein the switching component is a multi-channel inter-integrated circuit switching component (specifically SEL 460 which inputs signals from fan control unit 410 and Alive Detect Circuit 454; FIG. 4B).”
As per claim 8, Hashemi discloses “The server motherboard control system of claim 1 (as disclosed by Huang et al. and Hashemi above), wherein the first control component further comprises a plurality of first spare pins in addition to the first pin, and the second control component further comprises a plurality of second spare pins in addition to the second pin, and the first pin, the second pin, the plurality of first spare pins and the plurality of second spare pins are general-purpose input and output pins (in addition to the ERR1 and ERR2 lines there are also INTR lines and as well as lines 26, 28, 30, and 32; FIG. 2).”
As per claim 9, Hashemi discloses “The server motherboard control system of claim 1 (as disclosed by Huang et al. and Hashemi above), wherein the first control component is further connected to a first computing component, and the second control component is further connected to a second computing component (connections between Proc 1 and Proc 2 either directly through lines 26, 28, 30, and 32 or indirectly through the Error Reporting/Handling module 38; FIG. 2).”
Claim 7 is rejected under 35 U.S.C. 103(a) as being unpatentable over Huang et al. (Publication Number US 2019/0235592 A1) and Hashemi (Patent Number US 5,491,787) in view of Li (Publication Number US 2022/0206777 A1).
As per claim 7, Huang et al. and Hashemi disclose “The server motherboard control system of claim 6 (as disclosed by Huang et al. and Hashemi above).” However, Huang et al. and Hashemi do not disclose “wherein the programmable logic component further comprises a memory connected to the arbitration component, wherein first control component and the second control component are further configured to perform a firmware update operation on the memory.”
Li discloses “wherein the programmable logic component further comprises a memory connected to the arbitration component, wherein first control component and the second control component are further configured to perform a firmware update operation on the memory (Paragraphs 0033-0034).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Huang et al. and Hashemi in order to provide a function while the firmware is being updated [Paragraphs 0002-0005].
Claim 10 is rejected under 35 U.S.C. 103(a) as being unpatentable over Huang et al. (Publication Number US 2019/0235592 A1) and Hashemi (Patent Number US 5,491,787) in view of Cao et al. (Publication Number US 2012/0296941 A1).
As per claim 10, discloses “The server motherboard control system of claim 1 (as disclosed by Huang et al. and Hashemi above).” However, Huang et al. and Hashemi do not disclose “wherein a motherboard of the server motherboard control system is based on a Birch stream platform architecture.”
Cao et al. discloses “wherein a motherboard of the server motherboard control system is based on a Birch stream platform architecture (stream based clustering algorithms such as BIRCH; Paragraph 0035).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Huang et al with elements of Cao et al. in order to handle various spatial clustering algorithms associated with various contexts [Paragraph 0035].
CONCLUDING REMARKS
Conclusions
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.W.Y/Examiner, Art Unit 2181 November 6, 2025
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181