DETAILED ACTION
This action is responsive to the RCE filed 17 Jul 2025. Claims 1-20 are pending. Claims 1, 7, 13 and 17 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The Application Title has been changed to the following:
“OUTPUT LATCH AND AMPLIFIER USING TWO VOLTAGE DOMAINS AND KEEPER CIRCUIT”
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 17 Jul 2026 has been entered. Claims 1-20 are currently pending in the application.
Response to Arguments
Applicant’s arguments filed on 17 Jul 2026 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 102 as the claims are currently written. Applicant’s arguments with respect to claims 1, 7, 13 and 17 have been considered but are moot because the arguments do not apply to the citations being used in the current rejection. This office relies on Applicant’s Admitted Prior Art and a new reference Rozas..
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rozas, et al, U.S. Patent Application Publication 2014/0337659 (“Rozas”).
Regarding claim 1, Rozas teaches:
A circuit comprising: a bit-storing cell comprising a first read/write voltage domain crossing; (Rozas, fig 1, “[0016] FIG. 1 is a block diagram of one embodiment of an asynchronous FIFO memory 100. [0018] During operation of memory 100, output bits 190 flowing into dynamic mux 130 are driven by write voltage supply 170. FIFO memory array 120 remains entirely in the write domain. [0030] Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.”; a memory cell with an input write domain and output read domain, with the output bits flowing from the FIFO memory cell to the dynamic mux 130 (200 in figure 2) enroute to the output signal of figures 2 and 3; in paragraph 0030, Rozas explicitly states that the disclosed embodiments can be substituted with each other to create a third embodiment. This office action has substituted Rozas fig 2 as the “dynamic multiplexor” of figure 1 which similarly places the fig 2 circuits as a substitution in figure 3).
a read latch coupled to the bit-storing cell via a read bitline; and (Rozas, fig 1, 3, “[0028] During read operation, assuming the appropriate addressing, the illustrated 8T cell of memory array 350 is coupled to read bitline 336. Memory 300 includes a data read latch 330-R powered by read voltage supply 306 and clocked by read clock 310.”; a read domain voltage supply of 214 in figure 2 and 306 in figure 3 with a read latch of 204 of figure 2 and 330-R of figure 3. Figure 2 provides an optional “pre-charge” circuit that resides between the 336 Read Bitline and output latch 330-R of figure 3).
the read latch comprising a second read/write voltage domain crossing. (Rozas, fig 1, 3, “[0016] The output of dynamic mux 130 and the data select lines are both driven by read voltage supply 180. Thus, dynamic mux 130 operates to shift logic levels from the write domain to the read domain”; the precharge circuit of figure 2 and the read bitline of figure 3 are powered by the read voltage domains, that the 214 source of figure 2 and 306 source of figure 3 represent the same read voltage domain).
Regarding claim 2, Rozas teaches The circuit of claim 1, wherein the second read/write voltage domain crossing is configured in a pull-down network of the read latch. (Rozas, fig 2, “[0019] FIG. 2 is a schematic of one embodiment of a dynamic multiplexer 200, or of the asynchronous FIFO memory embodiment of FIG. 1. Mux 200 includes a series of NMOS pull-down stacks, NMOS pull-down 202-1, NMOS pull-down 202-2 and NMOS pull-down 202-3.”; fig 2, which is an embodiment of the dynamic multiplexor of figure 1; that the dynamic multiplexor 130/200 is powered by the second reading voltage domain; that the dynamic multiplexor has a pull-down network in the read voltage domain).
Regarding claim 3, Rozas teaches The circuit of claim 2, wherein the second read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (Rozas, fig 2, “[0020] In the embodiment of FIG. 2, NMOS pull-down 202-1 has one gate driven by a data input 216-1, and a second gate driven by a data select 218-1. Likewise, NMOS pull-down 202-2 is driven by a data input 216-2 and a data select 218-2, and NMOS pull-down 202-3 is driven by a data input 216-3 and a data select 218-3.”; a single, double or triple pull-down network in the second domain based on read data from the FIFO of fig 1 or the 336 input of fig 3 via the inverters 210 or 328. Note: because applicant has chosen the “comprising” construction of this claim, the art is not limited to a single transistor, rather it must be configured with at least one transistor- as taught by Rozas).
Regarding claim 4, Rozas teaches The circuit of claim 2, wherein the pull-down network is configured on a latching node of the read latch. (Rozas, fig 2, 3, “[0022] Mux 200 also includes a dynamic-to-static converter, or “glitch latch,” 204 that is clocked by pre-charge signal 212”; the dynamic multiplexor 130/200 which has a latching node which is 204 or 330-R of fig 3 which has the read data inputs via the inverters 210 or 328).
Regarding claim 5, Rozas teaches The circuit of claim 4, further comprising: a keeper circuit coupled between the read bitline and the latching node. (Rozas, fig 2, 3, “[0022] … To aid in latching the appropriate value, mux 200 further includes a keeper circuit having an inverter 210 coupled to the dynamic node and a PMOS transistor 208. PMOS transistor 208 has a source powered by read voltage source 214, a gate driven by an inverted feedback, and a drain coupled to the dynamic node.”; the dynamic multiplexor 130/200 takes the data line from the FIFO of fig 3 as input and processes the signal).
Regarding claim 6, Rozas teaches The circuit of claim 1, wherein the first read/write voltage domain crossing is configured at an interface of the bit-storing cell to the read bitline. (Rozas, fig 2, 3, “[0024] Memory array 350 includes a read wordline (RWL) 314, a write wordline (WWL) 322, a read bitline (RBL) 336,”; a read bitline coming from the memory cell interface at the Q node of the memory invertors interface via dual transistors- the data signal 336 is then fed to either the invertor 210 (a precharge network) or directly to the invertor 328; here the “first read/write voltage domain” is the write domain using the WWL to write at the bit-storing inverters).
Regarding claim 7, Rozas teaches:
A circuit comprising: a bit-storing cell configured to operate in a write voltage domain; (Rozas, fig 1, “[0016] FIG. 1 is a block diagram of one embodiment of an asynchronous FIFO memory 100. [0018] During operation of memory 100, output bits 190 flowing into dynamic mux 130 are driven by write voltage supply 170. FIFO memory array 120 remains entirely in the write domain.”; a memory cell with an input write domain and output read domain, with the output bits flowing from the FIFO memory cell to the dynamic mux 130 (200 in figure 2) enroute to the output signal of figures 2 and 3; in paragraph 0030, Rozas explicitly states that the disclosed embodiments can be substituted with each other to create a third embodiment. This office action has substituted Rozas fig 2 as the “dynamic multiplexor” of figure 1 which similarly places the fig 2 circuits as a substitution in figure 3).
a read latch coupled to the bit-storing cell via a read bitline, the read bitline configured to operate in a read voltage domain different than the write voltage domain; and (Rozas, fig 1, 3, “[0028] During read operation, assuming the appropriate addressing, the illustrated 8T cell of memory array 350 is coupled to read bitline 336. Memory 300 includes a data read latch 330-R powered by read voltage supply 306 and clocked by read clock 310.”; a read domain voltage supply of 214 in figure 2 and 306 in figure 3 with a read latch of 204 of figure 2 and 330-R of figure 3. Figure 2 provides an optional “pre-charge” circuit that resides between the 336 Read Bitline and output latch 330-R of figure 3).
a first read/write voltage domain crossing configured in the read latch. (Rozas, fig 1, 3, “[0016] The output of dynamic mux 130 and the data select lines are both driven by read voltage supply 180. Thus, dynamic mux 130 operates to shift logic levels from the write domain to the read domain”; the precharge circuit of figure 2 and the read bitline of figure 3 are powered by the read voltage domains, that the 214 source of figure 2 and 306 source of figure 3 represent the same read voltage domain).
Regarding claim 8, Rozas teaches The circuit of claim 7, wherein the first read/write voltage domain crossing is configured in a pull-down network of the read latch. (Rozas, fig 2, “[0019] FIG. 2 is a schematic of one embodiment of a dynamic multiplexer 200, or of the asynchronous FIFO memory embodiment of FIG. 1. Mux 200 includes a series of NMOS pull-down stacks, NMOS pull-down 202-1, NMOS pull-down 202-2 and NMOS pull-down 202-3.”; fig 2, which is an embodiment of the dynamic multiplexor of figure 1; that the dynamic multiplexor 130/200 is powered by the second reading voltage domain; that the dynamic multiplexor has a pull-down network in the read voltage domain).
Regarding claim 9, Rozas teaches The circuit of claim 8, wherein the first read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (Rozas, fig 2, “[0020] In the embodiment of FIG. 2, NMOS pull-down 202-1 has one gate driven by a data input 216-1, and a second gate driven by a data select 218-1. Likewise, NMOS pull-down 202-2 is driven by a data input 216-2 and a data select 218-2, and NMOS pull-down 202-3 is driven by a data input 216-3 and a data select 218-3.”; a single, double or triple pull-down network in the second domain based on read data from the FIFO of fig 1 or the 336 input of fig 3 via the inverters 210 or 328. Note: because applicant has chosen the “comprising” construction of this claim, the art is not limited to a single transistor, rather it must be configured with at least one transistor- as taught by Rozas).
Regarding claim 10, Rozas teaches The circuit of claim 8, wherein the pull-down network is configured on a latching node of the read latch. (Rozas, fig 2, 3, “[0022] Mux 200 also includes a dynamic-to-static converter, or “glitch latch,” 204 that is clocked by pre-charge signal 212”; the dynamic multiplexor 130/200 which has a latching node which is 204 or 330-R of fig 3 which has the read data inputs via the inverters 210 or 328).
Regarding claim 11, Rozas teaches The circuit of claim 10, further comprising: a keeper circuit coupled between the read bitline and the latching node. (Rozas, fig 2, 3, “[0022] … To aid in latching the appropriate value, mux 200 further includes a keeper circuit having an inverter 210 coupled to the dynamic node and a PMOS transistor 208. PMOS transistor 208 has a source powered by read voltage source 214, a gate driven by an inverted feedback, and a drain coupled to the dynamic node.”; the dynamic multiplexor 130/200 takes the data line from the FIFO of fig 3 as input and processes the signal).
Regarding claim 12, Rozas teaches The circuit of claim 7, wherein the bit-storing cell comprises a second read/write voltage domain crossing at an interface to the read bitline. (Rozas, fig 2, 3, “[0024] Memory array 350 includes a read wordline (RWL) 314, a write wordline (WWL) 322, a read bitline (RBL) 336,”; a read bitline coming from the memory cell interface at the Q node of the memory invertors interface via dual transistors- the data signal 336 is then fed to either the invertor 210 (a precharge network) or directly to the invertor 328).
Regarding claim 13, Rozas teaches:
A memory system comprising: a memory bank comprising a plurality of bit-storing cells operating in a write voltage domain; (Rozas, fig 1, “[0016] FIG. 1 is a block diagram of one embodiment of an asynchronous FIFO memory 100. [0018] During operation of memory 100, output bits 190 flowing into dynamic mux 130 are driven by write voltage supply 170. FIFO memory array 120 remains entirely in the write domain. [0030] Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.”; a memory cell with an input write domain and output read domain, with the output bits flowing from the FIFO memory cell to the dynamic mux 130 (200 in figure 2) enroute to the output signal of figures 2 and 3; in paragraph 0030, Rozas explicitly states that the disclosed embodiments can be substituted with each other to create a third embodiment. This office action has substituted Rozas fig 2 as the “dynamic multiplexor” of figure 1 which similarly places the fig 2 circuits as a substitution in figure 3).
the bit-storing cells coupled to a read bitline operating in a read voltage domain different than the write voltage domain; (Rozas, fig 1, 3, “[0028] During read operation, assuming the appropriate addressing, the illustrated 8T cell of memory array 350 is coupled to read bitline 336. Memory 300 includes a data read latch 330-R powered by read voltage supply 306 and clocked by read clock 310.”; a read domain voltage supply of 214 in figure 2 and 306 in figure 3 with a read latch of 204 of figure 2 and 330-R of figure 3. Figure 2 provides an optional “pre-charge” circuit that resides between the 336 Read Bitline and output latch 330-R of figure 3).
a read latch coupled to the read bitline; (Rozas, fig 1, 3, “[0016] The output of dynamic mux 130 and the data select lines are both driven by read voltage supply 180. Thus, dynamic mux 130 operates to shift logic levels from the write domain to the read domain”; the precharge circuit of figure 2 and the read bitline of figure 3 are powered by the read voltage domains, that the 214 source of figure 2 and 306 source of figure 3 represent the same read voltage domain).
a keeper circuit coupled between the read bitline at a latching node of the read latch; and (Rozas, fig 2, 3, “[0022] … To aid in latching the appropriate value, mux 200 further includes a keeper circuit having an inverter 210 coupled to the dynamic node and a PMOS transistor 208. PMOS transistor 208 has a source powered by read voltage source 214, a gate driven by an inverted feedback, and a drain coupled to the dynamic node.”; the dynamic multiplexor 130/200 takes the data line from the FIFO of fig 3 as input and processes the signal).
a first read/write voltage domain crossing coupled to the latching node. (Rozas, fig 1, 3, “[0028] During read operation, assuming the appropriate addressing, the illustrated 8T cell of memory array 350 is coupled to read bitline 336. Memory 300 includes a data read latch 330-R powered by read voltage supply 306 and clocked by read clock 310.”; a read domain voltage supply of 214 in figure 2 and 306 in figure 3 with a read latch of 204 of figure 2 and 330-R of figure 3. Figure 2 provides an optional “pre-charge” circuit that resides between the 336 Read Bitline and output latch 330-R of figure 3; here the “first read/write voltage domain crossing” must be the same as the read voltage domain to mirror applicant’s specification which comprises only two domains).
Regarding claim 14, Rozas teaches The circuit of claim 13, wherein the first read/write voltage domain crossing is configured in a pull-down network of the read latch. (Rozas, fig 2, “[0019] FIG. 2 is a schematic of one embodiment of a dynamic multiplexer 200, or of the asynchronous FIFO memory embodiment of FIG. 1. Mux 200 includes a series of NMOS pull-down stacks, NMOS pull-down 202-1, NMOS pull-down 202-2 and NMOS pull-down 202-3.”; fig 2, which is an embodiment of the dynamic multiplexor of figure 1; that the dynamic multiplexor 130/200 is powered by the second reading voltage domain; that the dynamic multiplexor has a pull-down network in the read voltage domain).
Regarding claim 15, Rozas teaches The circuit of claim 14, wherein the first read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (Rozas, fig 2, “[0020] In the embodiment of FIG. 2, NMOS pull-down 202-1 has one gate driven by a data input 216-1, and a second gate driven by a data select 218-1. Likewise, NMOS pull-down 202-2 is driven by a data input 216-2 and a data select 218-2, and NMOS pull-down 202-3 is driven by a data input 216-3 and a data select 218-3.”; a single, double or triple pull-down network in the second domain based on read data from the FIFO of fig 1 or the 336 input of fig 3 via the inverters 210 or 328. Note: because applicant has chosen the “comprising” construction of this claim, the art is not limited to a single transistor, rather it must be configured with at least one transistor- as taught by Rozas).
Regarding claim 16, Rozas teaches The circuit of claim 14, wherein the bit-storing cell comprises a second read/write voltage domain crossing at an interface to the read bitline. (Rozas, fig 2, 3, “[0024] Memory array 350 includes a read wordline (RWL) 314, a write wordline (WWL) 322, a read bitline (RBL) 336,”; a read bitline coming from the memory cell interface at the Q node of the memory invertors interface via dual transistors- the data signal 336 is then fed to either the invertor 210 (a precharge network) or directly to the invertor 328; here the “second read/write voltage domain” is the write domain using the WWL to write at the bit-storing inverters).
Regarding claim 17, Rozas teaches:
A process comprising: configuring a bit-storing cell to operate in a write voltage domain of a memory circuit; (Rozas, fig 1, “[0016] FIG. 1 is a block diagram of one embodiment of an asynchronous FIFO memory 100. [0018] During operation of memory 100, output bits 190 flowing into dynamic mux 130 are driven by write voltage supply 170. FIFO memory array 120 remains entirely in the write domain. [0030] Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.”; a memory cell with an input write domain and output read domain, with the output bits flowing from the FIFO memory cell to the dynamic mux 130 (200 in figure 2) enroute to the output signal of figures 2 and 3; in paragraph 0030, Rozas explicitly states that the disclosed embodiments can be substituted with each other to create a third embodiment. This office action has substituted Rozas fig 2 as the “dynamic multiplexor” of figure 1 which similarly places the fig 2 circuits as a substitution in figure 3).
configuring a read latch coupled to the bit-storing cell via a read bitline to operate in a read voltage domain different than the write voltage domain; and (Rozas, fig 1, 3, “[0028] During read operation, assuming the appropriate addressing, the illustrated 8T cell of memory array 350 is coupled to read bitline 336. Memory 300 includes a data read latch 330-R powered by read voltage supply 306 and clocked by read clock 310.”; a read domain voltage supply of 214 in figure 2 and 306 in figure 3 with a read latch of 204 of figure 2 and 330-R of figure 3. Figure 2 provides an optional “pre-charge” circuit that resides between the 336 Read Bitline and output latch 330-R of figure 3).
configuring a read/write voltage domain crossing in the read latch. (Rozas, fig 1, 3, “[0016] The output of dynamic mux 130 and the data select lines are both driven by read voltage supply 180. Thus, dynamic mux 130 operates to shift logic levels from the write domain to the read domain”; the precharge circuit of figure 2 and the read bitline of figure 3 are powered by the read voltage domains, that the 214 source of figure 2 and 306 source of figure 3 represent the same read voltage domain).
Regarding claim 18, Rozas teaches The process of claim 17, wherein the read/write voltage domain crossing is configured in a pull-down network of the read latch. (Rozas, fig 2, “[0019] FIG. 2 is a schematic of one embodiment of a dynamic multiplexer 200, or of the asynchronous FIFO memory embodiment of FIG. 1. Mux 200 includes a series of NMOS pull-down stacks, NMOS pull-down 202-1, NMOS pull-down 202-2 and NMOS pull-down 202-3.”; fig 2, which is an embodiment of the dynamic multiplexor of figure 1; that the dynamic multiplexor 130/200 is powered by the second reading voltage domain; that the dynamic multiplexor has a pull-down network in the read voltage domain).
Regarding claim 19, Rozas teaches The process of claim 18, wherein the read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (Rozas, fig 2, “[0020] In the embodiment of FIG. 2, NMOS pull-down 202-1 has one gate driven by a data input 216-1, and a second gate driven by a data select 218-1. Likewise, NMOS pull-down 202-2 is driven by a data input 216-2 and a data select 218-2, and NMOS pull-down 202-3 is driven by a data input 216-3 and a data select 218-3.”; a single, double or triple pull-down network in the second domain based on read data from the FIFO of fig 1 or the 336 input of fig 3 via the inverters 210 or 328. Note: because applicant has chosen the “comprising” construction of this claim, the art is not limited to a single transistor, rather it must be configured with at least one transistor- as taught by Rozas).
Regarding claim 20, Rozas teaches The process of claim 18, further comprising: configuring the pull-down network on a latching node of the read latch. (Rozas, fig 2, 3, “[0022] Mux 200 also includes a dynamic-to-static converter, or “glitch latch,” 204 that is clocked by pre-charge signal 212”; the dynamic multiplexor 130/200 which has a latching node which is 204 or 330-R of fig 3 which has the read data inputs via the inverters 210 or 328).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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