DETAILED ACTION
This action is responsive to the application filed 1 Dec 2025. Claims 1-20 are pending. Claims 1, 7, 13 and 17 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The Application Title has been changed to the following:
“OUTPUT LATCH AND AMPLIFIER USING TWO VOLTAGE DOMAINS AND KEEPER CIRCUIT”
Response to Amendment
The Amendment filed 1 Dec 2025 has been entered. Claims 1-20 are currently pending in the application.
Response to Arguments
Applicant’s arguments filed on 1 Dec 2025 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 102 as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
Argument 1: The Applicant states “Throughout the entire disclosure of Yap, the bit-storing cell 300 is described as operating from a single supply domain (Vdd).”
Response 1: The Examiner agrees. However, applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., “operating from a single supply domain”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). (see MPEP 2145 (VI).)
Yap teaches that two distinct lines power the circuit for two distinct purposes: the 310 WLW, and the 315 WLR as the rejection is written and shown in figures 3A, 3B, 4A, and 4B. From Yap paragraph “[0039] Non terminated input BL 155, may hold input data for write operations, with writes enabled by asserting WLW 310. BL 155 may also be used to sense data read from configuration latch 300, with reads enabled by asserting WLR 315.”
Argument 2: The Applicant states “The Office Action asserts that there is a voltage domain crossing between the read voltage domain and the write voltage domain because (a) the bitline 155 is used to both read bits from the data latch 302 and write bits to the data latch 302, and (b) the bitline 155 and read enable signal 315 are applied at different gates of transistor T1 in the pull-down network 304.”
Response 2: The Examiner respectfully disagrees. The Office Action clearly quotes Yap paragraph [0039] above. In paragraph [0039], the write domain is “asserted” by the voltages on WLW 310 while the read domain is “enabled by asserting WLR 315”.
Argument 3: The Applicant states “The Applicant's Specification, Drawings, and Claims consistently identify the read voltage domain and write voltage domain as different voltage domains (different ranges of high and low supply voltages - see Applicant's Specification, Par. 19). A broadest reasonable interpretation of the Claims cannot treat these distinct voltage domains as a single or the same voltage domain.”
Response 3: The Examiner disagrees. Regardless of this argument, Yap teaches two voltage domains from two distinct voltage supplies (domains) to assert either the writing to a memory via WLW 310 or reading from a memory using WLR 315.
Moreover, applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., “operating different ranges of high and low supply voltages”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). (see MPEP 2145 (VI).)
Moreover, Applicant’s characterization of their paragraph [0019] is misleading. Paragraph [0019] states, “"Read voltage domain" herein refers to the voltage domain (range of high and low voltage levels) in which readout logic of a memory system operates. "Write voltage domain" refers to herein refers to the voltage domain (range of high and low voltage levels) in which the bit-writing and storing logic of a memory system operates.” Both the read voltage domain and the write domain comprise a “range of high and low voltages”, not a written description of different high and low voltages as argued, and certainly the different voltages are not present in the claim language.
Argument 4: The Applicant states “The Office Action presumes that the bitline 155 in Yap switches voltage supply domains between reading and writing bits.”
Response 4: The Examiner respectfully disagrees. The examiner quotes Yap as stating that the two domains are controlled by different lines, by asserting the WLW 310 for writing data and by asserting WLR 315 for reading data.
Argument 5: The Applicant states “But any such switching between supply domains on the bitline 155 would be complex, inefficient, and unnecessary. It would be especially problematic because the bitline 155 is hard wired to the single voltage domain Vdd used by the Yap cell 300 by pull- up resistor 306. Even if the power supply voltage on the bitline 155 were somehow dynamically switched between reading and writing of bits to the latch 302, the switch would be immediately nullified by the pull-up 341 to supply Vdd (causing a large current surge). Nothing in the disclosure of Yap suggests such design or operation of the cell 300.”
Response 5: The Examiner respectfully disagrees. Regardless of any imputed “inefficiency” from this argument, Yap teaches two voltage domains from two distinct voltage supplies (domains) to assert either the writing to a memory via WLW 310 or reading from a memory using WLR 315.
Moreover, applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., “switching between reading and writing”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). (see MPEP 2145 (VI).)
Whether an operation is deemed “efficient” by the applicant or not is irrelevant. Here, Yap teaches the claimed “Read/write voltage domain crossing” as simply two different power lines, or “domains”, the WLW 310 and WLR 315 that to assert either the read or write function of a memory cell.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 5 and 7 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YAP, et al, U.S. Patent Application Publication 2023/0343372 (“YAP”).
Regarding claim 1, YAP teaches:
A circuit comprising: a bit-storing cell comprising a first read/write voltage domain crossing; (YAP, fig 1A/B, 2A/B, 4!/B, “[0030] FPGA device 150 may include an array 152 of programmable elements and conductors 160. [0039] Non terminated input BL 155, may hold input data for write operations, with writes enabled by asserting WLW 310. BL 155 may also be used to sense data read from configuration latch 300, with reads enabled by asserting WLR 315.”; that data (bits) can be stored in an FPGA array 152; that a bitline BL can be used to input data or to read data using BL 155; that reading occurs in latch 300 of figures 3 and 4. WLW 310 is the write domain and WLR 315 is the read domain of voltages that are input to the reading latch 300).
a read latch coupled to the bit-storing cell via a read bitline; and (YAP, fig 3A/B, 4A/B, “[0057] In FIG. 4B, as outlined with respect to FIG. 3A, the outer dashed block 407 shows circuit elements that are repeated for each readable and resettable configuration memory latch. [0071] As shown in FIG. 4B, WLR 315 is input to gate g-N6 of nMOS transistor N6 440-6”; a read latch circuit block 407 which has both WLW (write enabling domain) and WLR (read enabled domain) as inputs for the latching circuit).
the read latch comprising a second read/write voltage domain crossing. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations.”; a read latch circuit block 407 which has the WLR and WLW driven pull-up and pull-down circuits 304 and 306; thus the “read latch” circuit of 400 has inputs from both domains: the WLW write domain and the WLR read domain).
Regarding claim 2, YAP teaches The circuit of claim 1, wherein the second read/write voltage domain crossing is configured in a pull-down network of the read latch. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 3, YAP teaches The circuit of claim 2, wherein the second read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 4, YAP teaches The circuit of claim 2, wherein the pull-down network is configured on a latching node of the read latch. (YAP, fig 4A/B, “[0084] Therefore, pull down network 304 is activated and BL 155 is pulled to 0 starting at time D7 (as shown in waveform 487 in FIG. 4D) until time D8. … [0087] Accordingly, pull-down network 304 is deactivated and BL 155 is pulled to 1 by weak pull up Rl 341.”; the network 304 performs a pull-down (and pull-up with network 306) function in the read latch circuit block 407).
Regarding claim 5, YAP teaches The circuit of claim 4, further comprising: a keeper circuit coupled between the read bitline and the latching node. (YAP, fig 4A/B, “[0081] in the read latch circuit block 407. [0084] Therefore, pull down network 304 is activated and BL 155 is pulled to 0 starting at time D7 (as shown in waveform 487 in FIG. 4D) until time D8. … [0087] Accordingly, pull-down network 304 is deactivated and BL 155 is pulled to 1 by weak pull up Rl 341.”; the network 304 performs a pull-down (and pull-up with additional network 306) function for the read latch circuit 407; that these circuits operate as the claimed “keeper” for the 155 bitline into the read latch).
Regarding claim 7, YAP teaches:
A circuit comprising: a bit-storing cell configured to operate in a write voltage domain; (YAP, fig 1A/B, 2A/B, 4!/B, “[0030] FPGA device 150 may include an array 152 of programmable elements and conductors 160. [0039] Non terminated input BL 155, may hold input data for write operations, with writes enabled by asserting WLW 310. BL 155 may also be used to sense data read from configuration latch 300, with reads enabled by asserting WLR 315.”; that data (bits) can be stored in an FPGA array 152; that a bitline BL can be used to input data or to read data using BL 155; that reading occurs in latch 300 of figures 3 and 4. WLW 310 is the write domain and WLR 315 is the read domain of voltages that are input to the reading latch 300).
a read latch coupled to the bit-storing cell via a read bitline, the read bitline configured to operate in a read voltage domain different than the write voltage domain; and (YAP, fig 3A/B, 4A/B, “[0057] In FIG. 4B, as outlined with respect to FIG. 3A, the outer dashed block 407 shows circuit elements that are repeated for each readable and resettable configuration memory latch. [0071] As shown in FIG. 4B, WLR 315 is input to gate g-N6 of nMOS transistor N6 440-6”; a read latch circuit block 407 which has both WLW (write enabling domain) and WLR (read enabled domain) as inputs for the latching circuit).
a first read/write voltage domain crossing configured in the read latch. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations.”; a read latch circuit block 407 which has the WLR and WLW driven pull-up and pull-down circuits 304 and 306; thus the “read latch” circuit of 400 has inputs from both domains: the WLW write domain and the WLR read domain).
Regarding claim 6, The circuit of claim 7, wherein the first read/write voltage domain crossing is configured at an interface of the bit-storing cell to the read bitline. (YAP, fig 4A/B, "[0078] During D2, as shown in waveform 476, BL 155 transitions to 1. However, node Q stays at 1 because P4 445-4 is on (WLW=0) and P2 445-2 is on (S=0). Subsequently, at the start of D3, WLW 310 is asserted, as shown in waveform 472. With WLW=l and BL=l, N4 440-4 and N3 440-3 are on so that node Q is pulled to 0 starting at D3, as shown in waveform 478. Accordingly, output 360 transitions to 1 starting at D3 as shown in waveform 480. At D4, WLW 310 transitions to 0 and subsequently, in D4 BL 155 transitions 0."; that WLW infaces with the read latch 407 for reading the BL 155 result at the Q node, or data output.).
Regarding claim 8, YAP teaches The circuit of claim 7, wherein the first read/write voltage domain crossing is configured in a pull-down network of the read latch. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 9, YAP teaches The circuit of claim 8, wherein the first read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 10, YAP teaches The circuit of claim 8, wherein the pull-down network is configured on a latching node of the read latch. (YAP, fig 4A/B, “[0084] Therefore, pull down network 304 is activated and BL 155 is pulled to 0 starting at time D7 (as shown in waveform 487 in FIG. 4D) until time D8. … [0087] Accordingly, pull-down network 304 is deactivated and BL 155 is pulled to 1 by weak pull up Rl 341.”; the network 304 performs a pull-down (and pull-up with network 306) function in the read latch circuit block 407).
Regarding claim 11, YAP teaches The circuit of claim 10, further comprising: a keeper circuit coupled between the read bitline and the latching node. (YAP, fig 4A/B, “[0081] in the read latch circuit block 407. [0084] Therefore, pull down network 304 is activated and BL 155 is pulled to 0 starting at time D7 (as shown in waveform 487 in FIG. 4D) until time D8. … [0087] Accordingly, pull-down network 304 is deactivated and BL 155 is pulled to 1 by weak pull up Rl 341.”; the network 304 performs a pull-down (and pull-up with additional network 306) function for the read latch circuit 407; that these circuits operate as the claimed “keeper” for the 155 bitline into the read latch).
Regarding claim 12, YAP teaches The circuit of claim 7, wherein the bit-storing cell comprises a second read/write voltage domain crossing at an interface to the read bitline. (YAP, fig 4A/B, “[0078] During D2, as shown in waveform 476, BL 155 transitions to 1. However, node Q stays at 1 because P4 445-4 is on (WLW=0) and P2 445-2 is on (S=0). Subsequently, at the start of D3, WLW 310 is asserted, as shown in waveform 472. With WLW=l and BL=l, N4 440-4 and N3 440-3 are on so that node Q is pulled to 0 starting at D3, as shown in waveform 478. Accordingly, output 360 transitions to 1 starting at D3 as shown in waveform 480. At D4, WLW 310 transitions to 0 and subsequently, in D4 BL 155 transitions 0.”; that WLW infaces with the read latch 407 for reading the BL 155 result at the Q node, or data output).
Regarding claim 13, YAP teaches:
A memory system comprising: a memory bank comprising a plurality of bit-storing cells operating in a write voltage domain; (YAP, fig 1A/B, 2A/B, 4!/B, “[0030] FPGA device 150 may include an array 152 of programmable elements and conductors 160. [0039] Non terminated input BL 155, may hold input data for write operations, with writes enabled by asserting WLW 310. BL 155 may also be used to sense data read from configuration latch 300, with reads enabled by asserting WLR 315.”; that data (bits) can be stored in an FPGA array 152; that a bitline BL can be used to input data or to read data using BL 155; that reading occurs in latch 300 of figures 3 and 4. WLW 310 is the write domain and WLR 315 is the read domain of voltages that are input to the reading latch 300).
the bit-storing cells coupled to a read bitline operating in a read voltage domain different than the write voltage domain; (YAP, fig 4A/B, “[0071] As shown in FIG. 4B, WLR 315 is input to gate g-N6 of nMOS transistor N6 440-6. When reading a “1”, WLR 315 is active, WLW 310 is inactive, and the gate g-NS of nMOS transistor NS 440-5 will be at “1” (S=l). … Accordingly, BL 155 is pulled to 0, and sensing block 362 may detect or be configured to output a “1” (representing the latched data).”; a bitline BL 155 coupled with the WLR 315 in reading the bitline value at the output Q).
a read latch coupled to the read bitline; (YAP, fig 3A/B, 4A/B, “[0057] In FIG. 4B, as outlined with respect to FIG. 3A, the outer dashed block 407 shows circuit elements that are repeated for each readable and resettable configuration memory latch. [0071] As shown in FIG. 4B, WLR 315 is input to gate g-N6 of nMOS transistor N6 440-6”; a read latch circuit block 407 which has both WLW (write enabling domain) and WLR (read enabled domain) as inputs for the latching circuit).
a keeper circuit coupled between the read bitline at a latching node of the read latch; and (YAP, fig 4A/B, “[0081] in the read latch circuit block 407. [0084] Therefore, pull down network 304 is activated and BL 155 is pulled to 0 starting at time D7 (as shown in waveform 487 in FIG. 4D) until time D8. … [0087] Accordingly, pull-down network 304 is deactivated and BL 155 is pulled to 1 by weak pull up Rl 341.”; the network 304 performs a pull-down (and pull-up with additional network 306) function for the read latch circuit 407; that these circuits operate as the claimed “keeper” for the 155 bitline into the read latch).
a first read/write voltage domain crossing coupled to the latching node. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations.”; a read latch circuit block 407 which has the WLR and WLW driven pull-up and pull-down circuits 304 and 306; thus the “read latch” circuit of 400 has inputs from both domains: the WLW write domain and the WLR read domain).
Regarding claim 14, YAP teaches The circuit of claim 13, wherein the first read/write voltage domain crossing is configured in a pull-down network of the read latch. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 15, YAP teaches The circuit of claim 14, wherein the first read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 16, YAP teaches The circuit of claim 14, wherein the bit-storing cell comprises a second read/write voltage domain crossing at an interface to the read bitline. (YAP, fig 4A/B, “[0064] In FIG. 4B, reset 305 is active low and latch reset is initiated by asserting (pulling low) reset 305. During reset (when reset 305 is asserted), there is a path from node Q to supply voltage V DD but no path from node Q to ground so that node Q is pulled high and the out 360 is 0 as explained further below”; a second “read/write voltage”, or V.sub.DD that is input via transistors in the read latch circuit block 407).
Regarding claim 17, YAP teaches:
A process comprising: configuring a bit-storing cell to operate in a write voltage domain of a memory circuit; (YAP, fig 1A/B, 2A/B, 4!/B, “[0030] FPGA device 150 may include an array 152 of programmable elements and conductors 160. [0039] Non terminated input BL 155, may hold input data for write operations, with writes enabled by asserting WLW 310. BL 155 may also be used to sense data read from configuration latch 300, with reads enabled by asserting WLR 315.”; that data (bits) can be stored in an FPGA array 152; that a bitline BL can be used to input data or to read data using BL 155; that reading occurs in latch 300 of figures 3 and 4. WLW 310 is the write domain and WLR 315 is the read domain of voltages that are input to the reading latch 300).
configuring a read latch coupled to the bit-storing cell via a read bitline to operate in a read voltage domain different than the write voltage domain; and (YAP, fig 3A/B, 4A/B, “[0057] In FIG. 4B, as outlined with respect to FIG. 3A, the outer dashed block 407 shows circuit elements that are repeated for each readable and resettable configuration memory latch. [0071] As shown in FIG. 4B, WLR 315 is input to gate g-N6 of nMOS transistor N6 440-6”; a read latch circuit block 407 which has both WLW (write enabling domain) and WLR (read enabled domain) as inputs for the latching circuit).
configuring a read/write voltage domain crossing in the read latch. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations.”; a read latch circuit block 407 which has the WLR and WLW driven pull-up and pull-down circuits 304 and 306; thus the “read latch” circuit of 400 has inputs from both domains: the WLW write domain and the WLR read domain).
Regarding claim 18, YAP teaches The process of claim 17, wherein the read/write voltage domain crossing is configured in a pull-down network of the read latch. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 19, YAP teaches The process of claim 18, wherein the read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network. (YAP, fig 4A/B, “[0041] In some embodiments, configuration latch 300 may include a D-Latch 302, coupled to: (a) pull-down network 304, which, when activated, facilitates sensing “0” (on BL 155) by sensing block 362 during read operations, and (b) weak pull-up, which (when pull-down down network 304 is inactive) facilitates sensing “1” (on BL 155) by sensing block 362 during read operations. [0055] [0056] FIG. 4B shows another schematic illustrating an area-efficient readable and resettable configuration memory latch 450.”; the WLW (write) domain has input to the pull-down transistor 440-5 N5 via gate g-N5 via the s-node in the read latch circuit block 407).
Regarding claim 20, YAP teaches The process of claim 18, further comprising: configuring the pull-down network on a latching node of the read latch. (YAP, fig 4A/B, “[0084] Therefore, pull down network 304 is activated and BL 155 is pulled to 0 starting at time D7 (as shown in waveform 487 in FIG. 4D) until time D8. … [0087] Accordingly, pull-down network 304 is deactivated and BL 155 is pulled to 1 by weak pull up Rl 341.”; the network 304 performs a pull-down (and pull-up with network 306) function in the read latch circuit block 407).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825