DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on November 6th, 2025, have been carefully considered.
Claims 1, 4-5, 8-12, 17, 19-20, and 22, have been amended.
No claims have been added or canceled.
Claims 1-22 are currently pending in the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 11-14, and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. [US2004/0162942]. Lee teaches computer system embedding sequential buffers therein for improving the performance of a digital signal processing data access operation and method thereof.
Regarding claim 1 and 12, Lee teaches a method of managing access to a first memory via a second memory [Lee abstract “…The computer system comprises a DSP core, a data cache, first and second buffer modules, and an external memory…”], access to the first memory being at a first speed [Lee paragraph 0020, first 1-3 “…The external memory 220 includes separate and/or independent memory fields such as an input data field 222, a temporary data field 224, and an output data field 226…”] and the first memory being of a fixed size [Lee paragraph 0022, last lines “…One of the data registers 0, 1, 2, and 3 stores a data word (e.g., data in the unit of word)…”(Proves the first memory stored externally is addressed as fixed words)] and comprising a first plurality of data blocks [Lee paragraph 0022, middle lines “…While the sequential buffer may employ a multitude of data buffers, the sequential buffer 306 uses four data registers 0, 1, 2, and 3…”(Multiple words create a block)], access to the second memory being at a second speed [Lee figure 3, feature 306 (The buffer is on the SOC and thus faster than external memory.)], different from the first speed [Lee figure 3, feature 222 (The external memory is therefore inherently slower than the buffer memory on the SOC.)], and the second memory being of a fixed size [Lee paragraph 0022, last lines “…One of the data registers 0, 1, 2, and 3 stores a data word (e.g., data in the unit of word)…”] and comprising a second plurality of data blocks [Lee paragraph 0022, middle lines “…While the sequential buffer may employ a multitude of data buffers, the sequential buffer 306 uses four data registers 0, 1, 2, and 3…”(Multiple words create a block)], the method comprising:
performing automated copying of data from one or more of the data blocks in the first plurality of data blocks in the first memory to corresponding one or more of the data blocks in the second plurality of data blocks in the second memory sequentially [Lee paragraph 0027, middle lines “…The AUTO-FILL operation is conducted to stack data of the input data field 222 in the sequential buffer 306…” and paragraph 0021, most lines “…The address register 302 stores addresses for the external memory 220, which are set by the CPU core 212. The addresses are applied to the external memory 220 through an address bus AB to designate the input and output data fields therein. The increment unit 304 increments the external memory address by one bit to designate an internal address in the sequential buffer 306…”], the automated copying being performed when the second memory has available space [Lee paragraph 0027, middle lines “…when the sequential buffer 306 is empty due to data fetching by the DSP core 214…”], wherein the number of data blocks copied is according to a number of available blocks in the second memory [Lee paragraph 0027, middle lines “…when the sequential buffer 306 is empty due to data fetching by the DSP core 214…”(Empty reads on a number of available blocks since all the blocks are available.)];
receiving a command for reading from the second memory to a processor [Lee paragraph 0027, first lines “…the read operation in the DSP Core…”];
responsive to receiving the command for reading from the second memory [Lee paragraph 0027, first lines “…the read operation in the DSP Core…”], obtaining a pointer indicating an address of a data block in the second memory that contains data copied from the first memory and that is first available for access [Lee paragraph 0005, last lines “…operations for incrementing address pointer registers…” and paragraph 0021, most lines “…The address register 302 stores addresses for the external memory 220, which are set by the CPU core 212. The addresses are applied to the external memory 220 through an address bus AB to designate the input and output data fields therein. The increment unit 304 increments the external memory address by one bit to designate an internal address in the sequential buffer 306…”]; and
obtaining the data from the data block based on the pointer [Lee paragraph 0026, middle lines “…serially reads data from the input data field 222 of the external memory 220, if the sequential buffer 306 is empty, and then stacks the data in the data registers 0, 1, 2, and 3 of the sequential buffer 306.…”].
Regarding claims 2 and 13, as per claim 1, Lee teaches wherein the second speed is faster than the first speed [Lee figure 3, feature 306 (The buffer is on the SOC and thus faster than external memory.)].
Regarding claim 3, as per claim 1, Lee teaches the second memory is internal memory that is directly connected to one or more processors [Lee figure 3, feature 306 and 214 “DSP Core” and 212” CPU Core”] and the first memory is external memory not directly connected to the one or more processors [Lee figure 3, feature 222 “External Memory”].
Regarding claims 4 and 14, as per claim 1, Lee teaches autonomously performing automated copying comprises performing one or more iterations of operations [Lee paragraph 0027, middle lines “…The AUTO-FILL operation is conducted to stack data of the input data field 222 in the sequential buffer 306…”] comprising:
using a copy pointer indicative of an address of a next data block in the second memory that is available to receive data from the first memory [Lee paragraph 0021, most lines “…The address register 302 stores addresses for the external memory 220, which are set by the CPU core 212. The addresses are applied to the external memory 220 through an address bus AB to designate the input and output data fields therein. The increment unit 304 increments the external memory address by one bit to designate an internal address in the sequential buffer 306…” and paragraph 0024, last lines “…The multiplexer 320 transfers the data of the external memory 220 via a data bus DB to the data registers 0, 1, 2, and 3, which are addressed by the lower two bits of the address register 302…”];
copying data from one of the first plurality of data blocks in the first memory to the next data block in the second memory [Lee paragraph 0027, middle lines “…The AUTO-FILL operation is conducted to stack data of the input data field 222 in the sequential buffer 306 when the sequential buffer 306 is empty…”]; and incrementing a value of the copy pointer [Lee paragraph 0005, last lines “…operations for incrementing address pointer registers…”].
Regarding claims 11 and 20, as per claim 1, Lee teaches autonomously performing automated copying of one or more of the plurality of data blocks in the second memory to corresponding data blocks in the first memory [Lee paragraph 0027, last lines “….the AUTO-FLUSH operation is carried out to store the data of the sequential buffer 306 in the output data field 226 of the external memory 220…”];
receiving a command for writing data to the second memory [Lee paragraph 0027, middle lines “…AUTO-FLUSH…”];
responsive to receiving the command for writing to the second memory [Lee paragraph 0027, middle lines “…AUTO-FLUSH…”],
obtaining the pointer indicating an address of a data block in the second memory that is available to store new data [Lee paragraph 0022, last lines “…including a single valid bit 308 for informing whether it is available for a corresponding register to read data therefrom or to write data thereto…”]; and
writing the data as the new data in the data block based on the pointer [Lee paragraph 0027, last lines “….the AUTO-FLUSH operation is carried out to store the data of the sequential buffer 306 in the output data field 226 of the external memory 220…”].
Regarding claim 21, as per claim 12, Lee teaches the one or more processors is configured to maintain the pointer indicating an address of a data block in the internal memory that contains data copied from the external memory [Lee paragraph 0011, first lines “…an address buffer for storing an address of the external memory; an increment unit for increasing the address by one bit…”] and is available for access [Lee paragraph 0023, first lines “…The single valid bit 308 is set to "1" when data is written…”], a copy pointer indicating an address of a next data block in the internal memory that is available to receive data from the external memory [Lee paragraph 0023, middle lines “…The single valid bit 308 is set to "1" when data is written to the corresponding data register of the sequential buffer 306, and goes to "0" when the written data is stored in the output data field 226 of the external memory 220…”], and a release pointer indicating an address of a last data block in the internal memory that is available to receive data from the external memory [Lee paragraph 0023, last lines “…the valid bit 308 goes to "1" when data of the input data field 222 is changed in the data register of the sequential buffer 306 in response to a request from the DSP core 214, and to "0" when the data is read from the DSP core 214…”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US2004/0162942] in view of Milvert et al. [US6,601,015]. Lee teaches computer system embedding sequential buffers therein for improving the performance of a digital signal processing data access operation and method thereof. Milvert teaches embedded datalogger for an engine system
Regarding claim 22, as per claim 12, Lee fails to explicitly teach the plurality of data blocks in the internal memory are logically arranged in an order, wherein a last data block in the internal memory references a first data block in the internal memory such that incrementing the pointer indicating the last data block in the buffer results in the pointer indicating the first data block in the buffer.
However Milvert shows that it was well known in the art for buffers to be circular and loop back on themselves thus being called a circular buffer as can be seen in column 8, lines 10-20 which states “…Once activated in stage 126, circular buffer 35 continuously stores the selected engine parameters in a segment of contiguous memory locations in the relative address range BASE through TOP. Buffer address pointer PTR is incremented to consecutively store the one or more engine parameters specified in stage 122 in corresponding sets of one or more memory locations within buffer 35; where these sets are stored at the rate selected in stage 122. Once pointer PTR reaches the last address, PTR=TOP, it loops back to the first address, PTR=BASE, for the next memory storage operation…”].
Lee and Milvert are analogous art in that they both deal with efficiently caching data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee’s automatic copying with Milvert’s teachings of a circular buffer for the benefit of being able to loop back on it’s self and thus require less storage area which reduces cost.
Allowable Subject Matter
Claims 5-10 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot in view of new grounds of rejection.
The examiner has determined that even though the prior art uses different terminology, the prior art performs the same functions as the claim limitations as they are currently claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139