Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is responsive to the Amendment filed on 6/29/2026.
In the Instant Amendment, Claim(s) 1, 6 and 17 has/have been amended; Claim(s) 1 and 17 is/are independent claims. Claims 1-20 have been examined and are pending in this application.
Response to Arguments
The rejections of claims 17-20 are withdrawn because of the amendment and the persuasive argument in the remark (page 8).
Applicant's arguments filed 6/29/2026 have been fully considered but they are not persuasive.
Regarding claim 1, the Applicant is arguing in the remarks (pages 8-11) that Jang/Oh in the combination fails to teach “the first storage diode is configured to temporarily store the photocharges received from the first detection node and transfer the stored photocharges to the first floating diffusion region”.
The Examiner respectfully disagrees with the Applicant. The Examiner respectfully submits that Jang in the combination does teach the first storage diode (C2_A or C1_A) is configured to temporarily store the photocharges received from the first detection node and transfer the stored photocharges to the first floating diffusion region (Fig. 3; paras. 0068-0072; does C2_A or C1_A temporarily store the photocharges received from the first detection node of PD 100? Yes, it does; does C2_A or C1_A transfer stored charges to FD_A to be transferred out via FD_A to DX_A and SX_A? Yes, it does; Thus, this feature is taught). The claim fails to recite any specific structure different than Jang so as to have “the first storage diode is configured to temporarily store the photocharges received from the first detection node and transfer the stored photocharges to the first floating diffusion region”. In Jang, the photocharges received from the first detection node of PD 100 is temporarily stored into storage diodes C2_A and/or C1_A and also FD_A. The charges within C2_A and/or C1_A pass through or transferred to FD_A to be output via FD_A, DX_A and then SX_A to the vertical signal line SL_A.
Moreover, Oh, in an alternative, also can be combined to expressly teach the first storage diode (storage diode SD_A) is configured to temporarily store the photocharges received from the first detection node (photodiode 1606) and transfer the stored photocharges to the first floating diffusion region (FD_A) (Fig. 16; para. 0032: “Each pixel tap also includes a storage diode 204a, 204b configured to receive and store charge that is accumulated at the corresponding photogate 202a, 202b during the integration period. The storage diodes 204a, 204b (SD_A and SD_B) may comprise pinned diodes, as an example. The use of storage diodes as opposed to storage gates may provide various advantages. For example, while a storage gate offers wider voltage swing, the oxide interface of the storage gate also may contribute significant dark current, and thereby increase the noise floor. In contrast, a pinned diode may contribute less dark current, and thereby extend a dynamic range of the pixel tap on a lower signal end. Further, the use of a pinned diode does not require pulsing, as with a storage gate, and thus may reduce power consumption compared to the use of a storage gate”; paras. 0033-0035, 0052).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Jang has a pixel configuration of PD 100, RX_A, TX_A, FDX_A, C2_A and DX_A while Oh also has a similar pixel configuration with corresponding PD, DG, TG_A, FD_A, DCG_A, DCGcap_A and SF_A. Oh also has extra global transfer transistor SG_A and charge storage diode SD_A which can be incorporated into Jang. It is to utilize less dark current charge storage diode to enable a global shutter configuration while improving image signals with reduced power consumption yielding a predicted result.
For the reasons above, the Examiner respectfully submits that the combination of Jang and Hashimoto or/and Oh does teach the features as claimed in claim 1 and also claim 17 for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 20210368122 A1) in view of Hashimoto et al (US 20050248675 A1).
Regarding claim 1, Jang teaches An image sensing device (Figs. 1-2) comprising:
a pixel array including pixels (para. 0048; “a 2×2 matrix including pixels P23, P24, P33 and P34”), each pixel structured to respond to incident light to produce photocharges indicative of detected incident light, wherein the pixel array includes:
a first detection structure (first tap TA1223) configured to include a first control node receiving a first demodulation control signal and a first detection node disposed to surround the first control node (Figs. 3-4; para. 0048: “a first tap TA1223 may be disposed in the center of a 2×2 pixel matrix including pixels P12, P13, P22 and P23”; para. 0063: “The first control node CN1223 and the first detection nodes DN12a and DN23a may constitute a first tap (or first demodulation node)”);
a second detection structure (second tap TB2334) configured to include a second control node receiving a second demodulation control signal and a second detection node disposed to surround the second control node (para. 0048: “a second tap TB2334 may be disposed in the center of a 2×2 matrix including pixels P23, P24, P33 and P34”; para. 0063: “the second control node CN2334 and the second detection nodes DN23b and DN34b may constitute a second tap (or second demodulation node”);
a first storage diode electrically connected to the first detection node (Fig. 3; para. 0075; junction capacitor/storage diode C1_A or C2_A); and
a second storage diode electrically connected to the second detection node (Fig. 3; para. 0075; junction capacitor/storage diode C1_B or C2_B),
a first pixel transistor region configured to be disposed between adjacent first detection structures (Figs. 2, 17, 19; paras. 0212, 0215; FIG. 19, a pixel transistor region 1900 may correspond to a part of the first or second pixel transistor region (for example, PA23a-1 or PA23b-1) illustrated in FIGS. 17; pixel transistor region 1900 of each pixel within 2x2 pixels [P13, P14, P23, P24] is disposed at a vertex located at the center of the 2x2 pixels; it is obvious that four of pixel transistor region 1900 can be configured to be shared among the adjacent four pixels),
wherein the first detection structure (first tap TA1223) and the second detection structure (second tap TB2334) are disposed at two opposing vertices of a certain pixel (P23), respectively, to face each other in a diagonal direction within the pixel (Fig. 2),
the first pixel transistor region is disposed at one of two opposing vertices of the certain pixel in the other diagonal direction within the certain pixel (Figs. 2, 17, 19; paras. 0212, 0215; FIG. 19, a pixel transistor region 1900 may correspond to a part of the first or second pixel transistor region (for example, PA23a-1 or PA23b-1) illustrated in FIGS. 17; pixel transistor region 1900 of each pixel within 2x2 pixels [P13, P14, P23, P24] is disposed at a vertex located at the center of the 2x2 pixels),
the first pixel transistor region (as presented above) includes a first floating diffusion region (para. 0215: “a first terminal of the floating diffusion transistor may be coupled to a first capacitor (C1_A or C1_B of FIG. 3)… the terminal 1960 may indicate the floating diffusion node itself”; the structure in Fig. 19 shows that pixel transistor region 1900 of each pixel within 2x2 pixels [P13, P14, P23, P24] includes FD 1960 and the circuit in figure 3 shows that pixel transistor region 200 includes FD_A),
the first storage diode (C2_A or C1_A) is electrically connected between the first detection structure (Figs. 3-4; first tap TA1223 [CN1223, DN23a, DN23b]) and the first floating diffusion region (FD_A/1960) (the circuit in figure 3 shows that there is an electrical path between node FD_A to node DN23a of first tap TA1223 and the first storage diode [C2_A or C1_A] is electrically connected to the electrical path between node FD_A to node DN23a of first tap TA122; storage diode C2_A is electrically connected via transistor FDX_A or storage diode C1_A is electrically connected directly), and the first storage diode (C2_A or C1_A) is configured to temporarily store the photocharges received from the first detection node and transfer the stored photocharges to the first floating diffusion region (Fig. 3; paras. 0068-0072; does C2_A or C1_A temporarily store the photocharges received from the first detection node of PD 100? Yes, it does; does C2_A or C1_A transfer stored charges to FD_A to be transferred out via FD_A to DX_A and SX_A? Yes, it does; Thus, this feature is taught),
but fails to teach
the first pixel transistor region is disposed at one of two opposing vertices of the certain pixel in the other diagonal direction within the certain pixel, the first pixel transistor region is shared by four adjacent pixels including the certain pixel.
However, in the same field of endeavor Hashimoto teaches
the first pixel transistor region (12) is disposed at one (bottom right vertex) of two opposing vertices of the certain pixel (top left pixel within 2x2 pixels) in the other diagonal direction within the certain pixel (Figs. 23-25, 30), the first pixel transistor region is shared by four adjacent pixels including the certain pixel (Figs. 23-25, 30; paras. 0182-0189; pixel transistor region 12 including reset, select and amplification transistors is located at a vertex located at the center of 2x2 pixels and is shared by the four pixels).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Hashimoto in Jang to have the first pixel transistor region is disposed at one of two opposing vertices of the certain pixel in the other diagonal direction within the certain pixel, the first pixel transistor region is shared by four adjacent pixels including the certain pixel for configurating adjacent pixels to share a readout circuit so that pixel components can be reduced allowing more space for other components yielding a predicted result.
Regarding claim 2, the combination of Jang and Hashimoto teaches everything as claimed in claim 1. In addition, Jang teaches wherein:
the first detection node is connected to the first storage diode through a first storage transistor (TX_A); and the second detection node is connected to the second storage diode through a second storage transistor (TX_B) (Fig. 3; paras. 0068-0072).
Regarding claim 3, the combination of Jang and Hashimoto teaches everything as claimed in claim 1. In addition, Jang teaches wherein:
the first storage diode and the second storage diode are disposed to face each other in the other diagonal direction within the certain pixel (P23) (Figs. 17-19; paras. 0212, 0215).
Regarding claim 4, the combination of Jang and Hashimoto teaches everything as claimed in claim 1. In addition, Jang teaches wherein the pixel array includes a first pixel group including four adjacent pixels including the certain pixel, and wherein the first detection structure and additional first detection structures are disposed at vertices of the first pixel group, and the second detection structure is disposed at a center of the first pixel group (Figs. 4, 2; para. 0048).
Regarding claim 5, the combination of Jang and Hashimoto teaches everything as claimed in claim 1. In addition, Jang teaches wherein:
the first control node and the second control node are configured to generate a current in a substrate; and each of the first detection node and the second detection node is configured to capture photocharges carried by the current (Figs. 2-3; para. 0093).
Regarding claim 6, the combination of Jang and Hashimoto teaches everything as claimed in claim 5. In addition, Jang teaches wherein:
the second storage diode is configured to temporarily store the photocharges captured by the second detection node (Fig. 3; paras. 0068-0072).
Regarding claim 7, the combination of Jang and Hashimoto teaches everything as claimed in claim 1. In addition, Jang teaches wherein
the first pixel transistor region configured to includes a plurality of transistors for processing photocharges captured by the first detection node (Figs. 2, 17, 19; paras. 0212, 0215; FIG. 19, a pixel transistor region 1900 may correspond to a part of the first or second pixel transistor region (for example, PA23a-1 or PA23b-1) illustrated in FIGS. 17; pixel transistor region 1900 of each pixel within 2x2 pixels [P13, P14, P23, P24] is disposed at a first vertex located at the center of the 2x2 pixels [P13, P14, P23, P24]),
wherein the pixel array further includes a second pixel transistor region configured to be disposed between adjacent second detection structures and be shared by four adjacent pixels including the certain pixel (P23) (Figs. 2, 17, 19; paras. 0212, 0215; FIG. 19, a pixel transistor region 1900 may correspond to a part of the first or second pixel transistor region (for example, PA23a-1 or PA23b-1) illustrated in FIGS. 17; pixel transistor region 1900 of each pixel within 2x2 pixels [P22, P23, P32, P33] is disposed at a second vertex located at the center of the 2x2 pixels [P22, P23, P32, P33]), and
the second pixel transistor region includes a plurality of transistors (Fig. 19) for processing photocharges captured by the second detection node (Figs. 17, 19).
Regarding claim 8, the combination of Jang and Hashimoto teaches everything as claimed in claim 7. In addition, Jang teaches wherein the first pixel transistor region (the “first vertex located at the center of the 2x2 pixels [P13, P14, P23, P24]”) and the second pixel transistor region (the “second vertex located at the center of the 2x2 pixels [P22, P23, P32, P33]”) are alternately disposed in the pixel array in the diagonal direction (as presented in claim 7).
Regarding claim 9, the combination of Jang and Hashimoto teaches everything as claimed in claim 8. In addition, Jang teaches wherein:
the first pixel transistor region and the second pixel transistor region are disposed at different vertices from the vertices where the first detection structure and the second detection structure are disposed (as presented in claim 8; the first and second vertexes).
Regarding claim 10, the combination of Jang and Hashimoto teaches everything as claimed in claim 8. In addition, Jang teaches wherein:
the first pixel transistor region includes a first floating diffusion region (FD 1960) (Figs. 17, 19; paras. 0213, 0215); and
the first floating diffusion region is disposed at a center of a second pixel group (P23, P24, P13, P14) including four adjacent pixels including the certain pixel (P23), the first floating diffusion region (FD) configured to process photocharges captured by the first detection node (Figs. 2-3, 17, 19).
Regarding claim 11, the combination of Jang and Hashimoto teaches everything as claimed in claim 10. In addition, Jang teaches wherein:
the first floating diffusion region is electrically connected to the first storage diode through a first transfer transistor (Fig. 3; para. 0075).
Regarding claim 12, the combination of Jang and Hashimoto teaches everything as claimed in claim 8. In addition, Jang teaches wherein:
the second pixel transistor region (PA23b-1/1900) includes a second floating diffusion region (FD 1960) (Figs. 17, 19; paras. 0213, 0215); and
the second floating diffusion region is disposed at a center of a third pixel group (P22, P23, P32, P33) including four adjacent pixels including the certain pixel (P23), the second floating diffusion region configured to process photocharges captured by the second detection node (Figs. 2-3, 17, 19).
Regarding claim 13, the combination of Jang and Hashimoto teaches everything as claimed in claim 12. In addition, Jang teaches wherein:
the second floating diffusion region is electrically connected to the second storage diode through a second transfer transistor (Fig. 3; para. 0075).
Regarding claim 14, the combination of Jang and Hashimoto teaches everything as claimed in claim 1. In addition, Jang teaches wherein the first detection structure and the second detection structure are alternately disposed in the pixel array in the diagonal direction (Fig. 2; paras. 0050-0053).
Regarding claim 15, the combination of Jang and Hashimoto teaches everything as claimed in claim 14. In addition, Jang teaches wherein:
a vertex where the first detection structure is disposed and a vertex where the first detection structure or the second detection structure is not disposed are alternately disposed in a row direction of the pixel array; or a vertex where the second detection structure is disposed and a vertex where the first detection structure or the second detection structure is not disposed are alternately disposed in the row direction (Fig. 2; paras. 0050-0053).
Regarding claim 16, the combination of Jang and Hashimoto teaches everything as claimed in claim 14. In addition, Jang teaches wherein:
a vertex where the first detection structure is disposed and a vertex where the first detection structure or the second detection structure is not disposed are alternately disposed in a column direction of the pixel array; or a vertex where the second detection structure is disposed and a vertex where the first detection structure or the second detection structure is not disposed are alternately disposed in the column direction (Fig. 2; paras. 0050-0053).
Regarding claim 17, Jang teaches An image sensing device (Figs. 1-2) comprising:
a pixel (P23) structured to convert incident light to a pixel signal (Figs. 2-3);
a first detection node and a second detection node disposed to be two opposite sides of the pixel and spaced from each other in a first direction within the pixel (Fig. 2; para. 0063: “The first control node CN1223 and the first detection nodes DN12a and DN23a may constitute a first tap (or first demodulation node)”; para. 0063: “the second control node CN2334 and the second detection nodes DN23b and DN34b may constitute a second tap (or second demodulation node”);
a first storage diode electrically connected to the first detection node (Fig. 3; para. 0075; junction capacitor/storage diode C1_A or C2_A);
a transistor region configured to include transistors for processing photocharges (Figs. 2, 17, 19; paras. 0212, 0215; FIG. 19, a pixel transistor region 1900 may correspond to a part of the first or second pixel transistor region (for example, PA23a-1 or PA23b-1) illustrated in FIGS. 17; pixel transistor region 1900 of each pixel within 2x2 pixels [P13, P14, P23, P24] is disposed at a vertex located at the center of the 2x2 pixels) and
a second storage diode electrically connected to the second detection node (Fig. 3; para. 0075; junction capacitor/storage diode C1_B or C2_B), wherein each of the first detection node and the second detection node is configured to capture photocharges carried by a current generated in a substrate of the pixel (Fig. 3; paras. 0070-0078); and
each of the first storage diode and the second storage diode is configured to temporarily store the photocharges (Fig. 3; paras. 0070-0078),
the transistor region (as presented above) includes a floating diffusion region (para. 0215: “a first terminal of the floating diffusion transistor may be coupled to a first capacitor (C1_A or C1_B of FIG. 3)… the terminal 1960 may indicate the floating diffusion node itself”; the structure in Fig. 19 shows that pixel transistor region 1900 of each pixel within 2x2 pixels [P13, P14, P23, P24] includes FD 1960 and the circuit in figure 3 shows that pixel transistor region 200 includes FD_A),
the first storage diode (C2_A or C1_A) is electrically connected between the first detection node (Figs. 3-4; first tap TA1223 [CN1223, DN23a, DN23b]) and the first floating diffusion region (FD_A/1960) (the circuit in figure 3 shows that there is an electrical path between node FD_A to node DN23a of first tap TA1223 and the first storage diode [C2_A or C1_A] is electrically connected to the electrical path between node FD_A to node DN23a of first tap TA122), and the first storage diode is configured to temporarily store the photocharges received from the first detection node and transfer the stored photocharges to the floating diffusion region (Fig. 3; paras. 0068-0072; does C2_A or C1_A temporarily store the photocharges received from the first detection node of PD 100? Yes, it does; does C2_A or C1_A transfer stored charges to FD_A to be transferred out via FD_A to DX_A and SX_A? Yes, it does; Thus, this feature is taught),
but fails to teach
a transistor region configured to include transistors for processing photocharges and shared by four adjacent pixels that include the pixel.
However, in the same field of endeavor Hashimoto teaches
a transistor region configured to include transistors for processing photocharges and shared by four adjacent pixels that include the pixel (Figs. 23-25, 30; paras. 0182-0189; pixel transistor region 12 including reset, select and amplification transistors is located at a vertex located at the center of 2x2 pixels and is shared by the four pixels).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Hashimoto in Jang to have a transistor region configured to include transistors for processing photocharges and shared by four adjacent pixels that include the pixel for configurating adjacent pixels to share a readout circuit so that pixel components can be reduced allowing more space for other components yielding a predicted result.
Regarding claim 18, the combination of Jang and Hashimoto teaches everything as claimed in claim 17. In addition, Jang teaches further comprising:
a pixel array configured to include pixels that are arranged in rows and columns of a matrix (Figs. 1-2);
a control node configured to generate the current in the substrate (Figs. 2-3; paras. 0063-0068; first and second control nodes CN1223 and CN2334); and
wherein the control node and the transistor region are alternately disposed in a row or column direction of the pixel array (Figs. 2, 17, 19; paras. 0211-0213; as presented in claim 8).
Regarding claim 19, the combination of Jang and Hashimoto teaches everything as claimed in claim 18. In addition, Jang teaches wherein:
the control node and additional control nodes are disposed at each of vertices of the pixel, and are arranged in the pixel array in the first direction or a second direction perpendicular to the first direction (Figs. 2, 17, 19; paras. 0211-0213).
Regarding claim 20, the combination of Jang and Hashimoto teaches everything as claimed in claim 18. In addition, Jang teaches wherein:
the transistor region and additional transistor regions are disposed at each of vertices of the pixel, and are arranged in the pixel array in the first direction or a second direction perpendicular to the first direction (Figs. 2, 17-20; paras. 0211-0213; as presented in claims 7-8).
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as presented above under the combination of Jang and Hashimoto and in the alternative, as obvious further over Oh (US 20210360177 A1).
The combination of Jang and Hashimoto teaches everything as claimed in claims 1-20. In the alternative, to expressly teach the limitation “the first storage diode is electrically connected between the first detection structure and the first floating diffusion region” and “the first storage diode is configured to temporarily store the photocharges received from the first detection node and transfer the stored photocharges to the first floating diffusion region” in claims 1 and 17.
In the same field of endeavor Lee teaches
the first storage diode (storage diode SD_A) is electrically connected between the first detection structure (photodiode 1606) and the first floating diffusion region (FD_A) and the first storage diode (storage diode SD_A) is configured to temporarily store the photocharges received from the first detection node (photodiode 1606) and transfer the stored photocharges to the first floating diffusion region (FD_A) (Fig. 16; para. 0032: “Each pixel tap also includes a storage diode 204a, 204b configured to receive and store charge that is accumulated at the corresponding photogate 202a, 202b during the integration period. The storage diodes 204a, 204b (SD_A and SD_B) may comprise pinned diodes, as an example. The use of storage diodes as opposed to storage gates may provide various advantages. For example, while a storage gate offers wider voltage swing, the oxide interface of the storage gate also may contribute significant dark current, and thereby increase the noise floor. In contrast, a pinned diode may contribute less dark current, and thereby extend a dynamic range of the pixel tap on a lower signal end. Further, the use of a pinned diode does not require pulsing, as with a storage gate, and thus may reduce power consumption compared to the use of a storage gate”; paras. 0033-0035, 0052).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Oh in the combination to have the first storage diode is electrically connected between the first detection structure and the first floating diffusion region for utilizing less dark current charge storage diode to enable a global shutter configuration while improving image signals with reduced power consumption yielding a predicted result.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Quan Pham whose telephone number is (571)272-4438. The examiner can normally be reached Mon-Fri 9am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571) 272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Quan Pham/Primary Examiner, Art Unit 2637
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