Prosecution Insights
Last updated: October 04, 2026
Application No. 18/408,456

ULTRA-STABLE INTEGRATED LASER ON SILICON

Non-Final OA §102§103
Filed
Jan 09, 2024
Priority
Jan 09, 2023 — provisional 63/437,853
Examiner
FORDE, DELMA ROSA
Art Unit
Tech Center
Assignee
Government of the United States of America, As Represented By the Secretary of Commerce
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
410 granted / 535 resolved
+16.6% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
12 currently pending
Career history
541
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
57.4%
+17.4% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 535 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The references cited in the Information Disclosure Statement (IDS) submitted on January 09, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered and accepted by the examiner. Drawings The drawing submitted on January 09, 2024, has been considered and accepted by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 – 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guo et al. “Chip-Based Laser with 1 Hertz Integrated Linewidth”. The applied reference has a common inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. PNG media_image1.png 432 656 media_image1.png Greyscale PNG media_image2.png 502 658 media_image2.png Greyscale Regarding claim 1, Guo disclose an integrated chip-scale laser assembly comprising: a chip-scale laser (see Figures 1 and 3a, character “Self-injection lock”); and a compact reference optical cavity optically coupled (see Figures 1 and 3a, character µ-FP cavity) to an output of the chip-scale laser (see Figures 1 and 3a, character “Self-injection lock”). Regarding claim 2, Guo disclose the compact reference optical cavity is a vacuum-gap Fabry-Perot (FP) reference cavity (see Figures 1 and 3a, character µ-FP cavity, Abstract, Introduction, page 2, left column,1st full paragraph, page 3, left column, 3rd full paragraph, Discussion page 6, left column, 1st full paragraph). Regarding claim 3, Guo disclose the chip-scale laser is an integrated self-injection locked laser (see Figures 1 and 3a, character “Self-injection lock”, Abstract, Introduction, page 2, 1st full paragraph, page 3, 2nd full paragraph, Results page 3, right column 2nd full paragraph, Discussion page 6, left column 1st paragraph). Regarding claim 4, Guo disclose the chip-scale laser is locked with the Pound-Drever-Hall (PDH) technique to the compact reference optical cavity (see Figure 1, character “PDH lock”, Introduction page 2, left column, 1st full paragraph, page 3, 2nd full paragraph, Results page 3, right column 1st full paragraph. Regarding claim 5, Guo disclose coupling to the Fabry-Perot cavity from a planar waveguide circuit via bonding is achieved with at least one of metasurfaces or grating couplers (see Discussion, page 6, left column, 1st full paragraph). Regarding claim 6, Guo disclose the cavity is edge-coupled to a photonic circuit with a gradient index lens (see Discussion, page 6, left column, 1st full paragraph). Claims 1 – 2 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Notcutt et al. (US 2024/0142764). PNG media_image3.png 218 286 media_image3.png Greyscale PNG media_image4.png 282 396 media_image4.png Greyscale Regarding claim 1, Notcutt disclose an integrated chip-scale laser assembly comprising: a chip-scale laser (see Figure 2, character 115); and a compact reference optical cavity optically (see Figure 1A and 1B, character 10, Abstract, paragraphs [0014, 0025 and 0033] and the reference called “optical cavity”) coupled to an output of the chip-scale laser (see Figure 2, character 115). Regarding claim 2, Notcutt disclose the compact reference optical cavity is a vacuum-gap Fabry-Perot (FP) reference cavity (see Figure 1A and 1B, character 10, Abstract, paragraphs [0014, 0025 and 0033]). Regarding claim 4, Notcutt disclose the chip-scale laser is locked with the Pound-Drever-Hall (PDH) technique to the compact reference optical cavity (see paragraph [0044]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 4 and 6 are rejected under 35 U.S.C. 103 as being obvious over Notcutt et al. (US 2024/0142764) in view of Guo et al. “Chip-Based Laser with 1 Hertz Integrated Linewidth”. The applied reference has a common inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). Regarding claims 3, 5 and 6, Notcutt discloses the claimed invention except for the chip-scale laser is an integrated self-injection locked laser wherein coupling to the Fabry-Perot cavity from a planar waveguide circuit via bonding is achieved with at least one of metasurfaces or grating couplers and the cavity is edge-coupled to a photonic circuit with a gradient index lens. Guo teaches an integrated self-injection locked laser a planar waveguide circuit via bonding is achieved with at least one of metasurfaces or grating couplers and the cavity is edge-coupled to a photonic circuit with a gradient index lens. However, it is well known in the art to apply and/or modify the integrated self-injection locked laser a planar waveguide circuit via bonding is achieved with at least one of metasurfaces or grating couplers and the cavity is edge-coupled to a photonic circuit with a gradient index lens as discloses by 2 in (see Figure 1, 3a Abstract, Introduction, page 2, 1st full paragraph, page 3, 2nd full paragraph, Results page 3, right column 2nd full paragraph, Discussion page 6, left column 1st paragraph). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention was to apply and/or modify the integrated self-injection locked laser a planar waveguide circuit via bonding is achieved with at least one of metasurfaces or grating couplers and the cavity is edge-coupled to a photonic circuit with a gradient index lens as suggested to the device of Notcutt, the integrated self-injection locked laser is a compact photonic integrated circuit (PIC) design that uses self-injection locking to achieve ultra-low frequency noise and single-frequency operation without external master oscillators. In this configuration, the laser’s own output is fed back into its cavity to stabilize its frequency, enabling sub-Hz fundamental linewidths and sub-kHz integral linewidths. To further enhance integration, coupling to the µ-FP cavity from a planar waveguide circuit via links could be achieved using metasurfaces and grating couplers, similar to those successfully employed in atomic systems. Alternatively, the cavity could be coupled to the photonic circuit using a graded-index lens. Combined with photonic integration, this opens the way to a compact, integrated, cavity-stabilized hybrid laser. This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Delma R. Forde whose telephone number is (571)272-1940. The examiner can normally be reached M - TH 7:00 AM - 4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun O Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Delma R Forde/Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
Read full office action

Prosecution Timeline

Jan 09, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
91%
With Interview (+14.8%)
2y 9m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 535 resolved cases by this examiner. Grant probability derived from career allowance rate.

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