Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The modified drawings were received on 1/28/2026. These drawings are accepted.
Specification
The modified specification were received on 1/28/2026. The Specification is accepted.
Claim Objections
Claims 3, 4, 5 objected to because of the following informalities:
Claim 3, line 10, “the regulating point” should be – the preset regulating point—
Claim 4, line 5, “a preset regulating point” should be – the preset regulating point--
Claim 5, line 2, “the regulating point” should be – the preset regulating point on the starting module—
Claim 6, line 2, “a gate of a first NMOS transistor” should be—the gate of the first NMOA transistor—
Claim 6, line 2-3, “a sampling voltage—should be – the sampling voltage--
Appropriate correction is required.
Response to Arguments
Applicant’s arguments, see page 1 and page 2, filed 1/28/2026, with respect to the rejection(s) of claim(s) 1 under ( CN110703841) have been fully considered and are persuasive. Therefore, the 102 rejection has been withdrawn. However, upon further consideration, 112(b) rejection has been made with regarding to claims 1, 3-8.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “transient high-frequency” in claim 1, line 15 and line 17 is a relative term which renders the claim indefinite. The term “transient high-frequency” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purpose, “transient high-frequency is interpreted as transient frequency.
Claim 1 recites the limitation "the sampling point" in line 9. There is insufficient antecedent basis for this limitation in the claim. It is unclear “the sampling point” is refers to “preset sampling point “recited at claim 1, line 3 or not. For examination purpose, “the sampling point” is interpretated as “a sampling point,”
Claims 3-8 are rejected because they depend on claim 1.
Allowable Subject Matter
Claims 1, 3-8 would be allowable pending the Applicant overcome the 112(b) rejection above.
Regarding Claim 1, WU, SHI-MING et al. (CN110703841A). discloses an adaptive overshoot-voltage suppression circuit (e.g. and corresponding transistor MSN1 and capacitor C samples a voltage at node VSTN)(fig.2), comprising an overshoot-voltage suppression unit (e.g. and corresponding transistor MSN1 and capacitor C samples a voltage at node VSTN)(fig.2) and a voltage-to-current conversion unit (e.g. transistor MSN2 .with combined PMOS current mirror transistors MP3 and MP4)(fig.2), wherein an input end of the overshoot-voltage suppression unit (e.g. end of capacitor C)(fig.2) is connected to a preset sampling point on a to-be-measured reference circuit (e.g. figure 2 sampling point VSTN), an output end of the overshoot-voltage suppression unit (e.g. connection at the gate of transistor MSN2)(fig.2) is connected to an input end of the voltage-to-current conversion unit (e.g. connection at the gate of transistor MSN2)(fig.2), and an output end of the voltage-to-current conversion unit is connected to a preset regulating point on the to-be-measured reference circuit (e.g. drains of the MP3 and MP4 current mirror at nodes Vin or Vip)(fig.2); wherein the overshoot-voltage suppression unit comprises a capacitor (e.g. capacitor C1)(fig.2), a first NMOS transistor (e.g. transistor MSN1)(fig.2), and a second NMOS transistor (e.g. transistor MSN2)(fig.2).
and in a starting process of the to-be-measured reference circuit (e.g. prior art title is “Starting circuit of band-gap reference source…and starting method”, thus the prior art relates to a starting process)(fig.2), the overshoot-voltage suppression unit generates a transient high-frequency inducted voltage based on a sampling voltage obtained from the to-be-measured reference circuit (e.g. transistor MSN1 and capacitor C respond to the quickly rising voltage at VSTN and generate a corresponding high-frequency voltage signal, such as voltage VSTB)(fig.2), the transient high-frequency inducted voltage is converted into a corresponding pull-up current through the voltage-to-current conversion unit (e.g. the voltage VSTB at the gate of MSN2 controls the current mirror MP3/MP4, and current I is the corresponding current related to VSTB)(fig.2), and the pull-up current is injected into the to-be-measured reference circuit, and is superposed with a pull-down starting current of the to-be-measured reference circuit, to reduce a nonlinear starting current at a starting moment of the to-be-measured reference circuit (e.g. Injected current such as current I counteracts the primary starting current. The prior art states in the third paragraph of the summary of the invention section “the starting band gap reference source current of the feedback output module is continuously increased, entering into the stable state of the large current, can be more stable and reliable”. This is functionally the same as the claimed “reducing a nonlinear starting current to prevent overshoot”).
However, the prior art of record does not fairly disclose, teach or suggest “an end of the capacitor is connected to the sampling point and a gate of the first NMOS transistor, the other end of the capacitor is connected to a drain of the first NMOS transistor and a drain of the second NMOS transistor, a gate of the second NMOS transistor is connected to an external enable circuit, and a source of the first NMOS transistor and a source of the second NMOS transistor are connected to a common ground end voltage.”
Regard to claims 3-8, they depend on claim 1
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US9407149B2) teaches about A buck converting controller, adapted to control a DC-DC buck converting circuit to convert an input voltage into an output voltage,
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