DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokomitsu et al. (USPN 7,459,895).
Examiner’s Markup of Fig. 10 of Tokumitsu et al.
PNG
media_image1.png
532
752
media_image1.png
Greyscale
With respect to claim 1, Tokumitsu et al. discloses, in Figs 1, 2 and 10, a power supply regulation system (Fig. 10, see Examiner’s Markup above,, wherein Fig. 10 is an example of the power supply system that uses the error amplifier 1 of either one of the circuits as shown in Fig. 1 and 2) comprising:
a low dropout regulator (Fig. 1), comprising an error amplification stage (1/”1st amplifier”) and a power output stage (“3rd amplifier” alone or “2nd amplifier” with “3rd amplifier”); and
a power supply suppression circuit (note Applicant double includes elements from the power supply suppression circuit, compensation unit, and amplification unit within the error amplifier stage and/or power output stage, see page 5 line 30-34 of the instant specification which defines the error amplification stage and power output stage. The above cited portion states:
“a first PMOS transistor PM20, a second PMOS transistor PM21, a third PMOS transistor PM22, a fourth PMOS transistor PM23, a fifth PMOS transistor PM24, a first NMOS transistor NM21, a second NMOS transistor NM22, a third NMOS transistor NM23, and a fourth NMOS transistor NM24 together constitute the error amplification stage of the low dropout regulator. A sixth PMOS transistor PM25, a first capacitor C20, a second capacitor C21, and a first resistor R21 together constitute the power output stage of the low dropout regulator.”
Furthermore, the compensation unit is defined as “the compensation unit 106 is implemented by using the fifth PMOS transistor PM24” in lines 16-17 of page 6 of the instant specification. Thus, it can be seen the compensation unit is double included within the error amplifier stage.
Moreover, the amplification unit is defined as “the amplification unit 107 includes the fourth NMOS transistor NM24 and the fifth PMOS transistor PM24 of the compensation unit 106” in lines 22-23 of page 6 of the instant specification. Thus, it can be seen the amplification unit double includes both the “error amplifier stage” and the “compensation unit”. Therefore, Examiner will interpret and double include similar portions of the error amplification stage, compensation unit, sampling unit and amplification unit. Thus, Tokumitsu’s power supply suppression circuit is the first amplifier 1 with Ccup, Cfb, Rb1, and Rb2), comprising a sampling unit (Ccup, Rfb1, Rfb2 and Cfb of Fig. 10 or Ccup and R1 of Fig. 2 with Rfb1, Rfb2 and Cfb of Fig. 10), a compensation unit (one of N3 and N4 of Tokumitsu which are connected in essentially the same manner as PM24 of Applicant’s instant invention, except that it are NMOS), and an amplification unit (one of P3 and P4 with one of N3 and N4 which are connected in essentially the same manner as NM24 and PM24 of Applicant’s invention, except they are complementary conduction types), wherein the sampling unit is connected to the compensation unit, and the compensation unit is connected to the amplification unit (the circuits are connected and operative as claimed);
a first AC signal within a target frequency band is obtained, by the sampling unit, from either an output node of the low dropout regulator or a ground node connected to the low dropout regulator, via an RC network (an AC signal is obtained by Ccup and R1 of Fig. 2 at the output Vout of the voltage regulator, the AC signal set according to the value of Ccup and R1, see equations 7 and 9 of Col. 5), and is outputted to the compensation unit (output to the gate of N4),
wherein the compensation unit is configured to generate, based on the first AC signal and a second AC signal obtained from the error amplification stage of the low dropout regulator, a third AC signal in phase or out of phase with the power supply voltage, and to output the third AC signal to the amplification unit, such that, within the target frequency band, an AC voltage at an input end of the power output stage of the low dropout regulator closely follows AC variation of a power supply voltage of the low dropout regulator (the first AC and the second AC signal obtained from the amplification stage gm2/Azcp, see equation 8 of Col. 5 are set to cancel out AC variation of the power supply voltage of the low dropout regulator, i.e., increase PSRR, see Col. 6 line 64 to Col. 7 line 6. Furthermore, the circuitry is connected in essentially the same fashion as Applicant’s claimed circuitry and therefore operates in a similar fashion. Complementary CMOS amplifiers will operate in essentially the same fashion).
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guiraud et al. (USPN 11,940,859).
With respect to claim 1, Tokumitsu et al. discloses, in Fig. 6, a power supply regulation system (Fig. 6) comprising:
a low dropout regulator (Fig. 6), comprising an error amplification stage (2) and a power output stage (4 with 6); and
a power supply suppression circuit (note Applicant double includes elements from the power supply suppression circuit, compensation unit, and amplification unit within the error amplifier stage and/or power output stage, see page 5 line 30-34 of the instant specification which defines the error amplification stage and power output stage. The above cited portion states:
“a first PMOS transistor PM20, a second PMOS transistor PM21, a third PMOS transistor PM22, a fourth PMOS transistor PM23, a fifth PMOS transistor PM24, a first NMOS transistor NM21, a second NMOS transistor NM22, a third NMOS transistor NM23, and a fourth NMOS transistor NM24 together constitute the error amplification stage of the low dropout regulator. A sixth PMOS transistor PM25, a first capacitor C20, a second capacitor C21, and a first resistor R21 together constitute the power output stage of the low dropout regulator.”
Furthermore, the compensation unit is defined as “the compensation unit 106 is implemented by using the fifth PMOS transistor PM24” in lines 16-17 of page 6 of the instant specification. Thus, it can be seen the compensation unit is double included within the error amplifier stage.
Moreover, the amplification unit is defined as “the amplification unit 107 includes the fourth NMOS transistor NM24 and the fifth PMOS transistor PM24 of the compensation unit 106” in lines 22-23 of page 6 of the instant specification. Thus, it can be seen the amplification unit double includes both the “error amplifier stage” and the “compensation unit”. Additionally, it can be seen that the sampling unit may be included in the output stage, see lines 6-9 of page 5. Therefore, Examiner will interpret and double include similar portions of the error amplification stage, compensation unit, sampling unit and amplification unit, 2, 4, 6 and 30), comprising a sampling unit (30), a compensation unit (one of M4/M3), and an amplification unit (one of M4/M3 with M2), wherein the sampling unit is connected to the compensation unit (at the gate), and the compensation unit is connected to the amplification unit (M3 to M2 via M4, or the drains of M4 and M2 directly connected);
a first AC signal within a target frequency band is obtained, by the sampling unit, from either an output node of the low dropout regulator or a ground node connected to the low dropout regulator, via an RC network, (AC signal sampled by 30, i.e., at least one of the values sampled in δIRC_COMP) and is outputted to the compensation unit (to the gates of M3/M4),
wherein the compensation unit is configured to generate, based on the first AC signal and a second AC signal obtained from the error amplification stage of the low dropout regulator, a third AC signal in phase or out of phase with the power supply voltage, and to output the third AC signal to the amplification unit, such that, within the target frequency band, an AC voltage at an input end of the power output stage of the low dropout regulator closely follows AC variation of a power supply voltage of the low dropout regulator (the sampled AC signal is combined with various AC fluctuations within the amplification unit, see Col. 10 lines 19-24 and Col. 8 lines 31-67, such that the variation of the power supply δVDD is cancelled out, see Col. 10 lines 33. Thus, the circuit operates as claimed).
With respect to claim 3, the power supply regulation system according to claim 1, wherein the sampling unit comprise a sixth resistor (Rcomp1) and a fourth capacitor (Ccomp1), one end of the fourth capacitor is connected to a ground cable end connected to the low dropout regulator (end of Ccomp1 connected to ground via Rcomp1), the other end of the fourth capacitor is connected to one end of the sixth resistor (the end of Ccomp1 that is connected to node 15 is connected to the end of Rcomp1 connected to ground via the capacitive coupling of Ccomp1 to Rcomp1 and the resistive coupling of Rcomp1 to ground), and the other end of the sixth resistor is connected to an input end of the compensation unit (the other end of Rcomp1 that is directly connected to Ccomp1 is connected node 15/gate of M3/M4 via the capacitive coupling of Ccomp1 to node 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumitsu et al. (USPN 7,459,895).
With respect to claim 10, Tokumitsu discloses, in Fig. 10 the power supply regulator system of claim 1 (see above rejection. Furthermore, Tokumitsu further suggests that the circuitry is constructed on an integrated chip (see Col. 3 lines 14-17). However, Tokumitsu fails to explicitly disclose that the circuit of Fig. 10 is constructed on a chip. Thus, Tokumitsu fails to disclose “an integrated circuit chip, comprising the power supply suppression circuit of the power supply regulation system according to claim 1.”
However, it is old and well-known to integrate power supply regulator systems, such as the low dropout regulator of Fig. 10 of Tokumitsu, into a single integrated chip for the purpose of, among other things, allowing for miniaturization of the circuit compared to constructing the circuit/system from discrete electronic components. Examiner takes official notice of constructing circuits into a single integrated circuit chip.
It would have been obvious to construct the circuit of Fig. 10 of Tokumitsu into a single integrated circuit chip for the purpose of, among other things, allowing for miniaturization of the circuit.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagarajan et al. (USPN 10,897,228) in view of Tokumitsu et al. (USPN 7,459,895).
With respect to claim 11, a communication terminal, comprising the power supply suppression circuit of the power supply regulation system according to claim 1.
With respect to claim 11, Nagarajan et al. discloses, in Figs. 1 and 6, a communication terminal (transceiver of Fig. 1 details of 100 disclosed in Fig. 6), comprising a voltage regulator (152, 156 and 154 of Fig. 6 within 100 of Fig. 1). Nagarajan et al. discloses a generic voltage regulator (152, 156 and 154, or a device that may be replaced with a regulator, see Col. 11 lines 3-9).
Nagarajan et al. fails to disclose "the power supply suppression circuit according to claim 1". However, the Tokumitsu discloses the circuit according to claim 1 (see above rejection of claim 1). The regulator of Tokumitsu has an improved power supply rejection ratio (PSRR), see Col. 6 line 64 to Col. 7 line 6. It would have been obvious to replace the generic regulator of Nagarajan et al. with the voltage regulator as disclosed by Tokumitsu, for the purpose of having a regulator with an improved PSRR.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, 10 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Cited Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tomioka et al. (USPN 9,367,073) discloses in Figs. 2 and 4, an amplifier having NMOS transistors connected in the same fashion as Tokumitsu’s “compensation unit” (i.e., 114/119 of Fig. 1) is functionally equivalent to an amplifier having PMOS transistors connected in the same fashion as Applicant’s “compensation unit” (i.e., 501/508 of Fig. 4). In other words Tomioka et al. discloses that NMOS and PMOS transistors may be interchanged in a CMOS amplifier and the amplifier will operate in a functionally equivalent manner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2849