Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to arguments
Applicant’s arguments with respect to claims 1 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument
Drawings
The drawings were received on 1/26/26. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 10, 12-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yi et. al. (CN Patent No 115079762) in view of Morino (U.S. Patent No 8575906) in further view of Teyagi et. al. (CN Patent 206877187).
Regarding claims 1 and 19, Yi et. al. discloses a low-dropout regulator (e.g. 100)(Fig. 1), comprising: an amplifier circuit (e.g. 122)(Fig. 1) operating based on an input voltage (e.g. VIN input to 122)(Fig. 1) and configured to generate an amplified voltage (e.g. output of 122)(Fig. 1) at a node (e.g. PG)(Fig. 1) according to a reference voltage and a feedback voltage (e.g. VREF and VFB are inputs to 122)(Fig. 1); a power transistor (e.g. MH3)(Fig. 1) configured to generate an output voltage (e.g. VOUT)(Fig. 1) at an output terminal (e.g. unlabeled node between MH3 and R1 of the voltage divider)(Fig. 1) according to the input voltage (e.g. VIN input to MH3)(Fig. 1) and the amplified voltage (e.g. PG node)(Fig. 1); a feedback circuit (e.g. R1 and R2 output VFB to 122)(Fig. 1) configured to generate the feedback voltage according to the output voltage (e.g. VOUT connected to R1 and R2)(Fig. 1).
an accelerator circuit (e.g. 130)(Fig. 1) configured to perform an acceleration operation (Para [0029] Espacenet machine translation, “…circuit 130 is configured to lower the gate voltage of the voltage regulating tube MH3 when the output voltage VOUT is lower than the second threshold voltage”) on the output voltage (e.g. VOUT)(Fig. 1) according to a voltage difference (e.g. VOUT lower than the second threshold voltage) in the low-dropout regulator.
Yi et. al. does not disclose an accelerator circuit comprises: a first transistor being in a diode-connected form; and an accelerator switch coupled to the first transistor in series, wherein when the amplifier circuit is turned off, the accelerator switch is turned off, wherein when the amplifier circuit is turned on, the accelerator switch is turned on.
However, Morino teaches an accelerator circuit (e.g. M21 and SW of circuit 10)(Fig. 14) comprises:
a first transistor being in a diode-connected form (e.g. M21 of circuit 10)(Fig. 14); and
an accelerator switch coupled to the first transistor in series (e.g. SW of circuit 10)(Fig. 14).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “LDO circuit” teachings of Yi et. al. such that it comprises “an accelerator circuit comprises: a first transistor being in a diode-connected form; and an accelerator switch coupled to the first transistor in series” as taught by Morino. The reason for doing so would be to control the gain of the amplifier according to a difference between the power supply input and the output of the regulator.
The combination of Yi et. al. and Morino does not appear to explicitly relite limitations wherein when the amplifier circuit is turned off, the accelerator switch is turned off, wherein when the amplifier circuit is turned on, the accelerator switch is turned on.
However, Teyagi et. al. discloses wherein when the amplifier circuit is turned off, the accelerator switch is turned off, wherein when the amplifier circuit is turned on, the accelerator switch is turned on. (CN206877187 Espacenet English translation Para [0031-0032], “The control circuit shuts off the low-dropout regulator by closing the first and second switches and turning off the amplifier. The control circuit turns on the low-dropout regulator by opening the first and second switches and turning on the amplifier”)
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “LDO circuit” teachings of Yi et. al. and Morino such that it comprises “wherein when the amplifier circuit is turned off, the accelerator switch is turned off, wherein when the amplifier circuit is turned on, the accelerator switch is turned on” as taught by Teyagi et. al. The reason for doing so would be to control power on and off of the amplifier circuit protecting electrical components for electrical over stress.
Regarding claim 3, Yi et. al. discloses wherein the power transistor is a P-type transistor (Para 0026 Machine translation CN115079762, “Specifically, the voltage regulating tube MH3 is implemented by a PMOS transistor”).
Regarding claim 4, Morino discloses wherein the accelerator circuit is coupled between the node (e.g. node between EA11 output and gate of M11)(Fig. 14) and the output terminal (e.g. Vo/13)(Fig. 14) and configured to perform the acceleration operation according to the voltage difference in the low-dropout regulator, wherein the voltage difference is a difference between the amplified voltage and the output voltage (Col 11, lines 10-16, “Specifically, in the present embodiment, the switch SW is disposed between the output terminal 13 and the output of the first differential amplifier EA11. The diode-connected transistor M21 has a source terminal thereof connectable to the output terminal 13 via the switch SW, and gate and drain terminals thereof connected together to the output of the differential amplifier EA11”)(See fig. 14).
Regarding claim 5 and 14, Morino discloses wherein the first transistor is an N-type transistor (Col 14, Lines 13-15, “Also unlike the first embodiment, the diode-connected transistor of the differential gain controller 10 is configured as an NMOS transistor M21a”).
Regarding claim 6 and 15, Morino discloses wherein the first transistor is a P-type transistor (Col 7, Lines 13-15, “and a diode-connected PMOS transistor M21”).
Regarding claim 10, Yi et. al. discloses wherein the power transistor is an N-type transistor (Para [0026] Espacenet machine translation, “…the voltage regulating tube MH3”)(Para [0024] Espacenet machine translation, “The voltage regulator tube may be a PMOS (N-Metal-Oxide-Semiconductor) transistor or an NMOS (N-Metal-Oxide-Semiconductor) transistor”).
Regarding claim 12, Morino discloses wherein the accelerator circuit (e.g. 10)(Fig. 8) is coupled between the input voltage (e.g. Vi)(Fig. 8) and the node (e.g. node between EA11 and M11 gate)(Fig. 8) and configured to perform the acceleration operation according to the voltage difference in the low-dropout regulator, wherein the voltage difference is a difference between the input voltage and the amplified voltage (Col 9-10, Lines 61-67, 1-4, “According to this patent specification, the differential gain controller 10 controls the gain G of the first differential amplifier EA11 according to a difference Vd between the power supply input and output voltages Vi and Vo of the voltage regulator 1, wherein the switch SW turns on and off an electrical current flow from the input terminal 11 to the source terminal of the diode-connected transistor M21 depending on the differential voltage Vd, so as to enable and disable the diode-connected transistor M21 to electrically connect to, or interfere with, the output VEA1 of the differential amplifier EA11 determining a maximum gate-to-source voltage Vgs applied across the driver transistor M11”).
Regarding claim 13, Morino discloses wherein the accelerator circuit (e.g. 10)(Fig. 15) is coupled between the input voltage (e.g. 11/Vi)(Fig. 15) and the output terminal (e.g. 13/Vo)(Fig. 15) and configured to perform the acceleration operation according to the voltage difference in the low-dropout regulator, wherein the voltage difference is a difference between the input voltage and the output voltage (Col 11, Lines 41-47, “During operation, the differential amplifier EA21 compares the output voltage Vo against the input voltage Vi, so as to output an error-amplified signal VEA2 to the gate terminal of the switchable transistor M22. In generating the output signal VEA2, the differential amplifier EA21 exhibits a threshold, offset voltage Va (i.e., the difference Vi-Vo between the non-inverting and inverting inputs with which the amplifier output switches from one level to another”).
Claims 7-9 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yi et. al. (CN Patent No 115079762) and Morino (U.S. Patent No 8575906) in further view of Tsao et. al. (U.S. Publication No 2022/0365550).
Regarding claim 7 and 16, although Yi et. al. and Morino disclose the limitations in claim 2, they do not teach wherein the accelerator circuit further comprises:
a second transistor coupled to the first transistor in series and being in the diode-connected form.
However, Tsao et. al. teaches wherein the accelerator circuit further comprises:
a second transistor (e.g. 504)(Fig. 5) coupled to the first transistor (e.g. 502)(Fig. 5) in series and being in the diode-connected form (See 504 and 502 in Fig. 5)
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “LDO circuit” teachings of Yi et. al. and Morino such that it comprises “a second transistor coupled to the first transistor in series and being in the diode-connected form” as taught by Tsao et. al. The reason for doing so would be to limit current variations.
Regarding claim 8 and 17, Tsao et. al. discloses wherein a type of the first transistor is the same to a type of the second transistor (Para [0051], “one or more PMOS transistors 502 and 504”).
Regarding claim 9 and 18, Although Morino and Yi et. al. discloses the limitations in claim 2, they do not disclose a type of the first transistor is different from a type of the second transistor. Tsao et. al. discloses the claimed invention except for a type of the first transistor is different from a type of the second transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have type of the first transistor is different from a type of the second transistor, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the accelerator circuit (208)(Fig. 5) to include the features of a type of the first transistor is different from a type of the second transistor because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies.
Allowable Subject Matter
Claim 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 11, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggest wherein the accelerator circuit is coupled between a control terminal of the second transistor and the output terminal and configured to perform the acceleration operation according to the voltage difference between in the low-dropout regulator, wherein the voltage difference is a difference between a bias voltage at the control terminal and the output voltage. Claim 11 depends on claim 10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN W SOILEAU whose telephone number is (571)272-6650. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hammond L Crystal can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838