Prosecution Insights
Last updated: October 01, 2026
Application No. 18/408,627

POWER AMPLIFIER CIRCUIT AND POWER AMPLIFICATION METHOD

Final Rejection §103
Filed
Jan 10, 2024
Priority
Jul 15, 2021 — JP 2021-116817 +1 more
Examiner
HILTUNEN, THOMAS J
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
1023 granted / 1256 resolved
+21.4% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
28 currently pending
Career history
1291
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
45.8%
+5.8% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1256 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 9-10, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ngo et al. (USPN 9,793,860) in view of Bakker et al. (USPN 6,373,233). With respect to claim 1, Ngo et al. discloses, in Figs. 1, a power amplifier circuit (Fig. 1, each stage 12a-12c provides power amplification to the signal and is thus a power amplifier, see Col. 4 line 49 to Col. 5 line 3) comprising: an external input terminal (20 which is a terminus of 11 and is thus external to the circuit, see Col. 4 lines 9-12) and an external output terminal (22 which is a terminus and thus external, see Col. 4 lines 14-18); a power amplifier (11); and at least one external power supply terminal (Vs which is an external connection to an external power supplying device such as a battery or a supply control network, see Col. 5 lines 24-26, the device generating Vs is not shown an thus external to 11) that receives, from a power supply circuit, a power supply voltage to be supplied to the power amplifier (Vs from a battery or supply control network), wherein the power amplifier (11) includes a first amplifying element (12A) including a first input terminal (16A), a first output terminal (18A), and a first power supply terminal (26A), a second amplifying element (12B) including a second input terminal (16B), a second output terminal (18B), and a second power supply terminal (26B), a first circuit that restricts the power supply voltage to a predetermined range (24 to voltage range of VREG, see Col. 5 lines 54-59) and outputs the restricted power supply voltage (VREG to 26A), and the first input terminal is connected to the external input terminal (16A directly connected to 20), the first output terminal is connected to the second input terminal (18A and 16B directly connected), the second output terminal is connected to the external output terminal (18B connected to 22 via 12C), the first power supply terminal is connected to the at least one external power supply terminal via the first circuit (26A connected to Vs via 24), and the second power supply terminal is connected to the at least one external power supply terminal (26B is directly connected to Vs). Ngo et al. merely discloses, in Fig. 1, a generic voltage regulator (24) and fails to disclose the details of the construction of 24. Furthermore, Ngo et al. fails to explicitly disclose “a first RC series circuit connected in parallel with the first circuit”. However, Bakker et al. discloses, in Fig. 2A, a specific voltage regulator (30 lest R3, Cm and Rm, e.g., see Fig. 1) that restricts the power supply voltage (at IN) to a predetermined range (regulated voltage level OUT according to the values of Vref and the voltage division ratio of R1 and R2) and outputs the restricted power supply voltage (as the OUT signal) and further includes a first RC series circuit (at least one of R3 and Rm with Cm) connected in parallel with the first circuit (in parallel between IN and OUT via the R3, Cm and Rm being serially connected and connected in parallel with the source and drain terminals of M1 across IN and OUT). The circuit of Fig. 2A of Bakker et al. is a specific regulator and has an improved stability. It would have been obvious to replace the generic regulator of 24 of Ngo et al. with the specific regulator of Fig. 2A of Bakker et al. for the purpose of having a specific regulator device with good stability and capable of operating as required by Ngo et al. Additionally, assuming, arguendo, that Ngo et al. fails to explicitly disclose that Vs, 20 and 22 are “external” connections. It would have been obvious to make such connections external to the amplifier circuit 11, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art, Nerwin v. Erlichman, 168 USPQ 177, 179. One would have been motivated to do so to for the purpose of making it easier to replace the power supply device and/or 11 from the upstream and downstream circuitry. Thus increasing flexibility and ease of replacement should 11 be damaged and/or it is desired to be replaced. With respect to claim 2, Ngo et al. discloses, in Fig. 1, a power amplifier circuit (Fig. 1) comprising: an external input terminal (20) and an external output terminal (22); a power amplifier (11); and at least one external power supply terminal (Vs terminal) that receives, from a power supply circuit, a power supply voltage to be supplied to the power amplifier (Vs voltage from battery or supply control network), wherein the power amplifier includes a first amplifying element (12A) including a first input terminal (16A), a first output terminal (18A), and a first power supply terminal (26A), a second amplifying element (12B) including a second input terminal (16B), a second output terminal (18B), and a second power supply terminal (26B), a first circuit (24), the first input terminal is connected to the external input terminal (16A directly connected to 20), the first output terminal is connected to the second input terminal (18A and 18B directly connected), the second output terminal is connected to the external output terminal (18B connected to 22 via 12C), the first power supply terminal is connected to the at least one external power supply terminal via the first circuit (26A connected to Vs via 24), and the second power supply terminal is connected to the at least one external power supply terminal (26B directly connected to Vs). Ngo et al. merely discloses, in Fig. 1, a generic voltage regulator (24) and fails to disclose the details of the construction of 24. Furthermore, Ngo et al. fails to explicitly disclose “a first RC series circuit connected in parallel with the first circuit” and “the first circuit includes a third amplifying element including a third input terminal and a third output terminal, a transistor that includes a control terminal connected to the third output terminal and that is connected between the at least one external power supply terminal and the first power supply terminal, and a feedback circuit connected between the first power supply terminal and the third input terminal”. However, Bakker et al. discloses, in Fig. 2A, a specific voltage regulator (30 lest R3, Cm and Rm, e.g., see Fig. 1) that a first RC series circuit (at least one of R3 and Rm with Cm) connected in parallel with the first circuit (in parallel between IN and OUT via the R3, Cm and Rm being serially connected and connected in parallel with the source and drain terminals of M1 across IN and OUT) and a third amplifying element (32) including a third input terminal (non-inverting terminal) and a third output terminal (output of 32), a transistor (M1) that includes a control terminal connected to the third output terminal (gate) and that is connected between the at least one external power supply terminal (IN) and the first power supply terminal (OUT power supply terminal, i.e., regulated output voltage), and a feedback circuit connected between the first power supply terminal and the third input terminal (R1 and R2). The circuit of Fig. 2A of Bakker et al. is a specific regulator and has an improved stability. It would have been obvious to replace the generic regulator of 24 of Ngo et al. with the specific regulator of Fig. 2A of Bakker et al. for the purpose of having a specific regulator device with good stability and capable of operating as required by Ngo et al. Additionally, assuming, arguendo, that Ngo et al. fails to explicitly disclose that Vs, 20 and 22 are “external” connections. It would have been obvious to make such connections external to the amplifier circuit 11, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art, Nerwin v. Erlichman, 168 USPQ 177, 179. One would have been motivated to do so to for the purpose of making it easier to replace the power supply device and/or 11 from the upstream and downstream circuitry. Thus increasing flexibility and ease of replacement should 11 be damaged and/or it is desired to be replaced. With respect to claim 3, the power amplifier circuit according to Claim 1, wherein the at least one external power supply terminal is a single external power supply terminal (Vs is a single external power supply). With respect to claim 9, the combination of Ngo et al. and Bakker et al. fails to disclose “wherein a resistor of the first RC series circuit is a variable resistor”. It can be seen that the values of RM and CM set a desired placement of the zero of the frequency response of the serially connected RC circuit of Bakker et al. (see Col. 2 lines 45-47). It would have been obvious to construct the circuit such that RM is variable, since it has been held the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). One would have been motivated to do so to allow one to fine tune the placement of the zero of the frequency response. With respect to claim 10, the combination of Ngo et al. and Bakker et al. fails to disclose “wherein a resistor of the first RC series circuit is a variable capacitor”. It can be seen that the values of RM and CM set a desired placement of the zero of the frequency response of the serially connected RC circuit of Bakker et al. (see Col. 2 lines 45-47). It would have been obvious to construct the circuit such that CM is variable, since it has been held the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). One would have been motivated to do so to allow one to fine tune the placement of the zero of the frequency response. With respect to claim 12, the power amplifier circuit according to Claim 1, wherein a resistor of the first RC series circuit is disposed within a first integrated circuit, the first integrated circuit including the first circuit or a control circuit which controls the power amplifier (the resistor is within the integrated circuit of 24 of Ngo et al./circuit of Bakker et al.). With respect to claim 13, the power amplifier circuit according to Claim 12, wherein a capacitor of the first RC series circuit is disposed within the first integrated circuit (the capacitor is within the integrated circuit of 24 of Ngo et al./circuit of Bakker et al.). Claim 20 merely recites the method of operating/constructing the circuit as recited in claim 1. Claim 20 is rejected for similar reasons as claim 1. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ngo et al. (USPN 9,793,860) in view of Bakker et al. (USPN 6,373,233) and in further view of Greenberg (USPN 7,825,715). With respect to claim 4, the above combination fails to disclose “the power amplifier circuit according to Claim 1, wherein the power amplifier further includes a first switch connected in series with the first RC series circuit”. However, it can be seen that the values of RM and CM set a desired placement of the zero of the frequency response of the serially connected RC circuit of Bakker et al. (see Col. 2 lines 45-47). It would have been obvious to construct the circuit such that CM is variable, since it has been held the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). One would have been motivated to do so to allow one to fine tune the placement of the zero of the frequency response. Ngo et al. and Bakker et al. fails to explicitly disclose how to construct a variable capacitor circuit. However, it is old and well known to construct a variable capacitor from a plurality of capacitors connected in parallel and each of the plurality of capacitors connected serially to a switch. This is further evidenced in Fig. 1 of Greenberg which discloses a variable capacitor (Fig. 1) comprising a plurality of capacitors connected in parallel (110a-140a) and each of the plurality of capacitors connected serially to a switch (110a-140b). The variable capacitor of Greenberg allows for adjustable capacitive values and includes switches with low/near zero resistance such that the impedance of the adjustable capacitor is substantially capacitive. Thus, providing for an accurate variable capacitance value. It would have been obvious to use the variable capacitor of Greenberg to provide the above modified variable capacitance for the purpose of having an adjustable capacitor with an accurate variable capacitance value. Allowable Subject Matter Claims 5-8, 11 and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 7/27/2026 have been fully considered but they are not persuasive. The argument that the combination of Ngo (USPN 9,793,860) and Bakker (USPN 6,373,233) fails to disclose “a first circuit that restricts the power supply voltage to a predetermined range and output s the restricted power supply voltage” and “first RC series circuit connected in parallel with the first circuit” is not persuasive. Applicant argues: as “illustrated in Fig. 2A of Bakker, the components R3, Cm, and Rm for part of the circuit that restricts the output voltage, i.e., they are part of a low-dropout regulator (LDO) (Bakker, col. 2, 11. 33-50). R3, Cm, and Rm in Bakker's LDO are needed for the LDO to function as an LDO. Without them, the circuit in Bakker is not functional. Therefore, R3, Cm, and Rm are not "connected in parallel" to the LDO of Bakker, they are part of the LDO itself. As such, it is believed that Bakker does not disclose or suggest the claimed first RC circuit.” The above arguments are not persuasive. The argument that R3, Cm and Rm are part of the LDO and are needed for the LDO to function as an LDO is incorrect. This is further evidenced in Fig. 1 of Bakker which discloses a well-known prior-art LDO that provides a restricted voltage (OUT). As can be seen Fig. 1 is essentially the same circuit as Fig. 2A of Bakker lest R3, Cm and Rm. Therefore, it is M1, R1, R2 and 32 that provides the restriction of the VIN voltage to the VOUT level and thus, M1, R1, R2 and 32 provide for the LDO/restricting operation. Furthermore, R3, Cm and Rm are merely added to the LDO/voltage restricting circuitry of M1, R1, R2 and 32 to add zero and increase stability and improve the phase margin of the LDO/voltage restricting circuitry (see Col. 2 lines 46-50 and Col. 2 line 54 to Col. 3 line 9). It can further be seen that the circuitry of Bakker includes regulating circuitry (i.e., M1, R1, R2 and 32, i.e., the switching circuit and control circuit of Col. 1 lines 40-51 and lines 60-67) and an additional RC compensation circuit (i.e., R3, Cm and Rm, see Col. 1 lines 50-59) that is distinct from the switching and control (i.e., regulating/restricting circuitry). Thus, Bakker includes an LDO having two distinct circuits including a voltage restricting circuit (switching element M1 under control of the control circuit R1, R2 and 32) and an RC compensating circuit including a first resistor (R3) connected with an RC circuit (Cm with Rm). Bakker explicitly discloses two distinct circuits where R3, Cm and Rm are in parallel with M1 of the voltage restricting circuitry. Therefore, Applicant’s arguments are not persuasive. It is further noted that all that is required to meet the claim limitation is that the prior art discloses the claimed elements. Bakker discloses both claimed elements of a first circuit that restricts the power supply and a first RC circuit connected in parallel to the first circuit. Bakker discloses both circuits and thus is operative as claimed. Moreover, the R3, Cm and Rm are incapable of “restricting the power supply” without M1, R1, R2 and 32. Therefore, R3, Cm and Rm constitute a distinct circuit that is added to the circuitry of the LDO M1, R1, R2 and 32 to provide stability to the LDO/power supply restricting circuitry. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jan 10, 2024
Application Filed
May 05, 2026
Non-Final Rejection mailed — §103
Jul 27, 2026
Response Filed
Aug 25, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
88%
With Interview (+6.1%)
1y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1256 resolved cases by this examiner. Grant probability derived from career allowance rate.

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