DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/8/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 states, “the second conductor layer includes a plurality of second wirings having a maximum wiring width of 5 um or less and a maximum inter-wiring distance of 7 um or less and not including a differential wiring”. The specifications does not discuss this particular feature relating to the second wirings and does not appear to have support in the original disclosure.
MPEP 2173.05(i) states, “Any negative limitation or exclusionary proviso must have basis in the original disclosure. If alternative elements are positively recited in the specification, they may be explicitly excluded in the claims. See In re Johnson, 558 F.2d 1008, 1019, 194 USPQ 187, 196 (CCPA 1977) ("[the] specification, having described the whole, necessarily described the part remaining."). See also Ex parte Grasselli, 231 USPQ 393 (Bd. App. 1983), aff’d mem., 738 F.2d 453 (Fed. Cir. 1984). In describing alternative features, the applicant need not articulate advantages or disadvantages of each feature in order to later exclude the alternative features. See Inphi Corporation v. Netlist, Inc., 805 F.3d 1350, 1356-57, 116 USPQ2d 2006, 2010-11 (Fed. Cir. 2015). The mere absence of a positive recitation is not basis for an exclusion. However, a lack of literal basis in the specification for a negative limitation may not be sufficient to establish a prima facie case for lack of descriptive support. Ex parte Parks, 30 USPQ2d 1234, 1236 (Bd. Pat. App. & Inter. 1993). "Rather, as with positive limitations, the disclosure must only 'reasonably convey[] to those skilled in the art that the inventor had possession of the claimed subject matter as of the filing date.' ... While silence will not generally suffice to support a negative claim limitation, there may be circumstances in which it can be established that a skilled artisan would understand a negative limitation to necessarily be present in a disclosure." Novartis Pharms. Corp. v. Accord Healthcare, Inc., 38 F.4th 1013, 2022 USPQ2d 569 (Fed. Cir. 2022) (quoting Ariad Pharm. Inc. v. Eli Lilly & Co., 589 F.3d 1336, 1351, 94 USPQ2d 1161, 1172). Any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement. See MPEP § 2163 - § 2163.07(b) for a discussion of the written description requirement of 35 U.S.C. 112(a) and pre-AIA 35 U.S.C. 112, first paragraph.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-8, 13-14 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US PG. Pub. 2024/0015888) in view of Ikeda et al. (US PG. Pub. 2020/0389969).
Regarding claim 1 – Uchida teaches a wiring substrate (figs. 1A-1B, 5 [paragraph 0019] Uchida states, “wiring board 5”), comprising: a first wiring part (1 [paragraph 0019] Uchida states, “first interconnect structure 1”) comprising a first insulating layer (14 [paragraph 0028] Uchida states, “first insulating layer 14”) and a first conductor layer (15 [paragraph 0023] Uchida states, “first interconnect layer 15”) laminated on the first insulating layer (14); and a second wiring part (2 [paragraph 0023] Uchida states, “second interconnect structure 2”) formed on the first wiring part (1) and comprising a second insulating layer (21 [paragraph 0035] Uchida states, “second insulating layer 21”) and a second conductor layer (22 [paragraph 0037] Uchida states, “second interconnect layer 22”) laminated on the second insulating layer (21) such that a thickness of the second insulating layer (21 [paragraph 0040] Uchida states, “A thickness of the second insulating layer 21 can be in a range of approximately 10 μm to approximately 20 μm, for example”) is smaller than a thickness of the first insulating layer (14 [paragraph 0063 & 0058] Uchida states, “A material used for the first insulating layer 14 and a thickness of the first insulating layer 14 can be the same as those of the first insulating layer 12…The thickness of each of the first insulating layer 12 and the third insulating layer 32 can be in a range of approximately 20 μm to approximately 40 μm, for example”) and that a thickness of the second conductor layer (22 [paragraph 0041] Uchida states, “A thickness of the interconnect pattern forming the second interconnect layer 22 can be in a range of approximately 5 μm to approximately 10 μm”) is smaller than a thickness of the first conductor layer (15 [paragraph 0070] Uchida states, “the thickness of the interconnect pattern forming the first interconnect layer after the polishing becomes identical to the thickness of the first insulating layer 16. The thickness of the first insulating layer 16 can be in a range of approximately 5 μm to approximately 15 μm, for example”), wherein the first wiring part (1) is formed such that the first conductor layer (15) includes a plurality of first wirings (figure 1 shows a plurality of first wirings along the first conductor layer 15), and the second wiring part (2) is formed such that the second conductor layer (22) includes a plurality of second wirings (see plurality of second wirings along the second conductor 22) having a maximum wiring width of 5 um or less and a maximum inter-wiring distance of 7 um or less ([paragraph 0079] Uchida states, “The line-and-space of the second interconnect layer 22 can be in a range of approximately 3 μm/3 μm to approximately 8 μm/8 μm”) and not including a differential wiring (the second wirings along the second conductor 22 are not described as being “differential wirings” and appears to meet the claimed limitation) and that the second wiring part (2) is positioned closer to an outermost surface of the wiring substrate (5) than the first wiring part (1; claimed structure shown in figure 1A).
Ikeda fails to teach wherein the plurality of first wirings includes a plurality of differential wirings having a minimum wiring width of larger than 5 um and a minimum inter-wiring distance of larger than 7 um.
Ikeda teaches a wiring substrate (fig. 1, 100 [paragraph 0020] Ikeda states, “wiring substrate 100”) having a first wiring part (2 [paragraph 0021] Ikeda states, “core substrate 1”) having a plurality of first wirings (22/23/26 [paragraph 0053 & 0049] Ikeda states, “conductor layer 22…conductor layers (23a-23d)…strip line 26”) includes a plurality of differential wirings ([paragraph 0088] Ikeda states, “line pattern (26a) may each form a differential transmission line by including two wiring patterns extending in parallel”) having a minimum wiring width of larger than 5 um and a minimum inter-wiring distance of larger than 7 um ([paragraph 0035] Ikeda states, “the second conductor layer 22 and the conductor layers (23a-23e) in the core substrate 2 can each have, for example, a wiring pattern formed according to a wiring rule of (30 μm)/(30 μm) regarding a (minimum line width)/(minimum line spacing) (L/S)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first wiring part including a first conductor layer that has a plurality of first wirings as taught by Uchida with the first wirings include a plurality of differential wiring with a wiring width of 5um or larger and a minimum inter-wiring distance of 7um or larger as taught by Ikeda because Ikeda states, “By properly selecting the line widths and thicknesses of the first and second line patterns (16a, 26a) and the thicknesses and relative permittivities of the pair of interlayer insulating layers 140 and the pair of intra core substrate insulating layers 240, desired characteristic impedances of the strip lines can be obtained” [paragraph 0050].
Regarding claim 2 – Uchida in view of Ikeda teach the wiring substrate according to claim 1, wherein at least one of the first (Ikeda; figs. 1-2B, 2) and second wiring parts (1) includes a plane layer (fig. 2B, 23c [paragraph 0041] Ikeda states, “conductor layer (23c)”) adjacent to an upper side or a lower side of the differential wirings (26) such that the plane layer (23c) is positioned to overlap with the differential wirings (26; claimed structure show in figure 1).
Regarding claim 7 - Uchida in view of Ikeda teach the wiring substrate according to claim 1, wherein the first (Uchida; fig. 1A & 1B, 1) and second (2) wiring parts are formed such that each of the first insulating layer (14) and the second insulating layer (21) include inorganic filler particles (21f & 16f [paragraph 0040 & 0031] Uchida states, “the filler 21f, such as silica (SiO.sub.2)…The first insulating layer 14 and the third insulating layer 34 may include a filler, such as silica (SiO.sub.2) or the like. An average grain diameter of the filler, a maximum grain diameter of the filler, and a filler content of the filler included in the first insulating layer 14 and the third insulating layer 34 can be the same as those of the filler 16f included in the first insulating layer 16”) and that a maximum particle size of the inorganic filler particles (21f [paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”) in the second insulating layer (21) is smaller than a maximum particle size of the inorganic filler particles (16f [paragraph 0053] Uchida state, “the average grain diameter of the filler 16f would be less than or equal to 0.5 μm and the maximum grain diameter of the filler 16f would be less than or equal to 5 μm”) in the first insulating layer (14).
Regarding claim 8 – Uchida in view of Ikeda teach the wiring substrate according to claim 7, wherein the second wiring part (Uchida; fig. 1A & 1B, 2) is formed such that the maximum particle size of the inorganic filler particles (21f) in the second insulating layer is set to 1 um or less ([paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”).
Regarding claim 13 - Uchida in view of Ikeda teach the wiring substrate according to claim 2, wherein the first (Uchida; fig. 1A & 1B, 1) and second (2) wiring parts are formed such that each of the first insulating layer (14) and the second insulating layer (21) include inorganic filler particles (21f & 16f [paragraph 0040 & 0031] Uchida states, “the filler 21f, such as silica (SiO.sub.2)…The first insulating layer 14 and the third insulating layer 34 may include a filler, such as silica (SiO.sub.2) or the like. An average grain diameter of the filler, a maximum grain diameter of the filler, and a filler content of the filler included in the first insulating layer 14 and the third insulating layer 34 can be the same as those of the filler 16f included in the first insulating layer 16”) and that a maximum particle size of the inorganic filler particles (21f [paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”) in the second insulating layer (21) is smaller than a maximum particle size of the inorganic filler particles (16f [paragraph 0053] Uchida state, “the average grain diameter of the filler 16f would be less than or equal to 0.5 μm and the maximum grain diameter of the filler 16f would be less than or equal to 5 μm”) in the first insulating layer (14).
Regarding claim 14 – Uchida in view of Ikeda teach the wiring substrate according to claim 13, wherein the second wiring part (Uchida; fig. 1A & 1B, 2) is formed such that the maximum particle size of the inorganic filler particles (21f) in the second insulating layer is set to 1 um or less ([paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”).
Regarding claim 19 - Uchida in view of Ikeda teach the wiring substrate according to claim 4, wherein the first (Uchida; fig. 1A & 1B, 1) and second (2) wiring parts are formed such that each of the first insulating layer (14) and the second insulating layer (21) include inorganic filler particles (21f & 16f [paragraph 0040 & 0031] Uchida states, “the filler 21f, such as silica (SiO.sub.2)…The first insulating layer 14 and the third insulating layer 34 may include a filler, such as silica (SiO.sub.2) or the like. An average grain diameter of the filler, a maximum grain diameter of the filler, and a filler content of the filler included in the first insulating layer 14 and the third insulating layer 34 can be the same as those of the filler 16f included in the first insulating layer 16”) and that a maximum particle size of the inorganic filler particles (21f [paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”) in the second insulating layer (21) is smaller than a maximum particle size of the inorganic filler particles (16f [paragraph 0053] Uchida state, “the average grain diameter of the filler 16f would be less than or equal to 0.5 μm and the maximum grain diameter of the filler 16f would be less than or equal to 5 μm”) in the first insulating layer (14).
Regarding claim 20 – Uchida in view of Ikeda teach the wiring substrate according to claim 19, wherein the second wiring part (Uchida; fig. 1A & 1B, 2) is formed such that the maximum particle size of the inorganic filler particles (21f) in the second insulating layer is set to 1 um or less ([paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”).
Claim(s) 3, 4, 9-10, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida in view of Ikeda et al. as applied to claim 1 and 2 above, and further in view of Harazono et al. (US PG. Pub. 2011/0314666).
Regarding claim 3 – Uchida in view of Ikeda teach the wiring substrate according to claim 1, having differential wirings (Ikeda; fig. 1, 26 [paragraph 0088] Ikeda states, “the second line pattern (26a) may each form a differential transmission line by including two wiring patterns extending in parallel”) but fails to teach wherein the first conductor layer is formed in the first wiring part such that upper surfaces of wirings have an arithmetic mean roughness of 0.13 um or less.
Harazono teaches a wiring substrate (fig. 1A-1B) wherein the first conductor layer (11 [paragraph 0047] Harazono states, “conductive layers 11”) is formed in the first wiring part (6) such that upper surfaces of wirings (see wirings within the first conductor layer 11) have an arithmetic mean roughness of 0.13 um or less ([paragraph 0057] Harazono states, “The surface roughness of the side surface and one main surface of the conductive layer 11 has Ra (arithmetic average roughness) set to greater than or equal to 0.1 .mu.m and smaller than or equal to 1 .mu.m according to such unevenness. The arithmetic average roughness complies with ISO4287:1997”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first wiring part with a first conductor layer that includes a plurality of differential wirings as taught by Uchida in view of Ikeda with the wirings having an upper surface arithmetic mean roughness of 0.13 um or less as taught by Harazono because Harazono states, “The conductive layer 11 has microscopic unevenness formed on the side surface and one main surface thereof. As a result, the adhesion strength with the second resin layer 10b can be enhanced and separation between the conductive layer 11 and the second resin layer 10b can be reduced, so that breakage of the conductive layer 11 can be reduced” [paragraph 0057].
Regarding claim 4 – Uchida in view of Ikeda and Harazono teach the wiring substrate according to claim 3, wherein the first wiring part (Ikeda; fig. 1, 2) is formed such that the first wiring part (2) includes an organic film layer (24 [paragraph 0028] Ikeda states, “The intra core substrate insulating layers (24a-24f), the interlayer insulating layers (14a-14c) and the interlayer insulating layers 34 are formed using an arbitrary insulating material. Examples of the insulating material include an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, and the like”; epoxy resin is considered to be an organic as it contains carbon) covering the upper surfaces of the differential wirings (26).
Regarding claim 9 – Uchida in view of Ikeda teach the wiring substrate according to claim 2, having differential wirings (Ikeda; fig. 1, 26 [paragraph 0088] Ikeda states, “the second line pattern (26a) may each form a differential transmission line by including two wiring patterns extending in parallel”) but fails to teach wherein the first conductor layer is formed in the first wiring part such that upper surfaces of wirings have an arithmetic mean roughness of 0.13 um or less.
Harazono teaches a wiring substrate (fig. 1A-1B) wherein the first conductor layer (11 [paragraph 0047] Harazono states, “conductive layers 11”) is formed in the first wiring part (6) such that upper surfaces of wirings (see wirings within the first conductor layer 11) have an arithmetic mean roughness of 0.13 um or less ([paragraph 0057] Harazono states, “The surface roughness of the side surface and one main surface of the conductive layer 11 has Ra (arithmetic average roughness) set to greater than or equal to 0.1 .mu.m and smaller than or equal to 1 .mu.m according to such unevenness. The arithmetic average roughness complies with ISO4287:1997”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first wiring part with a first conductor layer that includes a plurality of differential wirings as taught by Uchida in view of Ikeda with the wirings having an upper surface arithmetic mean roughness of 0.13 um or less as taught by Harazono because Harazono states, “The conductive layer 11 has microscopic unevenness formed on the side surface and one main surface thereof. As a result, the adhesion strength with the second resin layer 10b can be enhanced and separation between the conductive layer 11 and the second resin layer 10b can be reduced, so that breakage of the conductive layer 11 can be reduced” [paragraph 0057].
Regarding claim 10 – Uchida in view of Ikeda and Harazono teach the wiring substrate according to claim 9, wherein the first wiring part (Ikeda; fig. 1, 2) is formed such that the first wiring part (2) includes an organic film layer (24 [paragraph 0028] Ikeda states, “The intra core substrate insulating layers (24a-24f), the interlayer insulating layers (14a-14c) and the interlayer insulating layers 34 are formed using an arbitrary insulating material. Examples of the insulating material include an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, and the like”; epoxy resin is considered to be an organic as it contains carbon) covering the upper surfaces of the differential wirings (26).
Regarding claim 17 - Uchida in view of Ikeda and Harazono teach the wiring substrate according to claim 3, wherein the first (Uchida; fig. 1A & 1B, 1) and second (2) wiring parts are formed such that each of the first insulating layer (14) and the second insulating layer (21) include inorganic filler particles (21f & 16f [paragraph 0040 & 0031] Uchida states, “the filler 21f, such as silica (SiO.sub.2)…The first insulating layer 14 and the third insulating layer 34 may include a filler, such as silica (SiO.sub.2) or the like. An average grain diameter of the filler, a maximum grain diameter of the filler, and a filler content of the filler included in the first insulating layer 14 and the third insulating layer 34 can be the same as those of the filler 16f included in the first insulating layer 16”) and that a maximum particle size of the inorganic filler particles (21f [paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”) in the second insulating layer (21) is smaller than a maximum particle size of the inorganic filler particles (16f [paragraph 0053] Uchida state, “the average grain diameter of the filler 16f would be less than or equal to 0.5 μm and the maximum grain diameter of the filler 16f would be less than or equal to 5 μm”) in the first insulating layer (14).
Regarding claim 18 – Uchida in view of Ikeda and Harazono teach the wiring substrate according to claim 17, wherein the second wiring part (Uchida; fig. 1A & 1B, 2) is formed such that the maximum particle size of the inorganic filler particles (21f) in the second insulating layer is set to 1 um or less ([paragraph 0040] Uchida states, “The average grain diameter of the filler 21f can be less than or equal to 0.1 μm”).
Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida in view of Ikeda et al. as applied to claims 1 and 2 above, and further in view of Nagai et al. (US PG. Pub. 2021/0185807).
Regarding claim 5 – Uchida in view of Ikeda teach the wiring substrate according to claim 1, but fails to teach wherein the first and second wiring parts are formed such that a dielectric loss tangent of the first insulating layer is smaller than a dielectric loss tangent of the second insulating layer and that a relative permittivity of the first insulating layer is smaller than a relative permittivity of the second insulating layer.
Nagai teaches wherein a dielectric loss tangent of a first insulating layer (fig. 1A, 11) is smaller than a dielectric loss tangent of a second insulating layer (23 [paragraph 0037] Nagai states, “the dielectric loss tangent of the first resin layers 11 and 12 is smaller than the dielectric loss tangent of the second resin layers 21, 22 and 23”) and that a relative permittivity of the first insulating layer (11) is smaller than a relative permittivity of the second insulating layer (23 [paragraph 0037] Nagai states, “a relative permittivity (E1) of the first resin layers 11 and 12 is lower than a relative permittivity (E2) of the second resin layers 21, 22, and 23 (E1<E2)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first and second wiring parts with first and second insulating layers as taught by Uchida in view of Ikeda with the first insulating layer has a smaller dielectric loss tangent and relative permittivity than that of the second insulating layer as taught by Nagai because Nagai states, “the first resin layers 11 and 12 have better high frequency characteristics than the second resin layers 21, 22, and 23…When the resin multilayer board is used for high frequency applications as in the present preferred embodiment, the first resin layers 11 and 12 preferably include materials having excellent high frequency characteristics…the insulating substrate 30 includes the first resin layers 11 and 12 having a lower relative permittivity than that of the second resin layers 21, 22, and 23. Thus, when a circuit with a predetermined characteristics is provided on the resin multilayer board, the line width of a conductor pattern provided on the insulating substrate 30 can be made wide, such that the conductor loss of the circuit can be reduced” [paragraphs 0037, 0036 & 0049].
Regarding claim 11 – Uchida in view of Ikeda teach the wiring substrate according to claim 2, but fails to teach wherein the first and second wiring parts are formed such that a dielectric loss tangent of the first insulating layer is smaller than a dielectric loss tangent of the second insulating layer and that a relative permittivity of the first insulating layer is smaller than a relative permittivity of the second insulating layer.
Nagai teaches wherein a dielectric loss tangent of a first insulating layer (fig. 1A, 11) is smaller than a dielectric loss tangent of a second insulating layer (23 [paragraph 0037] Nagai states, “the dielectric loss tangent of the first resin layers 11 and 12 is smaller than the dielectric loss tangent of the second resin layers 21, 22 and 23”) and that a relative permittivity of the first insulating layer (11) is smaller than a relative permittivity of the second insulating layer (23 [paragraph 0037] Nagai states, “a relative permittivity (E1) of the first resin layers 11 and 12 is lower than a relative permittivity (E2) of the second resin layers 21, 22, and 23 (E1<E2)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first and second wiring parts with first and second insulating layers as taught by Uchida in view of Ikeda with the first insulating layer has a smaller dielectric loss tangent and relative permittivity than that of the second insulating layer as taught by Nagai because Nagai states, “the first resin layers 11 and 12 have better high frequency characteristics than the second resin layers 21, 22, and 23…When the resin multilayer board is used for high frequency applications as in the present preferred embodiment, the first resin layers 11 and 12 preferably include materials having excellent high frequency characteristics…the insulating substrate 30 includes the first resin layers 11 and 12 having a lower relative permittivity than that of the second resin layers 21, 22, and 23. Thus, when a circuit with a predetermined characteristics is provided on the resin multilayer board, the line width of a conductor pattern provided on the insulating substrate 30 can be made wide, such that the conductor loss of the circuit can be reduced” [paragraphs 0037, 0036 & 0049].
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida in view of Ikeda et al. and Nagai et al. as applied to claim 5 above, and further in view of Takenaka et al. (US PG. Pub. 2022/0223532).
Regarding claim 6 – Uchida in view of Ikeda and Nagai teach the wiring substrate according to claim 5, but fails to teach wherein the first wiring part is formed such that the first insulating layer has the dielectric loss tangent of 0.005 or less and the relative permittivity of 3.5 or less at a frequency of 5.8 GHz.
Takenaka teaches a wiring substrate (fig. 1, 1) wherein the first wiring part (10 [paragraph 0021] Takenaka states, “first build-up part 10”) is formed such that the first insulating layer (11) has the dielectric loss tangent of 0.005 or less and the relative permittivity of 3.5 or less at a frequency of 1.0 GHz ([paragraph 0043] Takenaka states, “it is more preferable that the insulating layer 11 directly above the conductor layer 112 similarly has a relative permittivity of 3.5 or less and a dielectric loss tangent of 0.005 or less at a frequency of 1 GHz”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first and second wiring parts with first insulating layer having a smaller dielectric loss tangent and a smaller relative permittivity than the second insulating layer as taught by Uchida in view of Ikeda and Nagai with the first insulating layer having a dielectric loss tangent of 0.005 or less and a relative permittivity of 3.5 or less at a frequency of 1GHz as taught by Takenaka because Takenaka states, “Since all the insulating layers in contact with the conductor layer 112 have excellent high frequency characteristics, the conductor layer 112 can have even more excellent signal transmission quality” [paragraph 0043].
Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitation “at a frequency of 5.8 GHz“ which is narrative in form have not been given significant patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Please note that in the instant application, paragraph 0042 and 0048 Applicant has not disclosed any criticality for the claimed limitations.
Regarding claim 12 – Uchida in view of Ikeda and Nagai teach the wiring substrate according to claim 11, but fails to teach wherein the first wiring part is formed such that the first insulating layer has the dielectric loss tangent of 0.005 or less and the relative permittivity of 3.5 or less at a frequency of 5.8 GHz.
Takenaka teaches a wiring substrate (fig. 1, 1) wherein the first wiring part (10 [paragraph 0021] Takenaka states, “first build-up part 10”) is formed such that the first insulating layer (11) has the dielectric loss tangent of 0.005 or less and the relative permittivity of 3.5 or less at a frequency of 1.0 GHz ([paragraph 0043] Takenaka states, “it is more preferable that the insulating layer 11 directly above the conductor layer 112 similarly has a relative permittivity of 3.5 or less and a dielectric loss tangent of 0.005 or less at a frequency of 1 GHz”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first and second wiring parts with first insulating layer having a smaller dielectric loss tangent and a smaller relative permittivity than the second insulating layer as taught by Uchida in view of Ikeda and Nagai with the first insulating layer having a dielectric loss tangent of 0.005 or less and a relative permittivity of 3.5 or less at a frequency of 1GHz as taught by Takenaka because Takenaka states, “Since all the insulating layers in contact with the conductor layer 112 have excellent high frequency characteristics, the conductor layer 112 can have even more excellent signal transmission quality” [paragraph 0043].
Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitation “at a frequency of 5.8 GHz“ which is narrative in form have not been given significant patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Please note that in the instant application, paragraph 0042 and 0048 Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida in view of Ikeda et al. and Harazono et al. as applied to claim 3 above, and further in view of Nagai et al.
Regarding claim 15 – Uchida in view of Ikeda and Harazono teach the wiring substrate according to claim 3, but fails to teach wherein the first and second wiring parts are formed such that a dielectric loss tangent of the first insulating layer is smaller than a dielectric loss tangent of the second insulating layer and that a relative permittivity of the first insulating layer is smaller than a relative permittivity of the second insulating layer.
Nagai teaches wherein a dielectric loss tangent of a first insulating layer (fig. 1A, 11) is smaller than a dielectric loss tangent of a second insulating layer (23 [paragraph 0037] Nagai states, “the dielectric loss tangent of the first resin layers 11 and 12 is smaller than the dielectric loss tangent of the second resin layers 21, 22 and 23”) and that a relative permittivity of the first insulating layer (11) is smaller than a relative permittivity of the second insulating layer (23 [paragraph 0037] Nagai states, “a relative permittivity (E1) of the first resin layers 11 and 12 is lower than a relative permittivity (E2) of the second resin layers 21, 22, and 23 (E1<E2)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first and second wiring parts with first and second insulating layers as taught by Uchida in view of Ikeda and Harazono with the first insulating layer has a smaller dielectric loss tangent and relative permittivity than that of the second insulating layer as taught by Nagai because Nagai states, “the first resin layers 11 and 12 have better high frequency characteristics than the second resin layers 21, 22, and 23…When the resin multilayer board is used for high frequency applications as in the present preferred embodiment, the first resin layers 11 and 12 preferably include materials having excellent high frequency characteristics…the insulating substrate 30 includes the first resin layers 11 and 12 having a lower relative permittivity than that of the second resin layers 21, 22, and 23. Thus, when a circuit with a predetermined characteristics is provided on the resin multilayer board, the line width of a conductor pattern provided on the insulating substrate 30 can be made wide, such that the conductor loss of the circuit can be reduced” [paragraphs 0037, 0036 & 0049].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida in view of Ikeda et al., Harazono et al. and Nagai et al. as applied to claim 15 above, and further in view of Takenaka et al.
Regarding claim 16 – Uchida in view of Ikeda, Harazono and Nagai teach the wiring substrate according to claim 15, but fails to teach wherein the first wiring part is formed such that the first insulating layer has the dielectric loss tangent of 0.005 or less and the relative permittivity of 3.5 or less at a frequency of 5.8 GHz.
Takenaka teaches a wiring substrate (fig. 1, 1) wherein the first wiring part (10 [paragraph 0021] Takenaka states, “first build-up part 10”) is formed such that the first insulating layer (11) has the dielectric loss tangent of 0.005 or less and the relative permittivity of 3.5 or less at a frequency of 1.0 GHz ([paragraph 0043] Takenaka states, “it is more preferable that the insulating layer 11 directly above the conductor layer 112 similarly has a relative permittivity of 3.5 or less and a dielectric loss tangent of 0.005 or less at a frequency of 1 GHz”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having a first and second wiring parts with first insulating layer having a smaller dielectric loss tangent and a smaller relative permittivity than the second insulating layer as taught by Uchida in view of Ikeda, Harazono and Nagai with the first insulating layer having a dielectric loss tangent of 0.005 or less and a relative permittivity of 3.5 or less at a frequency of 1GHz as taught by Takenaka because Takenaka states, “Since all the insulating layers in contact with the conductor layer 112 have excellent high frequency characteristics, the conductor layer 112 can have even more excellent signal transmission quality” [paragraph 0043].
Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitation “at a frequency of 5.8 GHz“ which is narrative in form have not been given significant patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Please note that in the instant application, paragraph 0042 and 0048 Applicant has not disclosed any criticality for the claimed limitations.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Preda et al. (US PG. Pub. 2024/0136270) discloses a dense via pitch interconnect to increase wiring density.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Prosecution Insights