DETAILED ACTION
The office action is in response to application filed on 7-8-28. Claims 1-15 are pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 recites “two or more individual inverter” should be “two or more an individual inverter”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 103 (a) as being unpatentable over by US 2024/0235452 to Dai et al. (“Dai”) in view of US 2013/0242623 to Wei et al. (“Wei”).
Regarding claim 1, Dai disclose a method for balancing DC-link voltages of DC-link (fig. 4, DC-link 410, 412) the method comprising the steps of: receiving in a master controller (supervisor controller 446) measured DC-link voltages (para; 0072, lines 8-10, Particularly, with the symmetric topologies and PWM switching scheme, the voltage and current of the first inverter 424 and the second inverter 426) of two or more series connected inverters, (first inverter 424 and second inverter 426); generating in said master controller fan control data (para; 0166, The one or more memory device(s) 1010B can store information) and/or fan PWM control signaling (para; 0069) for each of said two or more cooling fans connected to a DC-link (fig. 4, DC-link 410, 412) of each of said two or more series connected inverters based on said measured DC-link voltages; and forwarding by said master controller said fan control data (para; 0166, The one or more memory device(s) 1010B can store information) and/or said fan PWM control signaling (para; 0154, lines 5-9, first switches of the first inverter can mirror their respective corresponding second switches of the second inverter. The first switches can be pulse width modulated to generate first PWM signals, e.g., for each phase of power the first inverter is configured to output) for controlling each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust).
But, Dai does not discloses capacitors in series connected inverters each of said series connected inverters having an individual inverters cooling fan of two or more cooling fans
However, Wei discloses capacitors (fig. 2, Cu, Cv, Cw are series with Ca, Cb, Cc) in series connected inverters (fig. 2, (120-1, 120-2) and (110-1, 110-2)) each of said series connected inverters having an individual inverters cooling fan of two or more cooling fans (para; 0019, two inverters 120-1 and 120-2 coupled with a shared single common mode choke 130 having four windings LA-LD in accordance with the disclosure with one or more blowers or cooling fans)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding one or more blowers or cooling fans to inverters as part of its configuration as taught by Wei, in order to remove excess heat from inverters, to prevent overheating and ensure optimal performance.
Regarding claim 2, Dai disclose in the step of generating fan PWM control signaling (para; 0062, pulse width modulated (PWM) switching scheme as will be described herein) for each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust) is generated in said master controller (supervisor controller 446); and in the step of forwarding said fan PWM control signaling is forwarded to each of said two or more cooling fans by said master controller for controlling each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust).
Regarding claim 6, Dai disclose said method is activated during a non-driving operation period of the series connected inverters (para; 0084, lines 10-13, if one of the first and second inverters 424, 426 of FIG. 8 is shut down or otherwise stops operating, common mode EMI can still be reduced by the first and second inductors 418, 420).
Regarding claim 7, Dai disclose said method is deactivated upon the start of the driving operation period of the series connected inverters (para; 0084, lines 10-13, if one of the first and second inverters 424, 426 of FIG. 8 is shut down or otherwise stops operating, common mode EMI can still be reduced by the first and second inductors 418, 420).
Claims 3-5 and 8-15 are rejected under 35 U.S.C. 103 (a) as being unpatentable over US 2024/0235452 to Dai et al. (“Dai”) in view of US 2024/0063746 to MORI et al. (“MORI”) and further in view of US 2013/0242623 to Wei et al. (“Wei”).
Regarding claim 3, Dai disclose in the step of generating fan control data (para; 0166, The one or more memory device(s) 1010B can store information) for each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust) is generated in said master controller, wherein said fan control data comprises (para; 0166, The one or more memory device(s) 1010B can store information) arranged to control each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust).
But, Dai does not discloses a DC-link reference voltage for each of said two or more series connected inverters; and in the step of forwarding said fan PWM control signaling is forwarded to two or more local controllers;
However, MORI disclose a DC-link reference voltage (para; 0049, lines 3-5, smoothing capacitor 12 suppresses and stabilizes variation of the DC voltage Vdc supplied to the first set of inverters 6a and the second set of inverters 6b) for each of said two or more series connected inverters; and in the step of forwarding said fan PWM control signaling is forwarded to two or more local controllers (fig. 2, 30a and 30b);
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding two controllers as part of its configuration as taught by MORI, in order to detect high potential side bus line and the low potential side bus line to balance output signal.
Regarding claim 4, Dai disclose the method comprises the steps of: receiving fan control data (para; 0166, The one or more memory device(s) 1010B can store information) from said master controller (supervisor controller 446); generating in said local controller fan PWM control signaling for a cooling fan of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust) based on the difference between inverter DC-link voltage and said DC-link reference voltage (para; 0060, DC-link 414 spans between the positive DC-link 410 and the negative DC-link 412. A DC-link capacitor 416 is positioned along the DC-link 414 and is operable to stabilize the DC voltage) received from said master controller (para; 0166, The one or more memory device(s) 1010B can store information); and forwarding by said local controller said fan PWM control signaling to said cooling fan for controlling said cooling fan (para; 0064, PWM switching scheme).
But, Dai does not disclose a local controller of said two or more local controllers;
However, MORI disclose a local controller of said two or more local controllers (fig. 2, 30a and 30b);
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding two controllers as part of its configuration as taught by MORI, in order to detect high potential side bus line and the low potential side bus line to balance output signal.
Regarding claim 5, Dai disclose in every microcontroller cycle (para; 0165, The one or more processor(s) 1010A can include any processing device, such as a microprocessor, microcontroller, integrated circuit, logic device, and/or other suitable processing device)
But, Dai does not disclose the ratio of the measured DC-link voltage Vdc mesa and a DC-link reference voltage Vdc ref of each of said two or more series connected inverters is computed as a voltage ratio V dc meas/Vdc ref and wherein based on said computed voltage ratio, the PWM duty cycle of the respective cooling fan is updated.
However, MORI disclose the ratio (para; 0085, lines 4-13, the first set of voltage utilization factor M1 is a ratio of an amplitude V1 amp of fundamental wave components of line voltages of applied voltages of the first set of three-phase armature windings with respect to the power source voltage V dc of the DC power source. The second set of voltage utilization factor M2 is a ratio of an amplitude V2 amp of fundamental wave components of line voltages of applied voltages of the second set of three-phase armature windings with respect to the power source voltage V de of the DC power source) of the measured DC-link voltage Vdc mesa and a DC-link reference voltage Vdc ref (para; 0049, lines 3-5, smoothing capacitor 12 suppresses and stabilizes variation of the DC voltage Vdc supplied to the first set of inverter 6a and the second set of inverter 6b) of each of said two or more series connected inverters is computed as a voltage ratio V dc meas/Vdc ref and wherein based on said computed voltage ratio, the PWM duty cycle of the respective cooling fan is updated (para; 0085, lines 4-13, the first set of voltage utilization factor M1 is a ratio of an amplitude V1 amp of fundamental wave components of line voltages of applied voltages of the first set of three-phase armature windings with respect to the power source voltage V dc of the DC power source. The second set of voltage utilization factor M2 is a ratio of an amplitude V2 amp of fundamental wave components of line voltages of applied voltages of the second set of three-phase armature windings with respect to the power source voltage Vdc of the DC power source).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding ratio of voltage as part of its configuration as taught by MORI, in order to set an effective value of a bus line AC superimposed on the bus current which flows through the bus line connecting between the DC power source V dc and the two sets of inverters.
Regarding claim 8, Dai disclose an arrangement for balancing DC-link voltages (fig. 4, DC-link 410, 412) arranged to supply power to an electric machine (404); each connected to a DC-link (fig. 4, DC-link 410, 412) of an inverter unit of said two or more series connected inverters (first inverter 424 and second inverter 426) and arranged to cool said inverter unit; and a master controller (supervisor controller 446) configured: to receive (para; 0166, The one or more memory device(s) 1010B can store information) measured DC-link voltages (para; 0072, lines 8-10, Particularly, with the symmetric topologies and PWM switching scheme, the voltage and current of the first inverter 424 and the second inverter 426) of two or more series connected inverters, to generate fan control data (para; 0166, The one or more memory device(s) 1010B can store information) and/or fan PWM control signaling (para; 0154, lines 5-9, first switches of the first inverter can mirror their respective corresponding second switches of the second inverter. The first switches can be pulse width modulated to generate first PWM signals, e.g., for each phase of power the first inverter is configured to output) for each of said two or more cooling fans based on said measured DC-link voltages, and to forward said fan control data (para; 0166, The one or more memory device(s) 1010B can store information) and/or said fan PWM control signaling (para; 0069) for controlling each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust).
But, Dai does not disclose two or more local controllers arranged to control each of said two or more cooling fans and further Dai in view of Mori does not disclose DC-link capacitors in series connected inverters comprising: two or more series connected inverters two or more individual inverter cooling fans.
However, MORI disclose two or more local controllers (fig. 2, 30a and 30b) arranged to control each of said two or more cooling fans and further Wei discloses DC-link capacitors (fig. 2, Cu, Cv, Cw are series with Ca, Cb, Cc) in series connected inverters comprising: two or more series connected inverters (fig. 2, (120-1, 120-2) and (110-1, 110-2)) two or more individual inverter cooling fans (para; 0019, two inverters 120-1 and 120-2 coupled with a shared single common mode choke 130 having four windings LA-LD in accordance with the disclosure with one or more blowers or cooling fans).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding two controllers as part of its configuration as taught by MORI, in order to detect high potential side bus line and the low potential side bus line to balance output signal, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai in view of MORI by adding one or more blowers or cooling fans to inverters as part of its configuration as taught by Wei, in order to remove excess heat from inverters, to prevent overheating and ensure optimal performance.
Regarding claim 9, Dai disclose said master controller is configured to generate fan PWM control signaling (para; 0069) for each of said two or more cooling fans, and to forward said fan PWM control signaling for controlling each of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust).
Regarding claim 10, Dai disclose said master controller is in every microcontroller cycle (para; 0165, The one or more processor(s) 1010A can include any processing device, such as a microprocessor, microcontroller, integrated circuit, logic device, and/or other suitable processing device)
But, Dai does not disclose configured to compute the ratio of the measured DC-link voltage Vdc measure and a DC-link reference voltage Vdc reference of each of said two or more series connected inverters as a voltage ratio Vdc measure and to update the PWM duty cycle of the V dc ref respective cooling fan based on said computed voltage ratio.
However, MORI disclose to compute the ratio (para; 0085, lines 4-13, the first set of voltage utilization factor M1 is a ratio of an amplitude V1 amp of fundamental wave components of line voltages of applied voltages of the first set of three-phase armature windings with respect to the power source voltage V dc of the DC power source. The second set of voltage utilization factor M2 is a ratio of an amplitude V2 amp of fundamental wave components of line voltages of applied voltages of the second set of three-phase armature windings with respect to the power source voltage V dc of the DC power source) of the measured DC-link voltage Vdc measure and a DC-link reference voltage Vdc reference (para; 0049, lines 3-5, smoothing capacitor 12 suppresses and stabilizes variation of the DC voltage Vdc supplied to the first set of inverters 6a and the second set of inverters 6b) of each of said two or more series connected inverters as a voltage ratio Vdc measure and to update the PWM duty cycle of the V dc ref respective cooling fan based on said computed voltage ratio (para; 0085, lines 4-13, the first set of voltage utilization factor M1 is a ratio of an amplitude V1 amp of fundamental wave components of line voltages of applied voltages of the first set of three-phase armature windings with respect to the power source voltage V dc of the DC power source. The second set of voltage utilization factor M2 is a ratio of an amplitude V2 amp of fundamental wave components of line voltages of applied voltages of the second set of three-phase armature windings with respect to the power source voltage V dc of the DC power source).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding ratio of voltage as part of its configuration as taught by MORI, in order to set an effective value of a bus line AC superimposed on the bus current which flows through the bus line connecting between the DC power source V dc and the two sets of inverters.
Regarding claim 11, Dai disclose said master controller is configured to generate fan control data (para; 0166, The one or more memory device(s) 1010B can store information) for each of said two or more cooling fans, and to forward said fan control data for controlling each of said two or more cooling fans (para; 0166, The one or more memory device(s) 1010B can store information), wherein said fan control data (para; 0166, The one or more memory device(s) 1010B can store information);
But, Dai does not disclose a DC-link reference voltage for each of said two or more series connected inverters.
However, MORI disclose a DC-link reference voltage (para; 0049, lines 3-5, smoothing capacitor 12 suppresses and stabilizes variation of the DC voltage Vdc supplied to the first set of inverters 6a and the second set of inverters 6b) for each of said two or more series connected inverters.
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding reference voltage as part of its configuration as taught by MORI, in order to stabilizes variation between the DC power source V dc and the two sets of inverters.
Regarding claim 12, Dai disclose receive (para; 0166, The one or more memory device(s) 1010B can store information) fan control data (para; 0166, The one or more memory device(s) 1010B can store information) from said master controller, to generate fan PWM control signaling (para; 0069) for a cooling fan of said two or more cooling fans (para; 0004, electrical power from one or more electric power sources may be provided to one or more electric machines to drive one or more fans to produce thrust) based on the difference between inverter DC-link voltage and said DC-link reference voltage received from said master controller, and to forward said fan PWM control signaling (para; 0069) to said cooling fan for controlling said cooling fan.
But, Dai does not disclose a local controller of said two or more local controllers controller,
However, MORI disclose a local controller (fig. 2, 30a and 30b) of said two or more local controllers controller,
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Dai by adding two controllers as part of its configuration as taught by MORI, in order to detect high potential side bus line and the low potential side bus line to balance output signal.
Regarding claim 13, Dai disclose said master controller is configured to activate said arrangement during a non-driving operation (para; 0062) period of the series connected inverters.
Regarding claim 14, Dai disclose said master controller (first inverter 424 and second inverter 426) is configured to deactivate said arrangement upon the start of the driving operation period of the series connected inverters (para; 0062).
Regarding claim 15, Dai disclose said master controller (supervisor controller 446) is configured to control one or more of the series connected inverters (first inverter 424 and second inverter 426).
Response to argument
Applicant’s argument filed on 7-8-25 with respect to claims 1-15 has been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAYAS G YESHAW whose telephone number is (571)270-1959. The examiner can normally be reached Mon-Sat 9AM-7PM.
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/ESAYAS G YESHAW/Examiner, Art Unit 2836
/REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836