DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter (i.e.; the embeddable tile is configured to be embedded into the package substrate of the semiconductor device so as to embed the plurality of passive devices into the package substrate without having to embed the passive devices into the package substrate individually as discrete components) which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Furthermore, the said limitation " without having to embed the passive devices into the package substrate individually as discrete components " is a negative limitation. Applicant attention is hereby directed to the fact that any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement (See MPEP § 2163 - § 2163.07(b) for a discussion of the written description requirement of 35 U.S.C. 112(a) and pre-AIA 35 U.S.C. 112, first paragraph). That is, any negative limitation or exclusionary proviso must have basis in the original disclosure See also Ex parte Grasselli, 231 USPQ 393 (Bd. App. 1983), aff’d mem., 738 F.2d 453 (Fed. Cir. 1984), which involved claims to a process for ammoxidation of propane or isobutene employing a catalyst “free of uranium and the combination of vanadium and phosphorous.” Under the particular facts in that case, it was held that the negative limitation introduced new concepts in violation of the description requirement of the first paragraph of 35 U.S.C. 112, citing In re Anderson, supra.
Claims 2-16 are also rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as being dependent on the rejected base claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (US 2024/0321759 A1 hereinafter referred to as "Wang").
With respect to claim 17, Wang discloses, in Figs.1-10, a package substrate of a semiconductor device, the package substrate comprising: a substrate core (206) (100)/(TVs 206 include in package core 100) (see Par.[0044]-[0051] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27; the substrate portions 110A, 110B and 110C may be referred to collectively as substrate portions 110; Although four substrate portions 110 (e.g., two substrate portions 110A, one substrate portion 110B and one substrate portion 110C) are shown in FIG. 1 having a particular size and a particular arrangement, the package structure 100 is not limited to any particular number, size or arrangement of the substrate portions 110; Par.[0070] wherein the molded interposer portion 22 may also include one or more through vias (TVs) 206 in the molding material layer 227); and a tile embedded in the substrate core (100), the tile including: a plurality of passive devices (200, 240), at least two of the passive devices being individually packaged for surface mounting on first sides thereof and having respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge); and a polymer layer (229, 329) surrounding the plurality of passive devices and having a planar surface, the planar surface being at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material; see Fig.3L wherein upper surface areas of 200, 240 are surrounded by underfill polymer 229, 329 respectively).
With respect to claim 18, Wang discloses, in Figs.1-10, the package substrate, wherein a thickness of the tile matches a thickness of the substrate core (10/100) (see Par.[0044]-[0051] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27; the substrate portions 110A, 110B and 110C may be referred to collectively as substrate portions 110. Although four substrate portions 110 (e.g., two substrate portions 110A, one substrate portion 110B and one substrate portion 110C) are shown in FIG. 1 having a particular size and a particular arrangement, the package structure 100 is not limited to any particular number, size or arrangement of the substrate portions 110).
With respect to claim 19, Wang discloses, in Figs.1-10, the package substrate, wherein the plurality of passive devices define a plurality of decoupling capacitors in relation to an integrated circuit to be mounted on the package substrate (see Par.[0060] wherein the IPDs may include one or more electronic components such as resistors, capacitors, inductors, coils, chokes, microstriplines, impedance matching elements, baluns, etc; the IPDs may be electrically coupled to the first semiconductor dies 141 through the back-side RDL interposer portion 21).
With respect to claim 20, Wang discloses, in Figs.1-10, the package substrate, wherein the plurality of passive devices define an integrated voltage regulator (IVR) in relation to an integrated circuit to be mounted on the package substrate (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi- passive integrated layer such as silicon bridge).
With respect to claim 21, Wang discloses, in Figs.1-10, a tile grid for manufacturing a plurality of tiles for embedding components (200, 240) into a package substrate (10/100) of a semiconductor device, the tile grid comprising: a frame (227) having a plurality of cutout regions defining a plurality of cells, each of the cells containing a plurality of passive devices (200, 240) and a printed circuit board (PCB) (21, 10, 40) on which the at least two passive devices (200, 240) are mounted (see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge; see Par.[0062]-[0063] wherein the molding material layer 227 may include an added material (e.g., filler material) for improving a property of the molding material layer 227 (e.g., thermal conductivity, CTE, etc.); see Par.[0154] wherein the underlayer 40 may include an underlayer molding material 427 and the components 41 and connectors 42 may be formed in the underlayer molding material 427; see Par.[0056]-[0057] wherein the back-side RDL interposer portion 21 may include a plurality of polymer layers 12 and a plurality of redistribution layers 12a stacked alternately; see Par.[0046] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27); and a plurality of polymer layers (229, 329) respectively filling the plurality of cells, each of the polymer layers surrounding the respective plurality of passive devices and having a planar surface (see Par.[0065], [0115] wherein the underfill layer 229 may then be formed under the LSI die 200 and around the microbumps 228; the underfill layer 229 may then be cured in an oven; see Par.[0069] wherein an underfill layer 329 may optionally be formed around the microbumps 328 and between the additional elements 240 and the front-side RDL interposer portion 23; and the optional underfill layer may be formed of an epoxy-based polymeric material; see Fig.3L wherein upper surface areas of 200, 240 are surrounded by underfill polymer 229, 329 respectively).
With respect to claim 22, Wang discloses, in Figs.1-10, the tile grid, wherein, in each of the cells, at least two of the passive devices (200, 240) are individually packaged for surface mounting on first sides thereof and have respective second sides opposite the first sides, the first sides of the at least two passive devices (200, 240) being aligned, the second sides of the at least two passive devices (200, 240) being at different heights relative to the aligned first sides, and, in each of the cells, the planar surface of the polymer layer is at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0044]-[0051] wherein the lower molded structure 10 may include one or more substrate portions 110A, 110B and 110C in a lower molding layer 27; the substrate portions 110A, 110B and 110C may be referred to collectively as substrate portions 110. Although four substrate portions 110 (e.g., two substrate portions 110A, one substrate portion 110B and one substrate portion 110C) are shown in FIG. 1 having a particular size and a particular arrangement, the package structure 100 is not limited to any particular number, size or arrangement of the substrate portions 110; see Par.[0064]-[0068] wherein the additional elements 240 may include, for example, one or more integrated voltage regulators (iVRs) for regulating a voltage in the package structure 100; the additional elements 240 may include, for example, one or more stand-alone IPDs to support signal communication with the first semiconductor dies 141; the molded interposer portion 22 may also include one or more local silicon interconnect (LSI) dies 200 (e.g., passive or semi-passive integrated layer such as silicon bridge); the molding material layer 227 may be formed around the LSI die 200 in the x-direction and y-direction; see Par.[0060] wherein one or more integrated passive devices (IPDs) (not shown) may be connected to the back-side RDL interposer portion 21 and located in the lower molding layer 27 of the lower molded structure 10; see Fig.3J wherein the height of iVRs 240 is greater than that of LSI 200).
With respect to claim 23, Wang discloses, in Figs.1-10, the tile grid, wherein, in each of the cells, the plurality of passive devices includes a stack of two or more unpackaged capacitors (see Par.[0060] wherein the IPDs may include one or more electronic components such as resistors, capacitors, inductors, coils, chokes, microstriplines, impedance matching elements, baluns, etc; the IPDs may be electrically coupled to the first semiconductor dies 141 through the back-side RDL interposer portion 21; see Fig.3L for stcked of packaging devices).
With respect to claim 24, Wang discloses, in Figs.1-10, the tile grid, wherein each of the cells further contains a plurality of metal terminals, the plurality of metal terminals including: two or more first metal terminals electrically isolated from each other and electrically connected to respective first electrodes of the two or more unpackaged capacitors; and a shared second metal terminal electrically connected to the second electrodes of the two or more unpackaged capacitors (see Par.[0070] wherein one or more through vias (TVs) 206 in the molding material layer 227. The TVs 206 may connect the front-side RDL interposer portion 23 to the redistribution layers 12a in the back-side RDL interposer portion 21. The TVs 206 may include, for example, one or more layers and may include metals, metal alloys, and/or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.)).
Claims 17-19, 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2016/0336296 A1 hereinafter referred to as "Jeong").
With respect to claim 17, Jeong discloses, in Figs.1-29, a package substrate of a semiconductor device, the package substrate comprising: a substrate core (110) (see Par.[0048] wherein an electronic component package 100A according to an example may include a frame 110 having a through-hole 110X, an electronic component 120 disposed in the through-hole 110X, an insulating part 150 at least covering upper portions of the frame 110 and the electronic component 120, a bonding part 111 at least partially disposed between the frame 110 and the insulating part 150, and redistribution parts 130 and 140 disposed below the frame 110 and the electronic component 120); and a tile embedded in the substrate core (110), the tile including: a plurality of passive devices (120, 124), at least two of the passive devices (120, 124) being individually packaged for surface mounting on first sides thereof and having respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown); and a polymer layer (150) surrounding the plurality of passive devices and having a planar surface, the planar surface being at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0069] wherein an insulating material may be used as a material of the insulating part 150; the insulating material includes polymer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as pre-preg, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an EMC, or the like, may also be used).
With respect to claim 18, Jeong discloses, in Figs.1-29, the package substrate, wherein a thickness of the tile matches a thickness of the substrate core (see Figs.24-25).
With respect to claim 19, Jeong discloses, in Figs.1-29, the package substrate, wherein the plurality of passive devices define a plurality of decoupling capacitors in relation to an integrated circuit to be mounted on the package substrate (see Par.[0043] wherein other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-firing ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), and the like).
With respect to claim 21, Jeong discloses, in Figs.1-29, a tile grid for manufacturing a plurality of tiles for embedding components into a package substrate of a semiconductor device, the tile grid comprising: a frame (110) having a plurality of cutout regions defining a plurality of cells, each of the cells containing a plurality of passive devices (124, 120) and a printed circuit board (PCB) (140) on which the at least two passive devices are mounted (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]- [0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown; see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed; see Par.[0048] wherein an electronic component 120 disposed in the through-hole 110X, an insulating part 150 at least covering upper portions of the frame 110 and the electronic component 120, a bonding part 111 at least partially disposed between the frame 110 and the insulating part 150, and redistribution parts 130 and 140 disposed below the frame 110 and the electronic component 120); and a plurality of polymer layers (150) respectively filling the plurality of cells, each of the polymer layers surrounding the respective plurality of passive devices and having a planar surface (see Par.[0069] wherein an insulating material may be used as a material of the insulating part 150; the insulating material includes polymer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as pre- preg, ABF, FR-4, BT, a PID resin, or the like. In addition, a known molding material such as an EMC, or the like, may also be used).
With respect to claim 22, Jeong discloses, in Figs.1-29, the tile grid, wherein, in each of the cells, at least two of the passive devices are individually packaged for surface mounting on first sides thereof and have respective second sides opposite the first sides, the first sides of the at least two passive devices being aligned, the second sides of the at least two passive devices being at different heights relative to the aligned first sides, and, in each of the cells, the planar surface of the polymer layer is at a height that is at least as great as the heights of the second sides of the at least two passive devices (see Par.[0057]-[0058] wherein the electronic component 120 may be various active components (such as a diode, a vacuum tube, a transistor, and the like) or passive components (such as an inductor, a condenser, a resistor, and the like); see Par.[0130]-[0131] wherein the passive component 124 may be, for example, an inductor, a condenser, a resistor, or the like, but is not limited thereto; see Fig.24, wherein 120 and 124 with different heights are shown; see Par.[0060] wherein the electronic component 120 within the through-hole 110X of the frame 110, the frame 110 may include any layer that is penetrated through by the through-hole 110X and has a distance from the redistribution parts 130 and 140 no more than a distance between an upper surface of the electronic component 120 opposing to a lower surface thereof on which the electrode pads 120P are formed).
Response to Arguments
Applicant's arguments filed 08/12/2026 regarding claim 17have been fully considered but they are not persuasive.
For example, Applicant alleges that Wang’s package structure 100 and/or molded structure 10 substrate core elements cannot represent claimed limitation of “substrate core” because substrate core is not a molding compound (see remarks, page 11). Examiner disagrees. Wang package structure representing the core substrate also includes TVS 206 within which passives devices 240, 200 are embedded. In response to applicant's argument that Wang fails to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., not molded compound as substrate core) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Moreover, the limitation of “substrate core” is a preamble limitation. As such, Applicant attention is also directed to the fact that if the body of a claim fully and intrinsically sets forth all of the limitations of the claimed invention, and the preamble merely states, for example, the purpose or intended use of the invention, rather than any distinct definition of any of the claimed invention’s limitations, then the preamble is not considered a limitation and is of no significance to claim construction. Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See also Rowe v. Dror, 112 F.3d 473, 478, 42 USPQ2d 1550, 1553 (Fed. Cir. 1997) ("where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention, the preamble is not a claim limitation"); Kropa v. Robie, 187 F.2d at 152, 88 USPQ2d at 480-81 (preamble is not a limitation where claim is directed to a product and the preamble merely recites a property inherent in an old product defined by the remainder of the claim); STX LLC. v. Brine, 211 F.3d 588, 591, 54 USPQ2d 1347, 1350 (Fed. Cir. 2000) (holding that the preamble phrase "which provides improved playing and handling characteristics" in a claim drawn to a head for a lacrosse stick was not a claim limitation). Compare Jansen v. Rexall Sundown, Inc., 342 F.3d 1329, 1333-34, 68 USPQ2d 1154, 1158 (Fed. Cir. 2003) (In a claim directed to a method of treating or preventing pernicious anemia in humans by administering a certain vitamin preparation to "a human in need thereof," the court held that the preamble is not merely a statement of effect that may or may not be desired or appreciated, but rather is a statement of the intentional purpose for which the method must be performed. Thus the claim is properly interpreted to mean that the vitamin preparation must be administered to a human with a recognized need to treat or prevent pernicious anemia.); In re Cruciferous Sprout Litig., 301 F.3d 1343, 1346-48, 64 USPQ2d 1202, 1204-05 (Fed. Cir. 2002) (A claim at issue was directed to a method of preparing a food rich in glucosinolates wherein cruciferous sprouts are harvested prior to the 2-leaf stage. The court held that the preamble phrase "rich in glucosinolates" helps define the claimed invention, as evidenced by the specification and prosecution history, and thus is a limitation of the claim (although the claim was anticipated by prior art that produced sprouts inherently "rich in glucosinolates”).
Furthermore, contrary of Applicant allegation (in remarks page 12) with respect to Jeong not disclosing package core. Examiner submits that package core of Jeong is 110 (see Fig.24). All response to arguments as set forth above regarding Wang are used for Jeong.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
