DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-20 are pending; claims 1 and 18 are independent.
Response to Arguments
Applicant's arguments filed 03/09/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument that “amended claim 1 requires "a control end of the charging module is electrically connected to a first control signal line" and "a first end of the charging module is electrically connected to the control end of the charging module, as recited in alims 1 and 18. " The claim thus requires a dedicated first control signal line, not a sequential stage output, connected to both the control end and the first end of the charging module.
However, the examiner respectfully disagrees, the claim required both control end and a first end of the charging module connected to a first control signal but no specific language to determine what kind or type of the first control signal.
In response to applicant's argument in pages 2-4, that “Importing Xiao's T1 diode-connection into Watanabe would require re-wiring Watanabe's transistor 107 such that its gate is connected to wiring 124[n-1] instead of wiring 121. This is not an obvious and predictable modification, it would fundamentally alter the function of Watanabe's transistor 107 and require dismantling the circuit 14 bootstrap sub-circuit.”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's arguments in pages 4-5 “First, Xiao's T5 is not an initialization module of a boost unit ….” against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant’s argument in page 5 that Second, in Xiao, the "first control signal line" equivalents are sequential stage output signals, not dedicated control lines.
However, the examiner respectfully disagrees, the claim required a control end of the initialization module is electrically connected to the first control signal line but no specific language to determine what kind or type of the first control signal.
In response to applicant's argument in pages 5-6, that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Third, the claimed topology creates a specific timing relationship absent from Xiao. Amended claim 1 requires that the first control signal line controls the control end of the charging module and, separately, the control end of the initialization module, meaning both the charging operation and the initialization operation are governed by the same dedicated control signal…) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's argument in page 6, that “Xiao's entire architecture is predicated on a cascaded shift register where each stage receives the sequential output of the preceding stage. The claimed boost unit, by contrast, is a standalone circuit in the non-display area that receives dedicated control signal lines, not sequential stage outputs.”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument in pages 6-7, that “Transplanting Xiao's T1 diode topology and T5's stage-signal-controlled gate into Watanabe's boost circuit would require not simply adding a feature, but fundamentally rewiring Watanabe's transistor 107 and transistor 105 in a manner that is inconsistent with the operation of Watanabe's bootstrap sub-circuit. This is not a known technique yielding a predictable result, it is a substantial structural redesign with unpredictable consequences for the boosting function”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument in page 7 that “Third, the references teach away from the combination. Watanabe's transistor 107 functions as a diode by having its gate connected to the high potential line 121, not to the scan line 124[n-1]…” the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument Pages 7-8 that “As shown above, neither Watanabe nor Xiao, alone or in combination, teaches a boost unit in which (1) the first end of the charging module is connected to the control end of the charging module and (2) the control end of the initialization module is connected to the same first control signal line that controls the charging module. These are the structural features that enable the claimed boost circuit to function in the recited manner, and the Office has not identified any teaching in either reference that achieves this specific structural topology in a boost circuit context”., a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2022/0108666), and further in view of Xiao (US 2016/0351140).
Regrading claim 1, Watanabe teaches a display panel, (fig. 1) comprising a display area (fig. 1, a pixel array 18) and a non-display area (fig. 1, a part of the display panel where a circuits 13, a source driver 11, and a gate driver 12 located), wherein:
the display area includes a plurality of pixel units and a plurality of gate lines electrically connected to the plurality of pixel units (fig. 1 and Para 0060, wherein the plurality of pixels 10 are provided to form a pixel array 18);
the non-display area includes a boost circuit including a plurality of boost units, a boost unit of the plurality of boost units is electrically connected to at least one of the plurality of gate lines, and the boost circuit is configured to boost a voltage on the at least one gate line above a voltage provided by a gate driver electrically connected to the boost circuit (fig. 1, the circuit 13 and Paras 0061-0062, wherein the circuit 13 is a boosting circuit and has a function of boosting a signal voltage for driving the pixel which is supplied from the gate driver 12);
the boost unit (fig. 3A) of the plurality of the boost units includes a charging module (fig. 3A, transistor 107), a bootstrap module (fig. 3A, combination of elements transistor 102 and capacitor 108), and an initialization module (fig. 3A, transistor 105 that are electrically connected, the bootstrap module at least includes a first module (fig. 3A, transistor 102) and a first capacitor (fig. 3A, capacitor 108);
a control end of the charging module is electrically connected to a first control signal line (fig. 3A, and para 0125, wherein a gate of the transistor 107 is electrically connected to the wiring 121) and a second end of the charging module is electrically connected to a gate line, a control end of the first module, and a first electrode of the first capacitor respectively (fig. 3A, and Para 0124, wherein the other of the source/drain of the transistor 107 is electrically connected to one electrode of the capacitor 108 and the gate of the transistor 102 and output terminal 125 through the capacitor 108);
a first end of the first module (fig. 3A, transistor 102) is electrically connected to a second control signal line (fig. 3A and Para 0125, wherein the other of the source/drain of the transistor 102 is electrically connected to the wiring 123) and a second end of the first module is electrically connected to a second electrode of the first capacitor (fig. 3A wherein the one source or drain of transistor 102 connected to another electrode of capacitor 108);
a first end of the initialization module (fig. 3A, the transistor 105) is electrically connected to the second electrode of the first capacitor (fig. 3A wherein the one source or drain of transistor 105 connected to another electrode of capacitor 108 via a capacitor 108), and
a second end of the initialization module is electrically connected to a first negative potential signal line (fig. 3A wherein the one source or drain of transistor 105 connected to the wiring 122); and
a potential value provided by the second control signal line is greater than a potential value provided by the first negative potential signal line (Paras 0069 and 0125, wherein the wiring 121 can function as a high potential power supply line, and the wiring 122 can function as a low potential power supply line and wiring 123 is a power supply line for supplying a potential higher than or equal to the potential of the wiring 121).
Watanabe does not expressly disclose a first end of the charging module is electrically connected to the control end of the charging module and a control end of the initialization module is electrically connected to the first control signal line.
However, Xiao discloses “a first end of the charging module is electrically connected to a control end of the charging module (fig. 2, T1) and a control end of the initialization module is electrically connected to the first control signal line (fig. 2, T5 and Para 0049).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a display panel of Watanabe with the teaching of Xiao to include both a gate and a drain of a first transistor are electrically coupled to an activation signal end STV of the circuit, and gate of the fifth transistors T5 are electrically coupled to the activation signal end STV of the circuit, as a known technique to yield a predictable result.
Regrading claim 2, Watanabe in view of Xiao teaches the display panel according to claim 1, wherein: the first control signal line provides a first control signal value, under a control of the first control signal value, the first end and the second end of the charging module are conductive, the first end and the second end of the initialization module are conductive, the first control signal value is transmitted to the gate line, the control end of the first module, and the first electrode of the first capacitor respectively, and the potential value provided by the first negative potential signal line is transmitted to the second electrode of the first capacitor; under the control of the first control signal value, the first end and the second end of the first module are connected; and the second control signal line provides a second control signal value, the second control signal value is transmitted to the second electrode of the first capacitor, a potential of the second electrode of the first capacitor is increased, and a potential of the first electrode of the first capacitor is increased by coupling with the second electrode of the first capacitor (fig. 3A and Paras 0123-0129, wherein the bootstrap operation is as follows. First, when a potential “H” is input to a node C (a wiring to which the other of the source and the drain of the transistor 107, the one electrode of the capacitor 108, the gate of the transistor 102, and the gate of the transistor 105 are connected) through the transistor 107, current flows through the transistor 102 until the potential of the node A increases from “L” to “H”. At this time, since the potential of the node C is increased to “H” or higher due to capacitive coupling of the capacitor 108, more current flows through the transistor 102; thus, the potential of the node A can be increased further. Note that the potential “H” is supplied to the one of the source and the drain and the gate of the transistor 107. When the potential of the other of the source and the drain of the transistor 107 (the node C) is higher than “H”, current does not flow to the transistor 107. That is, the transistor 107 functions as a diode. Watanabe).
Regrading claim 3, Watanabe in view of Xiao teaches the display panel according to claim 1, wherein: the charging module includes a first transistor (fig. 3A, a transistor 107), the first module includes a second transistor (fig. 3A, a transistor 102), and the initialization module includes a third transistor (fig. 3A, a transistor 105, Watanabe);
a gate of the first transistor is electrically connected to the first control signal line (fig. 3A, and para 0125, wherein a gate of the transistor 107 is electrically connected to the wiring 121, Watanabe), a drain of the first transistor is electrically connected to the gate line, and a gate of the second transistor, and the first electrode of the first capacitor, respectively (fig. 3A, and Para 0124, wherein the other of the source/drain of the transistor 107 is electrically connected to one electrode of the capacitor 108 and the gate of the transistor 102 and output terminal 125 through the capacitor 108, Watanabe);
a source of the second transistor is electrically connected to the second control signal line (fig. 3A and Para 0125, wherein the other of the source/drain of the transistor 102 is electrically connected to the wiring 123, Watanabe), and a drain of the second transistor is electrically connected to the second electrode of the first capacitor (fig. 3A wherein the one source or drain of transistor 102 connected to another electrode of capacitor 108, Watanabe); and
a source of the third transistor is electrically connected to the second electrode of the first capacitor (fig. 3A wherein the one source or drain of transistor 105 connected to another electrode of capacitor 108 via a capacitor 106, Watanabe), and a drain of the third transistor is electrically connected to the first negative potential signal line (fig. 3A wherein the one source or drain of transistor 105 connected to the wiring 122, Watanabe).
Watanabe in view of Xiao a source of the first transistor is electrically connected to the gate of the first transistor (fig. 2, T1, Xiao) and a gate of the third transistor is electrically connected to the first control signal line (fig. 2, T5 and Para 0049, Xiao).
Regrading claim 17, Watanabe in view of Xiao teaches the display panel according to claim 1, wherein: the plurality of gate lines extends along a first direction (fig. 1, a wiring 125 and Para 0062, Watanabe), and along the first direction, the non-display area includes a first non-display area (fig. 15A, the scan line driver circuit 221a, Watanabe ) and a second non-display area (fig. 15A, the common line driver circuit 241a, Watanabe ) on opposite sides of the display area (fig. 15A and Paras 0212-0214, Watanabe); and
the boost circuit is in the first non-display area and/or the second non-display area (fig. 1, the circuit 13 and Paras 0061-0062, Watanabe).
Regrading claim 18, Watanabe teaches a display panel (fig. 1), comprising a display area (fig. 1, a pixel array 18) and a non-display area (fig. 1, a part of the display panel where a circuits 13, a source driver 11, and a gate driver 12 located), wherein:
the display area includes a plurality of pixel units and a plurality of gate lines electrically connected to pixel units (fig. 1 and Para 0060, wherein the plurality of pixels 10 are provided to form a pixel array 18);
the non-display area includes a potential boost circuit including a plurality of boost units, a boost unit of the plurality of the boost units is electrically connected to at least one of the plurality of gate lines, and the boost circuit is configured to boost a voltage on the at least one gate line above a voltage provided by a gate driver electrically connected to the boost circuit (fig. 1, the circuit 13 and Paras 0061-0062, wherein the circuit 13 is a boosting circuit and has a function of boosting a signal voltage for driving the pixel which is supplied from the gate driver 12);
the boost unit of the plurality of the boost units (fig. 1, the circuit 13) includes a first transistor (fig. 3A, a transistor 107), a second transistor (fig. 3A, a transistor 102), a third transistor (fig. 3A, a transistor 105) and a first capacitor that are electrically connected (fig. 3A, a capacitor 108);
a gate of the first transistor is electrically connected to a first control signal line(fig. 3A, and para 0125, wherein a gate of the transistor 107 is electrically connected to the wiring 121), a drain of the first transistor is electrically connected to the gate line, a gate of the second transistor, and a first electrode of the first capacitor, respectively (fig. 3A, and Para 0124, wherein the other of the source/drain of the transistor 107 is electrically connected to one electrode of the capacitor 108 and the gate of the transistor 102 and output terminal 125 through the capacitor 108);
a source of the second transistor is electrically connected to a second control signal line (fig. 3A and Para 0125, wherein the other of the source/drain of the transistor 102 is electrically connected to the wiring 123), and a drain of the second transistor is electrically connected to a second electrode of the first capacitor (fig. 3A wherein the one source or drain of transistor 102 connected to another electrode of capacitor 108);
a source of the third transistor is electrically connected to the drain of the second transistor (fig. 3A wherein the one source or drain of transistor 105 connected to the source/drain of transistor 102 via a capacitor 106), and a drain of the third transistor is electrically connected to a first negative potential signal line (fig. 3A wherein the one source or drain of transistor 105 connected to the wiring 122); and
a potential value provided by the second control signal line is greater than a potential value provided by the first negative potential signal line (Paras 0069 and 0125, wherein the wiring 121 can function as a high potential power supply line, and the wiring 122 can function as a low potential power supply line and wiring 123 is a power supply line for supplying a potential higher than or equal to the potential of the wiring 121).
Watanabe does not expressly disclose a source of the first transistor is electrically connected to the gate of the first transistor and a gate of the third transistor is electrically connected to the first control signal line.
However, Xiao discloses “a source of the first transistor is electrically connected to the gate of the first transistor (fig. 2, T1) and a gate of the third transistor is electrically connected to the first control signal line (fig. 2, T5 and Para 0049).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a display panel of Watanabe with the teaching of Xiao to include both a gate and a drain of a first transistor are electrically coupled to an activation signal end STV of the circuit, and gate of the fifth transistors T5 are electrically coupled to the activation signal end STV of the circuit, as a known technique to yield a predictable result.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2022/0108666), in view of Xiao (US 2016/0351140), and further in view of Liu (US 2009/0284706).
Regrading claim 16, Watanabe in view of Xiao teaches the display panel according to claim 1, but Watanabe in view of Xiao does not expressly disclose wherein the non-display area includes a bonding area, the bonding area includes a plurality of conductive pads, and the plurality of gate lines is electrically connected to the plurality of conductive pads.
However, Liu discloses “wherein the non-display area includes a bonding area, the bonding area includes a plurality of conductive pads, and the plurality of gate lines is electrically connected to the plurality of conductive pads”, see fig. 3, a bonding area 360 and pads 365 and Paras 0021-0022.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display panel of Watanabe in view of Xiao with the teaching of Liu to include a bonding area comprises a plurality of bonding pads that coupling to one corresponding gate line, as a known technique to yield a predictable result.
Allowable Subject Matter
Claims 4-15 are allowed.
The prior art either alone or in obvious combination does NOT teach ALL of the above limitations including:
wherein: the boost unit also includes a strobe module, a control end of the strobe module is electrically connected to a data line, a first end of the strobe module is electrically connected to the second control signal line, and a second end of the strobe module is electrically connected to the first end of the first module, as recited in claim 4.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art either alone or in obvious combination does NOT teach ALL of the above limitations including:
wherein: the boost unit further includes a fourth transistor; and a gate of the fourth transistor is electrically connected to a data line, a source of the fourth transistor is electrically connected to the second control signal line, and a drain of the fourth transistor is electrically connected to the source of the second transistor, as recited in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kaneyasu (US 2013/0278324), relates to a semiconductor device. The present invention relates to an image display device, a storage device, and an electronic device each including the semiconductor device.
Tsai (US 2011/0116592), relates generally to a shift register, and more particularly, to a shift register with low power consumption for a display.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.E/Examiner, Art Unit 2625 3/25/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625