CTNF 18/409,286 CTNF 74348 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. The preliminary amendment filed on 1/20/24 is acknowledge. Claims 21-25 are canceled, claims 1-20 are pending and being examined. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-31-02 AIA Claim s 10 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 10 recites the limitation “… when the first core is active and the second core is inactive a clock value of the first core is fixed and a clock value of the second core varies based on the power parameter” (emphasis added). Though the specification provides support for frequency control for each core as being either fixed or variable, and the core having different power state (par. 70); there is no specific description of the causal relationship of the “ when cores are active and inactive” and operating in such a way that “the clock value of the first core is fixed and the clock value of the second core varies”. Nothing in the specification provide any support for the operation in the particular manner as claimed (i.e. fixed clock during active and varies clock during inactive). Thus the specification failed to provide sufficient support to enable one skilled in the art to make and use the claim. Claim 19 is rejected for having similar feature as in claim 1 a method form. Correction/clarification required . 07-30-02 The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 10 recites “ a clock value” ; however, it is unclear if this “clock value “ is the same as “ a clock value” of claim 1. The claim fails to provide a correlation between “a clock value” of claim 1 and “a clock value’ of claim 10. Also, claim 10 appears to be a run-on sentence which render the claim unclear. In addition, as discussed in the 35 USC 112 (a) above, it is unclear what applicant intend to cover in claim 10 and 19 as it is not clear how the active/inactive state of the first and second core relate to the “fixed and variable” clock values, thus the metes and bounds of the claim are unclear . As best understood based on the par. 71, the cores power state and frequency control values can be set in different modes or value respectively based on the DVFS. Correction/clarification required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-9, 11-13, and 15-17 and 20 is/are rejected under 35 U.S.C. 102 (a)(1) and/or(a)(2) as being anticipated by Kim 20210116955 Claim 1. Kim teaches a storage device [ Fig. 1-20, par. 35-37, 95, hardware memory, load/store unit, data processing device/storage device ] comprising: at least one nonvolatile memory device including at least one internal component [ Fig. 20, working memory 3250-3255 among other components, see also par. 42-43, 95] ; and a controller configured to control the at least one nonvolatile memory device [ Fig. 1, par. 30, processor/memory controller ] wherein the controller includes a parameter storage [ Fig. 17-18, registers, lookup table LUT] configured to store a power parameter performance indicating a clock value of each of a plurality of internal configurations for each power state of each of the at least one internal component storage [ par. 85-87, LUT may include control information, power states include voltage and clock control information, par. 60, receives a count value CNT1 and the clock signal ICK, a frequency division clock signal ; par. 37-40, state value of the clock gating signals EN based on the operating voltage and are used to reduce a power of the a component; par. 48-49, linear regression calculator, register 222 storing the linear regression coefficients ] wherein the power parameter is derived by performing a machine learning operation using a machine learning model trained to output the power parameter based on performance, peak power, and average power of the storage device [ Fig. 1-11, par. 31-34, 45-50, DMP calculator 200 provide DMP-OUT’ PMP 200 includes power calculator 220/220a includes a linear regression calculator 221 and a machine learning encoder 223 to perform dynamic voltage and frequency scaling (DVFS) based on state values, power classification value from a minimum to a maximum power, average value] Claim 2. Kim teaches the storage device of claim 1, wherein the power state of each of the at least one internal component is one of an active state, a background operating state, an idle state, or a sleep state [ Fig. 19-20, internal components , par. 69, active or inactive, idle; par. 40, a dynamic power consumed at the core 100, and there is a correlation between a state value and a dynamic power ]. Claim 3. Kim teaches the storage device of claim 1, wherein the clock value is adjusted using at least one of a clock division value, a clock gating value, or a clock gearing value [ par. 60, divider, par. 70 clock gating ] Claim 4. Kim teaches the storage device of claim 1, wherein the machine learning operation is performed in an external device of the storage device [ par. 49, registers 222 may be updated to values transmitted from a user or an external device, par. 53-54 and 58 pre-processed result stored and update in advance] Claim 5. Kim teaches the storage device of claim 4, wherein the external device includes processing circuitry configured to monitor the peak power and the average power according to a workload of the storage device; [ Fig. 3-11 par. 57-58, 38-40, 60-61 and 69-70 as discussed in claim 1] derive a scalar value in which the performance, the peak power, and the average power are synthesized according to the workload of the storage device [ par. 31-34, regulator 130 and management unit 140 may scale (or regulate) operating voltage and frequency based on the monitoring result, Fig. 17-18] ; and derive the power parameter by performing the machine learning operation based on the scalar value [ par. 31-34, DVFS management ]. Claim 6. Kim teaches the storage device of claim 5, wherein the processing circuitry is configured to determine the scalar value according to an equation [ par. 39, equation]. Claim 7. Kim teaches the storage device of claim 1, wherein the machine learning operation is performed inside the storage device [ par. 56, in a different embodiment, IC 10 may include a processor that generates the result of the gate level simulation and the result of the power analysis]. Claim 8. Kim teaches the storage device of claim 7, wherein the storage device includes processing circuitry configured to perform the machine learning operation in response to a request from a host device [Fig. 9, par 58-59, electronic device/IC 10 having processor executed the simulation of Fig. 9] Claim 9. Kim teaches the storage device of claim 8, the rest of the claim recites the same limitations as in claim 5 and rejected accordingly. Regarding claim 11, Kim teaches a method of operating a storage device [ [Fig. 1-20, par. 95, data processing device] ], the method comprising: setting a power parameter using machine learning [ Fig. 3-11 and associated description especially par. 57-58, 38-40, neural network/machine learning, i.e. power calculator 220 to analyze power monitored based on static and dynamic power monitor on performance ]; and adjusting a frequency of at least one active or inactive device based on the set power parameter , wherein the adjusting of the frequency includes at least one of dividing a clock corresponding to the frequency, gating the clock, or gearing the clock [ , [par. 31-34, regulator 130 and management unit 140 may scale (or regulate) operating voltage and frequency based on the monitoring result, Fig. 17-18 ] Claim 12. Kim teaches the method of claim 11, wherein setting the power parameter includes deriving, in an external device, the power parameter using the machine learning. [par. 49, registers 222 may be updated to values transmitted from a user or an external device, par. 53-54 and 58 pre-processed result stored and update in advance] Claim 13. Kim teaches the method of claim 12, the rest of the claim repeats the limitation of claim 5 and therefore rejected accordingly. Claim 15. Kim teaches the method of claim 11, wherein setting the power parameter includes performing a machine learning operation in internal processing circuitry in response to a request from a host device [Fig. 9, par 58-59, electronic device/IC 10 having processor executed the simulation of Fig. 9]. Regarding claim 16. A method of operating a storage device, the method comprising: receiving a machine learning execution request from a host device [ [Fig. 9, par 58-59, electronic device/IC 10 having processor executed the simulation of Fig. 9] performing a machine learning operation in response to the machine learning execution request [Fig. 9. steps 104-108] and setting a parameter according to a result of execution of the machine learning operation [ Fig. 1, step 110 ], wherein the parameter is a value derived considering performance, peak power, and average power [ Fig. 3-11 and associated description especially par. 57-58, 38-40, neural network/machine learning, i.e. power calculator 220 to analyze power monitored based on static and dynamic power monitor on performance (i.e. peak, see Fig. 4, par. 69-70) and average (par. 60-61)] [ Fig. 1-11, par. 31-34, 45-50, (DVFS) based on state values, power classification value from a minimum to a maximum power, average value] Claim 17. The method of claim 16, wherein the parameter indicates a clock value for each of a plurality of internal components of the storage device par. 31-34, regulator 130 and management unit 140 may scale (or regulate) operating voltage and frequency based on the monitoring result, Fig. 17-18] , and wherein setting the parameter includes adjusting the clock value using at least one of a clock division value, a clock gating value, or a clock gearing value. [ par. 60, divider, par. 70 clock gating; par. 31-34, DVFS management]. Claim 18. Kim teaches the method of claim 16, wherein the parameter indicates quality parameters determining a service quality, and the quality parameters include at least two of a program operation parameter, a buffer size, a core clock, firmware policy, or performance margin [ Fig. 2-4, 11; par. 3-4, 31-34, 39-40, thermal policy DFVS ]. 20. The method of claim 16, further comprising: receiving the performance and the power consumption of the storage device [ Fig. 9, S310-320, Fig. 10-11 ], deriving a scalar value in which the performance and the power consumption for each workload are synthesized [ par. 60, divider, par. 70 clock gating ] ; and performing the machine learning operation using the derived scalar value. [ par. 49, registers 222 may be updated to values transmitted from a user or an external device, par. 53-54 and 58 pre-processed result stored and update in advance] . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim . Based on the 35 USC 112 rejections above, as best understood based on the par. 71, claims 10 and 19 are interpreted as the cores power state and frequency control values can be set in different modes or value respectively based on the DVFS. Claim 10, Kim teaches the storage device of claim 1, wherein the at least one internal component includes a first core and a second core [ Fig. 2, 16, 10, core 1011-1014 , CPU GPU clusters ] and when the first core is active and the second core is inactive [ Fig. 17 , par. 43 , core enable/disable, par. 84-86, 90, each core include respective DMP, control signal CTRL 1-4 for different state] , and a clock value is provided to each of the core to control the operation of the core [ Fig. 18 , par. 87 and 90 each of the control information CTRL may include information indicating target frequency of the clock signal ICK]. Kim does not explicitly disclose a value of the first core is fixed and a clock value of the second core varies based on the power parameter. However, Kim teaches [ par. 93-94 CPU and GPU perform DVFS operation independently from each other ]. It would have been obvious to one having ordinary skill in the art to recognized that the clock value for each core would be set based on the DVFS and a frequency of the clock signal ICK1 and a frequency of the clock signal ICK2 may be independently calibrated based on its operating level [ par. 93 ]. Claim 19. Kim teaches the method of claim 16, determine the power state of the first and second core [ par. 85 ] the rest of the claim repeats the limitation of claim 2 and therefore rejected accordingly . 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim 20210116955 in view of NPL titled “Bayesian Optimization” Claim 14. Kim teaches the method of claim 13 but does not specify the machine learning is configured to use a Bayesian optimization. Applicant discloses the formula is based on the well-known Bayesian optimization which is a known formula. In addition, NPL teaches Bayesian optimization formula [ see formulas in methodology and numerical example ] uses a surrogate function to estimate the objective through sampling that represent as probability distributions which can be updated in light of new information to evaluate the probability of exploring a certain point. It would have been obvious to one having ordinary skill in the art to implement Bayesian optimization approach in order to take advantage of the powerful and efficient approach to optimizing complex functions, particularly when evaluations are expensive, noisy, or time-consuming [ NPL , Introduction ] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM HUYNH whose telephone number is (571)272-4147. The examiner can normally be reached M-Th 6:00am-4:0pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAWEED ABBASZADEH can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KIM HUYNH/ Primary Patent Examiner, Art Unit 2176 Application/Control Number: 18/409,286 Page 2 Art Unit: 2176 Application/Control Number: 18/409,286 Page 3 Art Unit: 2176 Application/Control Number: 18/409,286 Page 4 Art Unit: 2176 Application/Control Number: 18/409,286 Page 5 Art Unit: 2176 Application/Control Number: 18/409,286 Page 6 Art Unit: 2176 Application/Control Number: 18/409,286 Page 7 Art Unit: 2176 Application/Control Number: 18/409,286 Page 8 Art Unit: 2176 Application/Control Number: 18/409,286 Page 9 Art Unit: 2176 Application/Control Number: 18/409,286 Page 10 Art Unit: 2176 Application/Control Number: 18/409,286 Page 11 Art Unit: 2176 Application/Control Number: 18/409,286 Page 12 Art Unit: 2176
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