DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 7 is canceled, claims 1-6, and 8-20 are pending and being examined.
Response to Arguments
Applicant’s arguments filed on 9/15/26 have been considered but are moot because the new ground of rejection in light of the amended features.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5-6 and 8rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recite a storage device comprising a processing circuitry to perform a machine learning operation (i.e. the processing device is part of the storage device). Claim 5, however, recites that the processing circuitry is in an external device that is external to the storage device. Thus, claims 1 and 5 are contradictory and render the claim unclear and indefinite.
Claims 6 and 8 depend from claim 5 and therefore inherit the same deficiency.
Correction/clarification required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim 20210116955 in view of Narayanaswamy; US 20240094796 A1
Claim 1. Kim teaches a storage device [Fig. 1-20, par. 35-37, 95, electronic device 10/1000/3000 maybe a server, a data processing device, memory system] comprising:
at least one nonvolatile memory device including at least one internal component [Fig. 1-2 and par. 16, 19-20, par. 29-30, 35-37, 84, 95; integrated circuit 10 having multiple digital circuits; referred to as a memory device and having internal components]; and
a controller configured to control the at least one nonvolatile memory device [Fig. 1-2, 16-20, controller circuit include IVR and CMU connecting to memory device via memory controller 2330, see Fig. 16] ,
the controller including a parameter storage [registers 222] configured to store power parameter indicating a clock value of each of a plurality of internal configurations for each power state of each of the at least one internal component [par. 45, 49, 53-55, registers 222 configured to store a power parameter shown in table 1 in includes CLK value ICK and corresponding power state P, outputs from operation S130 may be stored or updated in advance in the registers 222]
processing circuitry [dynamic power monitor DPM 200] configured to perform a machine learning operation using a machine learning model trained to output the power parameter using inputs, [par. 51, 59, DPM monitor power and provide output to IVR 130 and CMU 140 result of the gate level simulation and the result of the power analysis, i.e. result of operation S320 and 130, are stored in storage device, result of operation in Fig. 3 and 6 are stored , see also par. 44 and 44, 58; deep neural network and machine learning executable by a power calculator power calculator]; the inputs based on performance, and power of the storage device [par. 31 and 43, DPM 200 monitors a power of the IC or bock 100 every cycle of the clock signal ICK. See Fig. 2, DPM having inputs including IVDD, ICK, EN, CORE, TMP which are based on performance, average temperature and peak temperature, TMP limit, i.e. peak power]
wherein the power parameter is derived by performing the machine learning operation using the machine learning model [Fig. 1-8, DPM-OUT is provided to IVR and CMP, DMP performs deep neural network (DNN) classification model executable by the machine learning. 57-58, 61-61]
Though Kim does not explicitly disclose the inputs IVDD, ICK, EN, CORE, TMP of DPM are related to the DPM include performance, peak and average power.
In the alternative, Narayanaswamy teaches techniques to optimize overall performance of a data center [Fig. 1] of a group of processors includes decreasing one or more clock frequencies of that group of processors to avoid exceeding a power consumption budget for those processors using machine learning model [par. 69, 75] machine learning models 106a-n are models optimized to allow a group of processors to perform applications] wherein the model include functions that uses telemetry data, such as workload factor, and/or user input including for setting power budget wherein the setting thresholds include maximum, minimum, optimum values associated with one or more processors, such as power delivery values or workload factor values [par. 52, 69; controller 102 sets threshold values based on one or more functions that include as inputs values associated with a processor, such as power, leakage power, dynamic power, average power, voltage, capacitance, dynamic capacitance, temperature, frequency, clock speed, activity factor, workload factor, number of processors in a group]. It would have been obvious to one having ordinary skill in the art before the effective filing date to implement the teaching of Narayanaswamy to optimize performance while avoid exceeding a power consumption [par. 52, 71]
Claim 2. Kim teaches the storage device of claim 1, wherein the power state of each of the at least one internal component is one of an active state, a background operating state, an idle state, or a sleep state [Fig. 19-20, internal components, par. 69, active or inactive, idle; par. 40, a dynamic power consumed at the core 100, and there is a correlation between a state value and a dynamic power].
Claim 3. Kim teaches the storage device of claim 1, wherein the clock value is adjusted using at least one of a clock division value, a clock gating value, or a clock gearing value [par. 60, divider, par. 70 clock gating]
Claim 4. Kim teaches the storage device of claim 1, wherein the machine learning operation is performed in an external device of the storage device [as best understood, par. 49, registers 222 may be updated to values transmitted from a user or an external device, par. 53-54 and 58 pre-processed result stored and update in advance].
Claim 5. The combination of Kim teaches the storage device of claim 4, wherein the processing circuitry configured to monitor the peak power and the average power according to a workload of the storage device; [Kim, Fig. 3-11 par. 57-58, 38-40, 60-61 and 69-70 as discussed in claim 1. Narayanaswamy, par. 57]
derive a scalar value in which the performance, the peak power, and the average power are synthesized according to the workload of the storage device [par. 31-34, regulator 130 and management unit 140 may scale (or regulate) operating voltage and frequency based on the monitoring result, Fig. 17-18, Narayanaswamy, par. 51, 57 and 265]; and
derive the power parameter by performing the machine learning operation based on the scalar value [Kim, par. 31-34, DVFS management, Narayanaswamy, par. 52 ].
Claim 6. Kim teaches the storage device of claim 5, wherein the processing circuitry is configured to determine the scalar value according to an equation [ par. 39, equation].
Claim 7. Kim teaches the storage device of claim 1, wherein the machine learning operation is performed inside the storage device [par. 56, in a different embodiment, IC 10 may include a processor that generates the result of the gate level simulation and the result of the power analysis].
Claim 8. Kim teaches the storage device of claim 7, wherein the storage device includes processing circuitry configured to perform the machine learning operation in response to a request from a host device [Fig. 9, par 58-59, electronic device/IC 10 having processor executed the simulation of Fig. 9]
Claim 9. Kim teaches the storage device of claim 8, the rest of the claim recites the same limitations as in claim 5 and rejected accordingly.
Claim 10, Kim as combined teaches the storage device of claim 1, Kim further teaches wherein the at least one internal component includes a first core and a second core [ Fig. 2, 16, 10, core 1011-1014, CPU GPU clusters] and when the first core is active and the second core is inactive [Fig. 17, par. 43, core enable/disable, par. 84-86, 90, each core include respective DMP, control signal CTRL 1-4 for different state], and a clock value is provided to each of the core to control the operation of the core [Fig. 11 and 8, par. 63-64 87 and 90 each of the control information CTRL may include information indicating target frequency of the clock signal ICK].
The combination does not explicitly disclose controlling the first core is fixed while in active state and a clock value of the second core varies based on the power parameter. However, during active mode, the system is under load, and the frequency is set to meet performance, stability, and output requirements and in in inactive mode, the system can be set adjusted to low or idle due to no load demand. Therefore, it would have been obvious to one having ordinary skill in the art to implement such common policy in optimizing the performance of the system since doing so would reduce unnecessary power consumption, prevents unnecessary wear, and avoids instability during active operation, while still allowing efficiency gains when the system is idle.
Regarding claim 11, Kim teaches a method of operating a storage device [[Fig. 1-20, par. 95, data processing device]], the method comprising:
setting a power parameter using machine learning [Fig. 3-11 and associated description especially par. 57-58, 38-40, neural network/machine learning, i.e. power calculator 220 to analyze power monitored based on static and dynamic power monitor on performance]; and
adjusting a frequency of at least one active or inactive device based on the set power parameter , wherein the adjusting of the frequency includes at least one of dividing a clock corresponding to the frequency, gating the clock, or gearing the clock [, [par. 31-34, regulator 130 and management unit 140 may scale (or regulate) operating voltage and frequency based on the monitoring result, Fig. 17-18].
As for the limitation peak power and voltage based on a workload of the storage device, Narayanaswamy discloses such limitation as discussed in claim 1 and is modified for the same reason.
Claim 12. Kim as combined teaches the method of claim 11, wherein setting the power parameter includes deriving, in an external device, the power parameter using the machine learning. [par. 49, registers 222 may be updated to values transmitted from a user or an external device, par. 53-54 and 58 pre-processed result stored and update in advance]
Claim 13. Kim teaches the method of claim 12, the rest of the claim repeats the limitation of claim 5 and therefore rejected accordingly.
Claim 15. Kim teaches the method of claim 11, wherein setting the power parameter includes performing a machine learning operation in internal processing circuitry in response to a request from a host device [Fig. 9, par 58-59, electronic device/IC 10 having processor executed the simulation of Fig. 9].
Regarding claim 16. A method of operating a storage device, the method comprising:
receiving a machine learning execution request from a host device [[Fig. 9, par 58-59, electronic device/IC 10 having processor executed the simulation of Fig. 9]
performing a machine learning operation in response to the machine learning execution request [Fig. 9. steps 104-108] and
setting a parameter according to a result of execution of the machine learning operation [Fig. 1, step 110], wherein the parameter is a value derived considering performance, peak power, and average power [Fig. 3-11 and associated description especially par. 57-58, 38-40, neural network/machine learning, i.e. power calculator 220 to analyze power monitored based on static and dynamic power monitor on performance (i.e. peak, see Fig. 4, par. 69-70) and average (par. 60-61)] [Fig. 1-11, par. 31-34, 45-50, (DVFS) based on state values, power classification value from a minimum to a maximum power, average value]. As for the limitation peak power and voltage based on a workload of the storage device, Narayanaswamy discloses such limitation as discussed in claim 1 and is modified for the same reason.
Claim 17. The method of claim 16, wherein the parameter indicates a clock value for each of a plurality of internal components of the storage device par. 31-34, regulator 130 and management unit 140 may scale (or regulate) operating voltage and frequency based on the monitoring result, Fig. 17-18], and wherein setting the parameter includes adjusting the clock value using at least one of a clock division value, a clock gating value, or a clock gearing value. [par. 60, divider, par. 70 clock gating; par. 31-34, DVFS management].
Claim 18. Kim teaches the method of claim 16, wherein the parameter indicates quality parameters determining a service quality, and the quality parameters include at least two of a program operation parameter, a buffer size, a core clock, firmware policy, or performance margin [Fig. 2-4, 11; par. 3-4, 31-34, 39-40, thermal policy DFVS ].
Claim 19. Kim as combined teaches the method of claim 16, determining the power state of the first and second core [par. 85] ; the rest of the claim repeats the limitation of claim 10 and therefore rejected accordingly.
20. The method of claim 16, further comprising:
receiving the performance and the power consumption of the storage device [Fig. 9, S310-320, Fig. 10-11],
deriving a scalar value in which the performance and the power consumption for each workload are synthesized [par. 60, divider, par. 70 clock gating ];
and performing the machine learning operation using the derived scalar value. [par. 49, registers 222 may be updated to values transmitted from a user or an external device, par. 53-54 and 58 pre-processed result stored and update in advance].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim 20210116955 in view of Narayanaswamy and further in view of NPL titled “Bayesian Optimization”
Claim 14. Kim teaches the method of claim 13 but does not specify the machine learning is configured to use a Bayesian optimization. Applicant discloses the formula is based on the well-known Bayesian optimization which is a known formula. In addition, NPL teaches Bayesian optimization formula [see formulas in methodology and numerical example] uses a surrogate function to estimate the objective through sampling that represent as probability distributions which can be updated in light of new information to evaluate the probability of exploring a certain point. It would have been obvious to one having ordinary skill in the art to implement Bayesian optimization approach in order to take advantage of the powerful and efficient approach to optimizing complex functions, particularly when evaluations are expensive, noisy, or time-consuming [NPL, Introduction]
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM HUYNH whose telephone number is (571)272-4147. The examiner can normally be reached M-Th 6:00am-4:0pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAWEED ABBASZADEH can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIM HUYNH/ Primary Patent Examiner,
Art Unit 2176
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