DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/28/2024 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “high frequency” in claims 1, 7-8, 13, & 19-20 is a relative term which renders the claim indefinite. The term “high frequency” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purposes, the Examiner will consider the term “high frequency” as any frequency value.
The term “short duration pulses” in claim 1, 7, 13 & 19 is a relative term which renders the claim indefinite. The term “short duration pulses” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purposes, the Examiner will consider the term “short duration pulses” as any time duration pulses.
Claims 2, 8 and 20 recites the limitation "short duration" in pages 32, 34 and 38. There is insufficient antecedent basis for this limitation in the claim.
The term “desired output voltage” in claim 1, 7, 13, & 19 is a relative term which renders the claim indefinite. The term “desired output voltage” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purposes, the Examiner will consider the term “desired output voltage” as any output voltage.
Claims 3-6, 9-12 & 21-24 are rejected due to their dependency of independent claims 1, 7, 13 and 19.
Allowable Subject Matter
Claim 1-24 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding claim 1, Ichikawa (US Patent US-20180178710-A1 cited in the IDS) teaches a driver circuit (circuit in Fig. 3 ) for supplying pulses of electrical power to a load (Fig. 3 circuit 1 provides pulses as seen in Fig. 23 to a semiconductor laser 10, [0096] & [0098]) comprising:
a power control (Fig. 3 lighting circuit 20 ) receiving input power (Fig. 3 power 2) and converting that input power to an output voltage (Fig. 3 Vout);
a high frequency switch (Fig. 3 switch transistor M1, [0089]) configured to provide short duration pulses of the output voltage to a load causing a pulsed load current of like duration to flow (see [089], [0090] and Fig. 2 SCTN are the generated pulses) therethrough;
a current sensor (Fig. 3 detection current 34) through which the pulsed load current flows for generating a signal representative of the pulsed load current ([007], from the circuit in Fig. 3 detection current 34 is connecting directly from one of the nodes of laser 10 from which pulsed load current flow);
a sample and hold circuit (Fig. 3 voltage adjustment 42 comprises S/H 90 in Fig. 16) configured to sample the signal representative of the pulsed load current ([0139]); and
a controller (Fig. 3 controller 32) receiving the sampled signal value (Fig. 3 controller 32 comprises S/ H90 ; hence receives the hold sample signal) and responsive thereto and to a reference value ([100] “ reference value V.sub.REF”), and configured to apply control signals to the power control to produce the desired output voltage (average of the two voltages V.sub.H and V.sub.L see Fig. 7 & [0104] [0119), and to the high frequency switch and the sample and hold circuit to control Fig. 32 controller 32 controls switch 4 and voltage adjustment circuit 42 that comprises S/H 90) the pulsed load current to a predetermined value (Fig. 3 driving current I.sub.DRV, see [0097]).
Ichikawa fails to teach a sample and hold circuit configured to sample the signal representative of the pulsed load current in synchronism with the high frequency switch and to hold the sampled signal value.
Regarding claim 1, Takekawa (US Patent US-9167647-B1) teaches a driver circuit (Fig. 3 control circuit 100) for supplying pulses of electrical power (Fig. 5 shows the pulses generated by 100) to a load (Fig. 3 load 14) comprising:
a power control (Fig. 3 power supply 10) receiving input power and converting that input power to an output voltage (Fig. 3 10 generates output voltage Vo, column 3 lines 37-38);
a high frequency switch (Fig. 3 S2) configured to provide short duration pulses of the output voltage to a load causing a pulsed load current of like duration to flow therethrough (see column 3 lines 37-41 “based on the voltage of the DC power supply E1 by turning on/off the switch S1 and control the flow of a drive current Id to the load 14 by turning on/off the switch S2”);
a current sensor through which the pulsed load current flows (Fig. 3 controller 22 measures the drive current Id in the energizing period of the load 14, column 4 lines 26-30) for generating a signal representative of the pulsed load current (Fig. 3 controller 22 generates feedback signal Sf, see column 4 lines 33-34);
a sample and hold circuit (Fig. 3 sample-hold circuit 22) configured to sample a signal (Fig. 3 sample-hold circuit 22 samples control signal Sc, column 5 lines 47-48) in synchronism with the high frequency switch and to hold the sampled signal value (Fig. 5 Sc plot is synchronized in the period that the LED is on/off control by S2); and
a controller receiving the sampled signal value (Fig. 3 controller 24 receives feedback signal Sf, column 4 lines 33-34) and responsive thereto and to a reference value (target current, see column 4 lines 40-41), and configured to apply control signals to the power control (Fig. 3 controller 24 controls signals to DC-DC converter 12 that is part of power supply 10, column 4 lines 35-40) to produce the desired output voltage (voltage of Id current, column 4 lines 35-40 ), and to the high frequency switch and the sample and hold circuit to control the pulsed load current (Fig. 3 controller 24 controls signal Sc which turn on/off S2 & S3, see column 3 lines 57-58 & column 4, lines 42-43 & column 5 lines 47-48; S3 is part of sample-hold circuit 220 ) to a predetermined value (Fig. 5 values of signal Sc).
Takekawa fails to teach a sample and hold circuit configured to sample the signal representative of the pulsed load current.
Sanchez (US Patents US-20060098699-A1 & US-20090225803-A1 both cited in the IDS) and Tanaka (US Patent US-5504722-A) do not remedy the deficiencies of Ichikawa or Takekawa.
Claims 1-7 are dependent on claim 1.
Regarding claim 7, Ichikawa (US Patent US-20180178710-A1) teaches a method for supplying pulses of electrical power to a load (Fig. 3 circuit 1 provides pulses as seen in Fig. 23 to a semiconductor laser 10, [0096] & [0098]) comprising:
converting an input power (Fig. 3 power 2) to an output voltage (Fig. 3 Vout);
providing high frequency short duration pulses of the output voltage to a load causing a pulsed load current of like duration to flow (Fig. 3 switch transistor M1, [0089]and Fig. 2 SCTN are the generated pulses) therethrough;
sensing the pulsed load current flow for generating a signal representative of the pulsed load current (Fig. 3 detection current 34, see [007], ], from the circuit in Fig. 3 detection current 34 is connecting directly from one of the nodes of laser 10 from which pulsed load current flow);
sampling the signal representative of the pulsed load current (Fig. 3 controller 32 comprises S/ H90 ; hence receives the hold sample signal) and responsive thereto and to a reference value ([0097]); and
receiving the sampled signal value (Fig. 3 controller 32 comprises S/ H90 ; hence receives the hold sample signal) and a reference value ([100] “ reference value V.sub.REF”), and applying control signals responsive to the sampled signal value and to the reference value to produce a desired output voltage (average of the two voltages V.sub.H and V.sub.L see Fig. 7 & [0104] [0119) and to control the high frequency short duration pulses and the sampling and holding to control the pulses of electrical power (Fig. 32 controller 32 controls switch 4 and voltage adjustment circuit 42 that comprises S/H 90) to a predetermined value (Fig. 3 driving current I.sub.DRV, see [0097]).
Ichikawa fails to teach sampling the signal representative of the pulsed load current in synchronism with the high frequency short duration pulses and holding the sampled signal value.
Sanchez (US Patents US-20060098699-A1 & US-20090225803-A1), Tanaka (US Patent US-5504722-A), and Takekawa (US Patent US-9167647-B1) do not remedy the deficiencies of Ichikawa.
Claims 8-13 are dependent on claim 7.
Regarding claim 13, Ichikawa (US Patent US-20180178710-A1) teaches a driver circuit (circuit in Fig. 3 ) for supplying pulses of electrical power to a light producing semiconductor device (Fig. 3 circuit 1 provides pulses as seen in Fig. 23 to a semiconductor laser 10, [0096] & [0098]) comprising:
a power control (Fig. 3 lighting circuit 20 ) including a DC converter (Fig. 3 converter 30) receiving input power (Fig. 3 power 2) and converting that input power to an output voltage (Fig. 3 Vout);
a high frequency switch transistor (Fig. 3 switch transistor M1, [0089]) configured to provide short duration pulses of the output voltage to a light producing semiconductor device causing a pulsed light producing semiconductor device current of like duration to flow (see [089], [0090] and Fig. 2 SCTN are the generated pulses) therethrough;
a current sensing resistor (Fig. 3 detection current 34 comprises resistor Rcs) through which the pulsed light producing semiconductor device current flows for generating a signal representative of the pulsed light producing semiconductor device current (([007], from the circuit in Fig. 3 detection current 34 is connecting directly from one of the nodes of laser 10 from which pulsed load current flow);
a sample and hold circuit (Fig. 3 voltage adjustment 42 comprises S/H 90 in Fig. 16); and
a controller (Fig. 3 controller 32) receiving the sampled signal value and responsive thereto (Fig. 3 controller 32 comprises S/ H90 ; hence receives the hold sample signal) and to a reference value ([100] “ reference value V.sub.REF”), configured to apply a control signal to the power control to produce the desired output voltage (average of the two voltages V.sub.H and V.sub.L see Fig. 7 & [0104] [0119), and to the high frequency switch and the sample and hold circuit to control Fig. 32 controller 32 controls switch 4 and voltage adjustment circuit 42 that comprises S/H 90) the pulsed load current to a predetermined value (Fig. 3 driving current I.sub.DRV, see [0097]), and to apply a pulse width modulated drive signal to the high frequency switch transistor (Fig. 2 shows the pulse width modulated drive signal of M1 ) and to the sample and hold circuit switch transistor to control the pulsed light producing semiconductor device current to a predetermined value (Fig. 3 driving current I.sub.DRV, see [0097]).
Ichikawa fails to teach a switch transistor configured to sample the signal representative of the pulsed light producing semiconductor device current in synchronism with the high frequency switch transistor and to hold the sampled signal value.
Sanchez (US Patents US-20060098699-A1 & US-20090225803-A1) , Tanaka (US Patent US-5504722-A) and Takekawa (US Patent US-9167647-B1) do not remedy the deficiencies of Ichikawa.
Claims 14-18 are dependent on claim 13.
Regarding claim 19, Ichikawa (US Patent US-20180178710-A1) teaches a method for supplying pulses of electrical power to a laser diode (Fig. 3 circuit 1 provides pulses as seen in Fig. 23 to a semiconductor laser 10, [0096] & [0098]) comprising:
converting an input power (Fig. 3 power 2) to an output voltage (Fig. 3 Vout);
providing high frequency short duration pulses of the output voltage to a laser diode causing a pulsed laser diode current of like duration to flow (Fig. 3 switch transistor M1, [0089]and Fig. 2 SCTN are the generated pulses) therethrough;
sensing the pulsed laser diode current flow for generating a signal representative of the pulsed laser diode current Fig. 3 detection current 34, see [007], ], from the circuit in Fig. 3 detection current 34 is connecting directly from one of the nodes of laser 10 from which pulsed load current flow);
sampling the signal representative of the pulsed laser diode current (Fig. 3 controller 32 comprises S/ H90 ; hence receives the hold sample signal) and responsive thereto and to a reference value ([0097]); and
receiving the sampled signal value (Fig. 3 controller 32 comprises S/ H90 ; hence receives the hold sample signal) and a reference value ([100] “ reference value V.sub.REF”), and applying control signals responsive to the sampled signal value and to the reference value to produce a desired output voltage (average of the two voltages V.sub.H and V.sub.L see Fig. 7 & [0104] [0119) and to control the high frequency short duration pulses and the sampling and holding to control the pulses of electrical power (Fig. 32 controller 32 controls switch 4 and voltage adjustment circuit 42 that comprises S/H 90) to a predetermined value (Fig. 3 driving current I.sub.DRV, see [0097]).
Ichikawa fails to teach sampling the signal representative of the pulsed laser diode current and responsive thereto and to a reference value in synchronism with the high frequency short duration pulses and holding the sampled signal value.
Sanchez (US Patents US-20060098699-A1 & US-20090225803-A1), Tanaka (US Patent US-5504722-A), and Takekawa (US Patent US-9167647-B1) do not remedy the deficiencies of Ichikawa.
Claims 20-24 are dependent on claim 19.
Conclusion
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/FERNANDA ADRIANA CAMACHO ALANIS/Examiner, Art Unit 2828
/MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828
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