DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-9 and 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 1, the limitation “a selection circuit, configured to select whether supplying the first voltage to the internal power supply circuit or supplying the second voltage to the internal power supply circuit according to a comparison result between the first voltage and a reference voltage or the second voltage and the reference voltage” (emphasis added), on lines 5-8, is unclear. It seems to be duplicate of limitation “the selection circuit is configured to select whether supplying the first voltage to the internal power supply circuit or supplying the second voltage to the internal power supply circuit according to a comparison result between the first voltage and the reference voltage”, on lines 11-14. Therefore, the clam is indefinite. Correction and/or clarification is required.
Claims 2-4, 6-9 and 11-12 are rejected due to their dependencies on the base claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 8-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hausman et al. (hereinafter Hausman, US 2022/0109323 A1).
For claim 1, Hausman discloses a semiconductor integrated circuit device (Figs. 2 and 11 of Hausman discloses a semiconductor circuit device including an internal power supply circuit 216/216’; a selection circuit 214/214’ and first circuit 225/225’. It is noted that Hausman discloses the circuit except for a semiconductor integrated circuit. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a semiconductor integrated circuit, since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). The term “integral” is sufficiently broad to embrace constructions united by such means as fastening and welding. In re Hotte, 177 USPQ 326, 328 (CCPA 1973). Building semiconductor integrated circuit reduces device size and increases reliability due to fewer physical connection), comprising:
a first power supply terminal, configured to receive a first voltage (Figs. 2 and 11 of Hausman disclose a first power supply 220/220’ having first power supply terminal 224/224’, configured to receive a first voltage VSUPP – see Hausman, Figs. 2 and 11, paragraphs [0032]-[0033]);
a second power supply terminal, configured to receive a second voltage (Figs. 2 and 11 of Hausman disclose a second power supply terminal which is output of a second power supply 204/204’, configured to receive a second voltage VBATT – see Hausman, Figs. 2 and 11, paragraph [0028] and [0126]);
an internal power supply circuit (Figs. 2 and 11 of Hausman disclose an internal power supply circuit 216/216’); and
a selection circuit (Figs. 2 and 11 of Hausman disclose a selection circuit 214/214’), configured to select whether supplying the first voltage to the internal power supply circuit 216/216’ or supplying the second voltage VSUPP to the internal power supply circuit 216/216’ according to a comparison result between the second voltage VSUPP and the reference voltage (Figs. 2 and 11-12 of Hausman discloses the selection circuit 214 configured to select whether supplying the first voltage VSUPP to the internal power supply circuit 216/216’ or supplying the second voltage VBATT to the internal power supply circuit 216/216’ according to a comparison result between the first voltage VSUPP and the reference voltage “threshold” – see Hausman, Figs. 2 and 11-12, paragraphs [0041]-[0042] and [0126]-[0129]), wherein
the second voltage is a voltage lower than the first voltage and during a current flowing through the second power supply terminal (Figs. 2 and 11 of Hausman disclose the second voltage VBATT (3 volts) is a voltage lower than the first voltage VSUPP (5 volts) and during a current flowing through the second power supply terminal 224 – see Hausman, Figs. 2 and 11, paragraphs [0029], lines 9-19; [0035]-[0036]; [0044], and [0126]),
wherein the selection circuit (Figs. 2 and 11 of Hausman disclose a selection circuit 214/214’), configured to select whether supplying the first voltage to the internal power supply circuit or supplying the second voltage to the internal power supply circuit according to a comparison result between the first voltage VSUPP and the reference voltage (Figs. 2 and 11-12 of Hausman discloses the selection circuit 214 configured to select whether supplying the first voltage VSUPP to the internal power supply circuit 216/216’ or supplying the second voltage VBATT to the internal power supply circuit 216/216’ according to a comparison result between the first voltage VSUPP and the reference voltage “threshold” – see Hausman, Figs. 2 and 11-12, paragraphs [0041]-[0042] and [0126]-[0129]).
For claim 3, Hausman discloses the semiconductor integrated circuit device of claim 1, further comprising a first circuit (Figs. 2 and 11 of Hausman discloses the semiconductor integrated circuit device further comprising a first circuit 225/225’ -- see Hausman, Figs. 2 and 11, paragraphs [0023], lines 1-3 and [0126]), wherein the internal power supply circuit (Figs. 2 and 11, the internal power supply circuit 216/216’) is configured to
generate a third voltage based on a voltage supplied from the selection circuit (Figs. 2 and 11 of Hausman disclose the internal power supply circuit 216 which is configured to generate a third voltage Vcc based on a voltage VBATT//VSUPP supplied from the selection circuit 214 – see Hausman, Figs. 2 and 11; paragraphs [0042] and [0126]), and
supply the third voltage to the first circuit (Figs. 2 and 5 of Hausman disclose the internal power supply circuit 216/516A which supplies the third voltage Vcc to the first circuit 225/525 – see Hausman, Figs. 2 and 11, paragraph [0074]).
For claim 4, Hausman discloses the semiconductor integrated circuit device of claim 1, further comprising a second circuit, wherein the first voltage is supplied to the second circuit (Fig. 2 of Hausman discloses a second circuit 225, wherein the first voltage VSUPP is supplied to the second circuit 225 – see Hausman, Fig. 2, paragraphs [0032]-[0033]).
For claims 6, 8 and 9, Hausman discloses the semiconductor integrated circuit device of claims 1, 3, or 4 wherein the semiconductor integrated circuit device is configured as a motor driver for driving a motor (Fig. 2 of Hausman discloses the semiconductor integrated circuit device 214, 216, 225 which is configured as a motor driver for driving a motor 206 – see Hausman, paragraph [0023], lines 1-15).
For claim 11, Hausman discloses a motor system, comprising:
the semiconductor integrated circuit device of claim 6 (see explanation as in claim 6 above); and
the motor (Fig. 2 of Hausman discloses the motor 206 -- see Hausman, paragraph [0023], lines 1-15).
For claim 12, Hausman discloses the motor system of claim 11 (see explanation as in claim 11above). Hausman is silent for disclosing a vehicle. However, given that the reference shows the precise structure claimed by the present invention adds nothing to the claimed structure of the circuit, the phenomena, whether it is used in “a vehicle”. Is an intended use of the circuit and that does not carry patentable weight. Since the teaching of Hausman for controlling motor in motorized window which can be used for powering window of “a vehicle”. Therefore, it would have been obvious to one having skill in the art at the time of the invention was made to use Hausman’s motor control system which powers window of “a vehicle”.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hausman et al. (hereinafter Hausman, US 2022/0109323 A1) in view of Sakamoto (US 2022/0302731 A1).
For claim 2, Hausman discloses all limitations as applied in claim 1 above. Hausman discloses the first and second power supply terminals. Hausman is silent for disclosing
the first power supply terminal is configured to be connected to a first end of a resistor externally connected to the semiconductor integrated circuit device and applied with the first voltage, and
the second power supply terminal is configured to be connected to a second end of the resistor.
However, Sakamoto discloses the semiconductor integrated circuit 1 as shown in Fig. 1 of Sakamoto except batteries B1, B2, contactors 22p, 22n, 32p, 32n, wherein the semiconductor integrated circuit 1 comprises first and second power supply terminals (Fig. 2 of Sakamoto discloses first power supply terminal 57p,57n/21p,21n and second power supply terminal 56p,56n/31p,31n – see Sakamoto, Fig. 2, paragraph [0050), wherein
the first power supply terminal is configured to be connected to a first end of a resistor externally connected to the semiconductor integrated circuit device and applied with the first voltage (Figs. 1-2 of Sakamoto disclose the first power supply terminal 57p,57n/21p,21n which is configured to be connected to a first end of a resistor included in contactors 32p externally connected to the semiconductor integrated circuit device and applied with the first voltage – see Sakamoto, Figs. 1-2, paragraphs [0041]-[0043]) and [0050], lines 1-7), and
the second power supply terminal is configured to be connected to a second end of the resistor (Figs. 1-2 of Sakamoto disclose the second power supply terminal 56p,56n/31p,31n is configured to be connected to a second end of the resistor included in contactors 32p – see Sakamoto, Digs. 1-2, paragraph [0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify teaching of Hausman to incorporate teaching of Sakamoto for purpose of controlling motor control system efficiently.
For claim 7, Hausman in view of Sakamoto disclose the semiconductor integrated circuit device of claim 2, wherein the semiconductor integrated circuit device is configured as a motor driver for driving a motor (Fig. 2 of Hausman discloses the semiconductor integrated circuit device 214, 216, 225 which is configured as a motor driver for driving a motor 206 – see Hausman, paragraph [0023], lines 1-15).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI T DINH whose telephone number is (571)270-3852. The examiner can normally be reached (571)270-3852.
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/THAI T DINH/Primary Examiner, Art Unit 2837
Jun 8, 2026
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