Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 07/08/2026 has been acknowledged. No claims have been amended. Claim 20 is canceled. Claim 21 is new. No new matter has been added.
This office action considers claims 1-19 and 21 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 07/08/2026 with respect to the rejection of claims 1-19 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 2, 5-8, 12, 15, 18-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20210036106 A1 – hereinafter Shin) in view of More (US 20230299138 A1), Wei et al. (US 20220139911 A1 – hereinafter Wei), and Van Dal et al. (US 12563781 B2 – hereinafter Van Dal).
Regarding independent claim 1, Shin teaches:
(Original) A semiconductor device ([0009] – “FIG. 1 illustrates a
schematic top view of a semiconductor device”) comprising:
a substrate (100 – Fig. 2 – [0025] – “substrate 100”);
an active pattern (101 – Fig. 2 – [0030] – “The first lower pattern 101 and the
second lower pattern 102 may be respectively formed by etching a portion of the substrate 100, and may include an epitaxial layer grown from the substrate 100”) extending in a first horizontal direction (X – Fig. 2 – [0029] – “first direction X”) on the substrate (100);
a plurality of nanosheets (111, 112, 113 – fig. 2 – [0043] – “nanowires 111, 112, 113”) spaced apart from each other and stacked in a vertical direction
(Z – Fig. 2 – [0034] – “The third nanowire 113 may be disposed on the second nanowire 112 to be spaced apart therefrom in the third direction Z”) on the active pattern (101);
a gate electrode (121 – Fig. 2 – [0051] – “gate electrode 121”) extending in a second horizontal direction (Y – Fig. 2 – [0054] – “gate electrode 121 may extend in the second direction Y”) different from the first horizontal direction (X) on the active pattern (101), the gate electrode (121) surrounding the plurality of nanosheets (111, 112, 113 – Fig. 2 shows this);
a source/drain region (151 – Fig. 2 – [0025] – “source/drain region 151”) disposed on at least one side of the gate electrode (121) on the active pattern (101), the source/drain region comprising a first layer doped with a metal, and a second layer disposed on the first layer; and
an inner spacer disposed between the gate electrode and the first layer, between each of the plurality of nanosheets, the inner spacer in contact with the first layer, the inner spacer comprising a metal oxide formed by oxidizing a same material as the metal.
Shin does not expressly disclose the other limitations of claim 1.
However, in an analogous art, More teaches
the source/drain region (210 – Fig. 9B – [0153] – “the source/drain region 210 and the source/drain contact 902” – 902 is contained in the source/drain region 102) comprising a first layer (508a – Fig. 9B – [0155] – “source/drain region 210 includes the portion 508a (e.g., a second portion of the first epitaxial layer) over the inner spacers 404a”) doped with a metal and a second layer (514a – Fig. 9B – [0155] – “the portion 514a (e.g., a second portion of the second epitaxial layer) adjacent to the portion 508a”) disposed on the first layer (508a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source/drain region structure as taught by More into Shin.
An ordinary artisan would have been motivated to use the known technique of More in the manner set forth above to produce the predictable result of [0012] – “The sidewall layer and/or the dielectric region may further reduce, prevent, and/or block migration of the dopants from the source/drain region to the other areas of the device. As a result, a performance of the device may be increased by decreasing short channel effects (e.g., DIBL), decreasing an off-current of the device, and decreasing leakage within the device.”
Shin and More do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Wei teaches
doped with a metal (366 – Fig. 4E – {[0091] – “the S/D region 366”}, {[0089] – “the S/D material 366 may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy”}, {[0050] – “The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions”} – element 366 corresponds to element 114 a source/drain region).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate doping with a metal structure as taught by Wei into Shin and More.
An ordinary artisan would have been motivated to use the known technique of Wei in the manner set forth above to produce the predictable result [0002] – “to optimize the performance of each device and each interconnect becomes increasingly significant.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Shin, More, and Wei do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Van Dal teaches
an inner spacer (21 – Fig. 22A – [6:13] – “inner spacers 21”) disposed between the gate electrode (84 – Fig. 22A – [6:14] – “gate electrode layer 84”) and the first layer (74), between each of the plurality of nanosheets (25), the inner spacer (21) in contact with the first layer (74), the inner spacer (21) comprising a metal oxide formed by oxidizing (this is a product by process limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. In this case, formed by oxidizing does not result in a structural difference) a same material as the metal ({[6:15-16] – “inner spacers 21 are remaining portions of a sacrificial layer 20”}, {[7:55-58] – “sacrificial layer 25 are made of one or more layers of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide or any other suitable insulating material” – ‘sacrificial layer 25’ is a typo and should read ‘sacrificial layer 20’ as 25 is a semiconductor layer – [7:35-36] – “semiconductor layers 25 are made of oxide semiconductor materials”}).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer structure as taught by Van Dal into Shin, More, and Wei.
An ordinary artisan would have been motivated to use the known technique of Van Dal in the manner set forth above to produce the predictable result [3:31-34] – “Minimization of power consumption in a semiconductor device, such as an integrated circuit (IC), is a critical issue for semiconductor devices for high speed operations and/or semiconductor devices for mobile terminals.”
Regarding claim 2, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 2 depends. Shin, More, and Wei do not expressly disclose the limitations of claim 2.
However, in an analogous art, Van Dal teaches
(Original) The semiconductor device of claim 1, wherein the metal
comprises either aluminum (Al) or nickel (Ni) ([6:27-29] –
“body contact layer 74 is made of one or more of W, Cu, Ti, Ag, Al, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal structure as taught by Van Dal into Shin, More, and Wei
An ordinary artisan would have been motivated to use the known technique of Van Dal in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 5 depends. Shin further teaches
(Original) The semiconductor device of claim 1, further comprising: a
gate insulating layer (122 – Fig. 4 – [0051] – “gate insulating film 122”) disposed between the gate electrode (121) and the inner spacer (141), the gate insulating layer (122) contacting the inner spacer (141 – Fig. 4 shows this).
Regarding claim 6, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 6 depends. Shin further teaches
(Original) The semiconductor device of claim 1, wherein upper and
lower surfaces of the inner spacer (141) between each of the plurality of nanosheets (111, 112, 113) contact the plurality of nanosheets (111, 112, 113 – Fig. 2 – [0043] – “nanowires 111, 112, 113” – Fig. 4 shows this).
Regarding claim 7, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 7 depends. Shin further teaches
(Original) The semiconductor device of claim 1, wherein the first
layer (151 – fig. 4 – [0065] – “first source/drain region 151”) does not contact each of upper and lower surfaces of the plurality of nanosheets (111, 112, 113) between each of the plurality of nanosheets (111, 112, 113 – Fig. 4 shows this).
Regarding claim 8, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 8 depends. Shin further teaches
(Original) The semiconductor device of claim 1, wherein side walls of
the inner spacer (341 – Fig. 6 – [0094] – “inner spacer 341”) contacting the first layer (151 – Fig. 6) are formed concavely toward the gate electrode (131 – Fig. 6 – [0084] – “gate electrode 131”) beyond side walls of the plurality of nanosheets (111, 112, 113) in the first horizontal direction (X – Fig. 6 shows this).
Regarding independent claim 12, Shin teaches:
(Original) A semiconductor device ([0009] – “FIG. 1 illustrates a
schematic top view of a semiconductor device”) comprising:
a substrate (100 – Fig. 2 – [0025] – “substrate 100”);
an active pattern (101 – Fig. 2 – [0030] – “The first lower pattern 101 and the
second lower pattern 102 may be respectively formed by etching a portion of the substrate 100, and may include an epitaxial layer grown from the substrate 100”) extending in a first horizontal direction (X – Fig. 2 – [0029] – “first direction X”) on the substrate (100);
a plurality of nanosheets (111, 112, 113 – fig. 2 – [0043] – “nanowires 111,
112, 113”) spaced apart from each other and stacked in a vertical direction (Z – Fig. 2 – [0034] – “The third nanowire 113 may be disposed on the second nanowire 112 to be spaced apart therefrom in the third direction Z”) on the active pattern (101);
a gate electrode (121 – Fig. 2 – [0051] – “gate electrode 121”) extending in a second horizontal direction (Y – Fig. 2 – [0054] – “gate electrode 121 may extend in the second direction Y”) different from the first horizontal direction (X) on the active pattern (101), the gate electrode (121) surrounding the plurality of nanosheets (111, 112, 113 – Fig. 2 shows this);
a source/drain region (151 – Fig. 2 – [0025] – “source/drain region 151”) disposed on at least one side of the gate electrode (121) on the active pattern (101), the source/drain region comprising a first layer doped with either aluminum (Al) or nickel (Ni), and a second layer disposed on the first layer;
a gate insulating layer (122 – Fig. 4 – [0051] – “gate insulating film 122”) disposed between the gate electrode (121) and the first layer (151 – fig. 4 – [0065] – “first source/drain region 151”), wherein the gate insulating layer (122) is disposed between adjacent nanosheets (111, 112, 113 – Fig. 2 – [0043] – “nanowires 111, 112, 113”) of the plurality of nanosheets (111, 112, 113 – Fig. 4 shows this); and
an inner spacer (141 – Fig. 2 – [0051] – “inner spacer 141”) disposed between the gate electrode (121) and the first layer (151), wherein the inner spacer (141) is disposed between adjacent nanosheets (111, 112, 113) of the plurality of nanosheets (111, 112, 113 – Fig. 4 shows this), the inner spacer (141) contacts the first layer (151) and the gate insulating layer (122), and the inner spacer (21 – Fig. 22A – [6:13] – “inner spacers 21”) comprises aluminum oxide or nickel oxide ({[6:15-16] – “inner spacers 21 are remaining portions of a sacrificial layer 20”}, {[7:55-58] – “sacrificial layer 25 are made of one or more layers of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide or any other suitable insulating material” – ‘sacrificial layer 25’ is a typo and should read ‘sacrificial layer 20’ as 25 is a semiconductor layer – [7:35-36] – “semiconductor layers 25 are made of oxide semiconductor materials”}).
Shin does not expressly disclose the other limitations of claim 12.
However, in an analogous art, More teaches
the source/drain region (210 – Fig. 9B – [0153] – “the source/drain region 210 and the source/drain contact 902” – 902 is contained in the source/drain region 102) comprising a first layer (508a – Fig. 9B – [0155] – “source/drain region 210 includes the portion 508a (e.g., a second portion of the first epitaxial layer) over the inner spacers 404a”) doped with either aluminum (Al) or nickel (Ni), and a second layer (514a – Fig. 9B – [0155] – “the portion 514a (e.g., a second portion of the second epitaxial layer) adjacent to the portion 508a”) disposed on the first layer (508a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source/drain region structure as taught by More into Shin.
An ordinary artisan would have been motivated to use the known technique of More in the manner set forth above to produce the predictable result as stated above in claim 1.
Shin and More do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Wei teaches
doped with either aluminum (Al) or nickel (Ni) (366 – Fig. 4E – {[0091] – “the S/D region 366”}, {[0089] – “the S/D material 366 may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy”}, {[0050] – “The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions”} – element 366 corresponds to element 114 a source/drain region).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate doping with a metal structure as taught by Wei into Shin and More.
An ordinary artisan would have been motivated to use the known technique of Wei in the manner set forth above to produce the predictable result as stated above in claim 1.
Shin, More, and Wei do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Van Dal teaches
the inner spacer (21 – Fig. 22A – [6:13] – “inner spacers 21”) comprises aluminum oxide or nickel oxide ({[6:15-16] – “inner spacers 21 are remaining portions of a sacrificial layer 20”}, {[7:55-58] – “sacrificial layer 25 are made of one or more layers of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide or any other suitable insulating material” – ‘sacrificial layer 25’ is a typo and should read ‘sacrificial layer 20’ as 25 is a semiconductor layer – [7:35-36] – “semiconductor layers 25 are made of oxide semiconductor materials”}).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer structure as taught by Van Dal into Shin, More, and Wei.
An ordinary artisan would have been motivated to use the known technique of Van Dal in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 15, Shin as modified by More, Wei, and Van Dal, teaches claim 12 from which claim 15 depends. Shin further teaches
(Original) The semiconductor device of claim 12, wherein side walls
of the inner spacer (341 – Fig. 6 – [0094] – “inner spacer 341”) contacting the first layer (151 – Fig. 6) are formed concavely toward the gate electrode (131 – Fig. 6 – [0084] – “gate electrode 131”) beyond side walls of the plurality of nanosheets (111, 112, 113) in the first horizontal direction (X – Fig. 6 shows this).
Regarding independent claim 18, Shin teaches:
(Original) A semiconductor device ([0009] – “FIG. 1 illustrates a schematic top view of a semiconductor device”) comprising:
a substrate (100 – Fig. 2 – [0025] – “substrate 100”);
an active pattern (101 – Fig. 2 – [0030] – “The first lower pattern 101 and the
second lower pattern 102 may be respectively formed by etching a portion of the substrate 100, and may include an epitaxial layer grown from the substrate 100”) extending in a first horizontal direction (X – Fig. 2 – [0029] – “first direction X”) on the substrate (100);
a plurality of nanosheets (111, 112, 113 – fig. 2 – [0043] – “nanowires 111,
112, 113”) spaced apart from each other and stacked in a vertical direction (Z – Fig. 2 – [0034] – “The third nanowire 113 may be disposed on the second nanowire 112 to be spaced apart therefrom in the third direction Z”) on the active pattern (101);
a gate electrode (121 – Fig. 2 – [0051] – “gate electrode 121”) extending in a second horizontal direction (Y – Fig. 2 – [0054] – “gate electrode 121 may extend in the second direction Y”) different from the first horizontal direction (X) on the active pattern (101), the gate electrode (121) surrounding the plurality of nanosheets (111, 112, 113 – Fig. 2 shows this);
a source/drain region (151 – Fig. 2 – [0025] – “source/drain region 151”) disposed on at least one side of the gate electrode (121) on the active pattern (101), the source/drain region comprising a first layer doped with a metal, and a second layer disposed on the first layer; and
an inner spacer disposed between the gate electrode and the first layer, between each of the plurality of nanosheets, the inner spacer in contact with the first layer, the inner spacer comprising aluminum oxide,
wherein the first layer does not contact each of upper and lower surfaces of the plurality of nanosheets between each of the plurality of nanosheets.
Shin does not expressly disclose the other limitations of claim 18.
However, in an analogous art, More teaches
the source/drain region (210 – Fig. 9B – [0153] – “the source/drain region 210 and the source/drain contact 902” – 902 is contained in the source/drain region 102) comprising a first layer (508a – Fig. 9B – [0155] – “source/drain region 210 includes the portion 508a (e.g., a second portion of the first epitaxial layer) over the inner spacers 404a”) doped with a metal, and a second layer (514a – Fig. 9B – [0155] – “the portion 514a (e.g., a second portion of the second epitaxial layer) adjacent to the portion 508a”) disposed on the first layer (508a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source/drain region structure as taught by More into Shin.
An ordinary artisan would have been motivated to use the known technique of More in the manner set forth above to produce the predictable result as stated above in claim 1.
Shin and More do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Wei teaches
doped with a metal (366 – Fig. 4E – {[0091] – “the S/D region 366”}, {[0089] – “the S/D material 366 may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy”}, {[0050] – “The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions”} – element 366 corresponds to element 114 a source/drain region).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate doping with a metal structure as taught by Wei into Shin and More.
An ordinary artisan would have been motivated to use the known technique of Wei in the manner set forth above to produce the predictable result as stated above in claim 1.
Shin, More, and Wei do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Van Dal teaches
an inner spacer (21 – Fig. 22A – [6:13] – “inner spacers 21”) disposed between the gate electrode (84 – Fig. 22A – [6:14] – “gate electrode layer 84”) and the first layer (74), between each of the plurality of nanosheets (25), the inner spacer (21) in contact with the first layer (74), the inner spacer (21) comprising aluminum oxide ({[6:15-16] – “inner spacers 21 are remaining portions of a sacrificial layer 20”}, {[7:55-58] – “sacrificial layer 25 are made of one or more layers of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide or any other suitable insulating material” – ‘sacrificial layer 25’ is a typo and should read ‘sacrificial layer 20’ as 25 is a semiconductor layer – [7:35-36] – “semiconductor layers 25 are made of oxide semiconductor materials”}),
wherein the first layer (74) does not contact each of upper and lower surfaces of the plurality of nanosheets (25) between each of the plurality of nanosheets (25 – Fig. 22A shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer and first layer structure as taught by Van Dal into Shin, More, and Wei.
An ordinary artisan would have been motivated to use the known technique of Van Dal in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 19, Shin as modified by More, Wei, and Van Dal, teaches claim 18 from which claim 19 depends. Shin further teaches
(Original) The semiconductor device of claim 18, wherein side walls
of the inner spacer (341 – Fig. 6 – [0094] – “inner spacer 341”) contacting the first layer (151 – Fig. 6) are formed concavely toward the gate electrode (131 – Fig. 6 – [0084] – “gate electrode 131”) beyond side walls of the plurality of nanosheets (111, 112, 113) in the first horizontal direction (X – Fig. 6 shows this).
Regarding claim 21, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 21 depends. Shin does not expressly disclose the limitations of claim 21.
However, in an analogous art, More teaches
(New) The semiconductor device of claim 1, wherein the first layer (508a –
Fig. 9B – [0155] – “source/drain region 210 includes the portion 508a (e.g., a second portion of the first epitaxial layer) over the inner spacers 404a”) comprises a semiconductor material (514 – [0108] – “the epitaxial layer 514 may include a silicon germanium material doped with boron (SiGeB)” – element 514a is part of element 514)) doped with the metal, and wherein the inner spacer does not include the semiconductor material.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source/drain region structure as taught by More into Shin.
An ordinary artisan would have been motivated to use the known technique of More in the manner set forth above to produce the predictable result as stated above in claim 1.
Shin and More do not expressly disclose the other limitations of claim 21.
However, in an analogous art, Wei teaches
doped with the metal (366 – Fig. 4E – {[0091] – “the S/D region 366”}, {[0089] – “the S/D material 366 may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy”}, {[0050] – “The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions”} – element 366 corresponds to element 114 a source/drain region).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate doping with a metal structure as taught by Wei into Shin and More.
An ordinary artisan would have been motivated to use the known technique of Wei in the manner set forth above to produce the predictable result as stated above in claim 1.
Shin, More, and Wei do not expressly disclose the other limitations of claim 21.
However, in an analogous art, Van Dal teaches
and wherein the inner spacer (21) does not include the semiconductor material ([11:36-41] – “part of the sacrificial layers 20 remain as inner spacers 21. When the sacrificial layers 20 remain as the inner spacers 21, the sacrificial layers 20 are made of an insulating material in some embodiments” – insulating materials are not semiconductor materials).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer structure as taught by Van Dal into Shin, More, and Wei.
An ordinary artisan would have been motivated to use the known technique of Van Dal in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of More, Wei, Van Dal, and Sekine et al. (US 20090014809 A1 – hereinafter Sekine).
Regarding claim 3, Shin as modified by More, Wei, and Van Dal, teaches claim 2 from which claim 3 depends. Shin, More, Wei, and Van Dal do not expressly disclose the limitations of claim 3.
However, in an analogous art, Sekine teaches
(Original) The semiconductor device of claim 2, wherein the substrate (101
– Fig. 11 – [0064] – “101 denotes a silicon substrate”) is a p-channel metal-oxide-semiconductor (PMOS) region (104 – Fig. 12 – [0064] – “104 denotes a pMOS region”), the metal is aluminum (Al) (107 – Fig. 1 – [0064] – “107 denotes an aluminum film”), and the metal oxide is aluminum oxide (108 – Fig. 14 – [0064] – “AlO film 108”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the p-channel region structure as taught by Sekine into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Sekine in the manner set forth above to produce the predictable result of [0069] – “the work functions of the n-channel and p-channel MOS transistors are modulated by the aluminum film 107 including small amount of oxygen and the AlO film 108 existing between the HfSiON film 106 and the nickel silicide gate electrode 109, the work functions are controlled without changing the gate electrode materials.”
Regarding claim 13, Shin as modified by More, Wei, and Van Dal, teaches claim 12 from which claim 13 depends. Shin further teaches
the inner spacer (141).
Shin, More, Wei, and Van Dal do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Sekine teaches
(Original) The semiconductor device of claim 12, wherein the substrate (101
– Fig. 11 – [0064] – “101 denotes a silicon substrate”) is a p-channel metal-oxide-semiconductor (PMOS) region (104 – Fig. 12 – [0064] – “104 denotes a pMOS region”), the first layer comprises (107 – Fig. 1 – [0064] – “107 denotes an aluminum film”) doped aluminum (Al), and the inner spacer comprises aluminum oxide (108 – Fig. 14 – [0064] – “AlO film 108”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the p-channel region structure as taught by Sekine into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Sekine in the manner set forth above to produce the predictable result as stated above I claim 3.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Shin, More, Wei, Van Dal, and Takahashi et al. (US 20070138580 A1 – hereinafter Takahashi).
Regarding claim 4, Shin as modified by More, Wei, and Van Dal, teaches claim 2 from which claim 4 depends. Shin, More, Wei, and Van Dal do not expressly disclose the limitations of claim 4.
However, in an analogous art, Takahashi teaches
(Original) The semiconductor device of claim 2, wherein the substrate (1 –
Fig. 1 – [0011] – “substrate 1”) is an n-channel metal-oxide-semiconductor (NMOS) region ([0012] – “n-type and p-type MOSFETs”), the metal is nickel (Ni) ([0013] – “n-type MOSFET is composed of nickel silicide (NiSi) formed by turning poly-silicon completely into silicide with nickel (Ni)”), and the metal oxide is nickel oxide ([0034] – “the gate insulating film includes an electrically insulating film having a high dielectric constant and containing one of metal oxide … contains silicide of metal M as a primary constituent … The metal M is selected from nickel (Ni)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the n-channel region structure as taught by Takahashi into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable result [0014] – “to modulate a work function of a gate electrode by 0.5 eV at greatest.”
Regarding claim 14, Shin as modified by More, Wei, and Van Dal, teaches claim 12 from which claim 14 depends. Shin further teaches
the inner spacer (141).
Shin, More, Wei, and Van Dal do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Takahashi teaches
(Original) The semiconductor device of claim 12, wherein the substrate (1 –
Fig. 1 – [0011] – “substrate 1”) is an n-channel metal-oxide-semiconductor (NMOS) region ([0012] – “n-type and p-type MOSFETs”), the first layer ([0013] – “n-type MOSFET is composed of nickel silicide (NiSi) formed by turning poly-silicon completely into silicide with nickel (Ni)”) comprises doped nickel (Ni), and the inner spacer comprises nickel oxide ([0034] – “the gate insulating film includes an electrically insulating film having a high dielectric constant and containing one of metal oxide … contains silicide of metal M as a primary constituent … The metal M is selected from nickel (Ni)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the n-channel region structure as taught by Takahashi into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable result as stated above in claim 4.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of More, Wei, Van Dal and Yu et al. (US 20210408247 A1 – hereinafter Yu).
Regarding claim 9, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 9 depends. Shin further teaches
the first horizontal direction (X).
Shin, More, Wei, and Van Dal do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Yu teaches
(Original) The semiconductor device of claim 1, wherein side walls ([0045] –
“the outer sidewalls of the first inner spacers 89 are illustrated as being straight in FIG. 11C, the outer sidewalls of the first inner spacers 89 may be concave or convex” – hereinafter ‘SW’) of the inner spacer (89 – Fig. 11C – [0045] – “inner spacers 89” – Fig. 11C displays the element as ‘90’ vice ‘89’ as specified, although 90 is an inner spacer - [0048] – “the inner spacers 90”) contacting the first layer (92A – Fig. 12C – [0053] – “epitaxial source/drain regions 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C”) are formed convexly ([0045] – “the outer sidewalls of the first inner spacers 89 are illustrated as being straight in FIG. 11C, the outer sidewalls of the first inner spacers 89 may be concave or convex”) toward the first layer (92A) beyond side walls (SW) of the plurality of nanosheets (54 – Fig. 11D – [0045] – “FIG. 11D illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 89 are concave, and the first inner spacers 89 are recessed from sidewalls of the second nanostructures 54”) in the first horizontal direction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer structure as taught by Yu into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of [0043] – “The first inner spacers 89 act as isolation features between subsequently formed source/drain regions and a gate structure.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 16, Shin as modified by More, Wei, and Van Dal, teaches claim 12 from which claim 16 depends. Shin further teaches
the first horizontal direction (X).
Shin, More, Wei, and Van Dal do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Yu teaches
(Original) The semiconductor device of claim 12, wherein side walls ([0045]
– “the outer sidewalls of the first inner spacers 89 are illustrated as being straight in FIG. 11C, the outer sidewalls of the first inner spacers 89 may be concave or convex” – hereinafter ‘SW’) of the inner spacer (89 – Fig. 11C – [0045] – “inner spacers 89” – Fig. 11C displays the element as ‘90’ vice ‘89’ as specified, although 90 is an inner spacer - [0048] – “the inner spacers 90”) contacting the first layer (92A – Fig. 12C – [0053] – “epitaxial source/drain regions 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C”) are formed convexly ([0045] – “the outer sidewalls of the first inner spacers 89 are illustrated as being straight in FIG. 11C, the outer sidewalls of the first inner spacers 89 may be concave or convex”) toward the first layer (92A) beyond side walls (SW) of the plurality of nanosheets (54 – Fig. 11D – [0045] – “FIG. 11D illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 89 are concave, and the first inner spacers 89 are recessed from sidewalls of the second nanostructures 54”) in the first horizontal direction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer structure as taught by Yu into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result as stated above in claim 9.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Shin, More, Wei, Van Dal and Chen et al. (US 20220320309 A1 – hereinafter Chen).
Regarding claim 10, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 10 depends. Shin, More, Wei, and Van Dal do not expressly disclose the limitations of claim 10.
However, in an analogous art, Chen teaches
(Original) The semiconductor device of claim 1, wherein at least a part of
the first layer (130A – Fig. 11 – [0045] – “source/drain layers 130A”) between each of the plurality of nanosheets (110 – Fig. 7C – [0045] – “semiconductor layers 110”) contacts lower surfaces of each of the plurality of nanosheets (Fig. 7C shows that the lower surface of the nanosheet 110 is unconstrained to be in contact with the first layer 130A that is shown in Fig. 11).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first layer and nanosheet structure as taught by Chen into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result [0002] – “to improve gate control by increasing gate-channel coupling, reducing OFF-state current, and reducing short-channel effects (SCEs). Nano-sheet-based devices include a stack of suspended channel layers at least partially surrounded by a gate structure. The nano-sheet-based devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, allowing them to be aggressively scaled down while maintaining gate control and mitigating SCEs.”
Claims 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of More, Wei, Van Dal, and Lin et al. (US 12268023 B2 – hereinafter Lin).
Regarding claim 11, Shin as modified by More, Wei, and Van Dal, teaches claim 1 from which claim 11 depends. Shin, More, Wei, and Van Dal do not expressly disclose the limitations of claim 11.
However, in an analogous art, Lin teaches
(Original) The semiconductor device of claim 1, wherein at least a part of
the inner spacer (206 – Fig. 9 – [9:33] – “inner spacers 206”) contacts side walls (430 – Fig. 9 – [9:66-67] – “sidewall surfaces 430 for the semiconductor layers 120”) of the plurality of nanosheets (120 – Fig. 9 – [9:66-67] – “semiconductor layers 120”) in the first horizontal direction (X – Fig. 9 – [9:21] – “X-direction” – Fig. 9 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer and nanosheet structure as taught by Lin into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result [1:22-31] – “multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device is nano-sheet-based transistor, whose gate structure extends around its channel region providing access to the channel region on all sides. The nano-sheet-based transistors are compatible with conventional metal-oxide-semiconductor (MOS) processes, allowing them to be aggressively scaled down while maintaining gate control and mitigating SCEs.”
Regarding claim 17, Shin as modified by More, Wei, and Van Dal, teaches claim 12 from which claim 17 depends. Shin, More, Wei, and Van Dal do not expressly disclose the limitations of claim 17.
However, in an analogous art, Lin teaches
(Original) The semiconductor device of claim 12, wherein at least a part of
the inner spacer (206 – Fig. 9 – [9:33] – “inner spacers 206”) contacts side walls (430 – Fig. 9 – [9:66-67] – “sidewall surfaces 430 for the semiconductor layers 120”) of the plurality of nanosheets (120 – Fig. 9 – [9:66-67] – “semiconductor layers 120”) in the first horizontal direction (X – Fig. 9 – [9:21] – “X-direction” – Fig. 9 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inner spacer and nanosheet structure as taught by Lin into Shin, More, Wei, and Van Dal.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result as stated above in claim 11.
Pertinent Art
For the benefits of the Applicant, US 20250359165 A1 and US 20230132749 A1
are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the specific orientations of the inner spacer sidewalls.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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