Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
See the Terminal disclaimer Approved on 9/4/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13-24, 37-39 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
In remarks filed 7/20/2026 page 5 the Applicant states that the amendments to claim 13 clarify the 112 issue “These claimed features distinguish the buffer material from any of the device layers, including the n-type material comprising GaAs”, however they do not, see below the Applicant either does not know the answer or has not disclosed it. See paragraph 0039-0043 of the PG-PUB “the CS material can include InP, InGaAs, gallium arsenide (GaAs), gallium phosphide (GaP), indium gallium arsenide phosphide (InGaAsP), indium aluminum gallium arsenide (InAlGaAs), indium arsenide (InAs), indium gallium phosphide (InGaP), or a combination thereof” however this is not in the claim language and also the Examiner notes that from paragraph 0039-0043 it is clear that the Applicant does not know which buffer is used for “the n-type material can include an InP material” and which buffer is used for “the n-type material includes a GaAs material” and the Examiner notes that the materials cited InP, GaAs, InAs have different lattice constants, thus a person of ordinary skill in the art trying to make and use the invention would be unable to do so, thus the question of enablement is raised and so the 112 is now changed to 112 enablement.
The Examiner notes that the Applicant added the limitations “the Si substrate having a first bandgap characteristic, a first thermal characteristic, a first polarity, and a first crystalline characteristic” and “configured to have a second bandgap characteristic, a second thermal characteristic, a second polarity, and a second crystalline characteristic” however these limitations are not compared to each other in the claim and they are not used anywhere else in the claims and this is true even in the specification and the specification does not explain by giving any examples of these characteristics , and there is no example or best mode showing what these characteristics are, thus there is no enablement for the characteristics, because how can they be claimed, if the Applicant does not know what they are.
Claim 13 recites “a buffer material overlying the Si substrate, the buffer material comprising a compound semiconductor (CS) material” and “an array of photodetectors formed overlying the buffer material, and each of the photodetectors comprising: an n-type material comprising a GaAs material”, however the claim does not state that the buffer material is NOT “an n-type material comprising a GaAs material” which also satisfies the limitation of “the buffer material comprising a compound semiconductor (CS) material” , see also dependent claim 18 which states that the buffer can be GaAs, yet the Applicant argues , see Remarks filed “However, the bottom layer of this GaAs photodetector, shown in Figure 6A of Li, is an n-type GaAs layer. In fact, none of the layers of the photodetector 50 are described as a buffer layer. Thus, Li does not teach or disclose the claimed CS buffer material and claim 13 is not anticipated by Li” “For clarification, claim 13 is amended to recites "a buffer material overlying the Si substrate..." and "an array of photodetectors formed overlying the buffer material...". These amendments clarify the claimed device structure as having the photodetector materials spatially configured overlying the CS buffer material, which is spatially configured overlying the silicon substrate” and the Examiner asks the question: for the purpose of determining infringement, how is it possible to distinguish the buffer from the n-type GaAs material, is the claim saying that the buffer is NOT “an n-type material comprising a GaAs material” ? or is the claim saying the buffer can be “an n-type material comprising a GaAs material” but is just called by a different name ? or is the Applicant stating that a “buffer” layer must be undoped in order to buffer against defects formed due to mismatch with an underlying substrate, i.e. is the Applicant saying that it is not only the lattice constant but also the doping that defines a buffer layer ? For the purpose of examination, it is assumed that the buffer can be the same as or different than the n-type GaAs material.
Claim 13 amendment recites “the Si substrate having a first bandgap characteristic, a first thermal characteristic, a first polarity, and a first crystalline characteristic” “the buffer material comprising a compound semiconductor (CS) material configured to have a second bandgap characteristic, a second thermal characteristic, a second polarity, and a second crystalline characteristic” however the term polarity is not defined in the specification and the actual polarity is not in the claims and the specification does not given even one example of polarities for the substrate and the buffer so the Applicant either does not know the polarities or has not disclosed them, thus the invention is not enabled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
[ The Examiner notes that claim amendments including polarity required the change in the rejection below]
Claim(s) 13-15, 18, 20-22, 37, 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20160372502 A1) hereafter referred to as Li . Cheng (US 20130048061 A1) is provided as evidence.
In regard to claim 13 [see 112 rejection above, for this reason the rejection is 103, however the Examiner explains how the prior art appears to anticipate the claim limitations] Li teaches a circuit for a photodetector [see Fig. 6E, Fig. 9, see paragraph 0012 “FIGS. 6A, 6B, 6C, 6D, 6E and 6F, collectively referred to as FIG. 6, each show an enlarged, non-limiting embodiment of a photodetector used in the front-side illuminated FPA embodiment of FIGS. 7-10” “FIG. 6E shows a non-limiting example of a quantum dot IR photodetector structure”, see Figs. 7-10, see paragraph 0046, 0056 “vertically stacked and lateral radiation detecting structures shown in FIGS. 4, 5, 9 and 10 each function as a single pixel in a multi-pixel radiation detector. In practice some thousands or millions of the stacked or lateral Ge P-I-N visible wavelength photodetectors and the stacked or lateral InGaAs P-I-N IR wavelength photodetectors (pixel structures) are fabricated on the common Si substrate 10 to form a FPA circuit”] comprising:
a first terminal [see Fig. 10, Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”];
a second terminal [see Fig. 10, Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”];
a silicon (Si) substrate [see Si substrate 10 see the detector region on the left] comprising a surface region , [see 112 rejection above, these characteristics are not used or compared anywhere else in the claims, and the characteristics are not defined in the specification, thus they are not enabled] the Si substrate having a first bandgap [i.e inherent Si bandgap] characteristic, a first thermal [i.e. inherent thermal behavior of Si] characteristic, a first polarity [i.e. see Fig. 10, Fig. 9 see polarities, the Si substrate is a CMOS substrate], and a first crystalline [i.e. inherently that of the Si substrate] characteristic;
an array of photodetectors formed overlying the substrate [see paragraph 0056 “The vertically stacked and lateral radiation detecting structures shown in FIGS. 4, 5, 9 and 10 each function as a single pixel in a multi-pixel radiation detector. In practice some thousands or millions of the stacked or lateral Ge P-I-N visible wavelength photodetectors and the stacked or lateral InGaAs P-I-N IR wavelength photodetectors (pixel structures) are fabricated on the common Si substrate 10 to form a FPA circuit” see that implicitly pixel is array, see “focal plane arrays (FPAs)”, “In embodiments of this invention there can be two, three, four or more discrete photodetectors provided per pixel, where each photodetector is responsive to a different range of EM radiation wavelengths (possibly overlapping a wavelength range or ranges of one or more other photodetectors within the pixel)”, see that in Fig. 9 the Fig. 6E is GaAs detector with quantum dots i.e. it is 50 in Fig. 9]
each of the photodetectors comprising:
an n-type material [see Fig. 6E n-type GaAs Si doped, showing concentration “FIG. 6E shows an example of a quantum dot IR photodetector structure wherein a region containing InAs quantum dots is interposed between an N-type GaAs layer and a P-type GaAs layer” ] comprising a GaAs material having an silicon impurity with a concentration ranging from 3E17 cm-3 to 5E18 cm-3;
an absorption material overlying the n-type material, the absorption material being primarily free [see paragraph 0051 “FIG. 6E shows an example of a quantum dot IR photodetector structure wherein a region containing InAs quantum dots is interposed between an N-type GaAs layer and a P-type GaAs layer, each having a thickness of, for example, about 200 nm”, see no doping is disclosed, Li is not doping the absorption region] from any impurity, and the absorption material comprising InAs quantum dot material or a quantum dash containing material;
a p-type material [see Fig. 6E see p-type GaAs Zn doped, showing concentration] overlying the absorption material, the p-type material comprising a zinc impurity or a beryllium impurity or a carbon impurity having a concentration ranging from 3E17 cm-3 to 1E20 cm-3;
a first electrode [see Fig. 10, Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”] coupled to the n-type material and coupled to the first terminal;
a second electrode [see Fig. 10, Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”] coupled to the p-type material and coupled to the second terminal to define [i.e. a photodetector] a two terminal device;
an illumination region [see Figs. 7-10 see paragraph 0052 “In this front-side illuminated embodiment the top surface acts as a receiving surface for incident EM radiation”] characterized by an aperture region,
but does not state a buffer material overlying the Si substrate, the buffer material comprising a compound semiconductor (CS) material configured to have a second bandgap characteristic, a second thermal characteristic, a second polarity, and a second crystalline characteristic; and that the array of photodetectors is formed overlying the buffer material.
However see 112 rejection above, in remarks filed 7/20/2026 page 5 the Applicant states that the amendments to claim 13 clarify the 112 issue “These claimed features distinguish the buffer material from any of the device layers, including the n-type material comprising GaAs”, however they do not, and also these characteristics are not used or compared anywhere else in the claims.
See Cheng paragraph 0019 “Conventional structures that employ Germanium (Ge) often start with a Ge parent substrate that is expensive to fabricate. A III-V material may be formed on the Ge parent substrate (usually GaAs). The Ge substrate will be processed to form an n+-layer and a p+-layer. Forming an n+ Ge layer is difficult to achieve. In addition, epitaxially growing a lattice-matched layer on Ge is difficult. The epitaxial interface between Ge and, say, GaAs is prone to anti-phase defects, and atoms interact at the boundary forming undesirable interfacial compounds. Further, Ge diffuses into a GaAs …”.
Thus in Li the interface part i.e the lowermost portion of n-type GaAs in Fig. 6E is prone to defects and in any case can be called as “buffer” under broadest reasonable interpretation.
For this reason Li appears to anticipate the claim limitations, see Li teaches a buffer material [see Fig. 10, Fig. 9 see photodetector 50 is made by “An aperture 18A is then opened in the oxide layer 18 above the SOI layer where a first visible photodetector is desired, followed by the epitaxial growth of a GaAs photodetector 50 within the aperture 18A. The aperture 18A extends to the surface of the Ge layer 14”, see 112 rejection, see dependent claim 18 the “buffer” can be GaAs, thus a lowermost portion of n-type GaAs in Fig. 6E can be called as “buffer” under broadest reasonable interpretation] overlying the Si substrate, the buffer material comprising [see it is GaAs] a compound semiconductor (CS) material configured to have a second bandgap characteristic [i.e. that of GaAs], a second thermal [i.e. that of GaAs] characteristic, a second polarity [see above n-type GaAs], and a second crystalline [i.e. that of GaAs] characteristic;
that the array of photodetectors is formed overlying the buffer material [the Examiner notes that the claim does not state that the buffer material is a single contiguous layer across all the pixels, see in Fig. 9 the Fig. 6E GaAs photodetector 50 is formed within the aperture 18A in every single pixel, see paragraph 0056 “The vertically stacked and lateral radiation detecting structures shown in FIGS. 4, 5, 9 and 10 each function as a single pixel in a multi-pixel radiation detector. In practice some thousands or millions of the stacked or lateral Ge P-I-N visible wavelength photodetectors and the stacked or lateral InGaAs P-I-N IR wavelength photodetectors (pixel structures) are fabricated on the common Si substrate 10 to form a FPA circuit” see that implicitly pixel is array, see “focal plane arrays (FPAs)”, “In embodiments of this invention there can be two, three, four or more discrete photodetectors provided per pixel, where each photodetector is responsive to a different range of EM radiation wavelengths (possibly overlapping a wavelength range or ranges of one or more other photodetectors within the pixel)”, thus the array of Fig. 6E photodetectors are formed overlying the buffer material, thus under broadest reasonable interpretation, the claim limitation is satisfied.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include a buffer material overlying the Si substrate, the buffer material comprising a compound semiconductor (CS) material configured to have a second bandgap characteristic, a second thermal characteristic, a second polarity, and a second crystalline characteristic; and that the array of photodetectors is formed overlying the buffer material.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the lowermost portion of n-type GaAs in Fig. 6E can be called as “buffer” under broadest reasonable interpretation.
In regard to claim 14 Li does not teach wherein the Si substrate is configured to allow the plurality of photons to traverse there through.
However see Li teaches both front side and back side illumination, see Fig. 4 see thinned Si substrate through which light passes.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include wherein the Si substrate is configured to allow the plurality of photons to traverse there through.
The motivation is to be able to detect light from either top or bottom as desired.
In regard to claim 20 Li as combined in claim 14 teaches [see Fig. 4 see thinned Si substrate through which light passes] is characterized as a back side illuminated (BSI) device.
In regard to claim 15 Li teaches wherein the illumination region is free [see Li Figs. 7-10, see illumination from top] from any portion of the Si substrate.
In regard to claim 18 Li teaches wherein the CS material comprises [see claim 13 it is GaAs] InP, InGaAs, GaAs, GaP, InGaAsP, InAs, InAlGaAs, InGaP, or a combination thereof.
In regard to claim 21 Li teaches [see Li Figs. 7-10, see illumination from top] is characterized as a front side illuminated (FSI) device.
In regard to claim 22 Li teaches further comprising: a readout integrated circuit [see Fig. 10, Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”] comprising: a first input terminal [see Fig. 10, Fig. 9 see above] coupled to the first terminal; a second input terminal [see Fig. 10, Fig. 9 see above] coupled to the second terminal; and a pixel output [see readout is for each pixel “generated photocarriers are transported to the CMOS readout circuitry 16 via the metal interconnect layer 36 and the vertical interconnects 34” “Additional circuitry, in addition to the CMOS readout circuitry 16, can also be provided such as conventional pixel row and column multiplexers, etc”].
In regard to claim 37 Li teaches wherein each photodetector in the array of photodetectors is separated from each other photodetector by one or more isolation [see Fig. 10, Fig. 9 “FIG. 7 also shows the structure after the layer of protective oxide 18 (e.g., SiO.sub.2) is grown so as to cover the CMOS circuitry 16. An aperture 18A is then opened in the oxide layer 18 above the SOI layer where a first visible photodetector is desired” “Two additional apertures 18A are then opened in sequence (or simultaneously) to expose the top surface of the Ge layer 14. Into each aperture is deposited the InP/GaAs buffer layer 26 followed by the deposition of a first InGaAs photodetector 54 (shown in FIG. 6C) and a second InGaAs photodetector 56 (shown in FIG. 6D)”] structures, and wherein each isolation structure is configured between at least the p-type materials, the absorption materials, and the n-type materials of the photodetectors.
In regard to claim 38 Li teaches wherein the CS material of the buffer material is configured using direct [see Fig. 10, Fig. 9 see photodetector 50 is made by “An aperture 18A is then opened in the oxide layer 18 above the SOI layer where a first visible photodetector is desired, followed by the epitaxial growth of a GaAs photodetector 50 within the aperture 18A. The aperture 18A extends to the surface of the Ge layer 14” i.e. the GaAs is grown directly on the Ge] heteroepitaxy such that the CS material has [see parent claim 13] the first bandgap characteristic, the first thermal characteristic, the first polarity, and the first crystalline characteristic.
Claim(s) 16, 17, 23, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Chen et al. (US 20190348460 A1) hereafter referred to as Chen
In regard to claim 16 Li does not teach further comprising a color filter overlying the illumination region.
However this common in the art, see Chen paragraph 0107, 0147 “Each of pixel cells 800 also includes optical components to control the properties of first light component 822 and second light component 824 of light 820. For example, each of pixel cells 800 includes a microlens 832 to focus light 820, as well as an optical filter 834 to select, for example, the wavelength range of second light component 824 (e.g., one of red, green, or blue colors) to be absorbed/measured by second photodiode 810”
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include further comprising a color filter overlying the illumination region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to better control what light is input to the detector to have more control of detection spectrum, and microlens helps absorb more light.
In regard to claim 17 Li and Chen as combined teaches [see combination claim 16] further comprising a lens overlying the color filter.
In regard to claim 23 Li does not teach further comprising an analog front end circuit coupled to the first input terminal and the second input terminal.
However this common in the art, see Chen paragraph 0107, 0147 “As shown in FIG. 19, pixel cell 800 includes a set of switches M0, M1, M2, first photodiode 808, second photodiode 810, charge storage device 616, a voltage buffer 1902, an analog-to-digital converter (ADC) 1904, and a controller 1906”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include an analog front end circuit coupled to the first input terminal and the second input terminal.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to process the signal detected to obtain maximum information.
In regard to claim 24 Li and Chen as combined teaches [see combination claim 23] further comprising analog to digital conversion.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Haralson et al. (US 6359322 B1) hereafter referred to as Haralson
In regard to claim 19 Li teaches wherein the each photodetector is configured with a separate absorption material [see Li Fig. 9 see plurality of detectors of different type, see InGaAs detectors on the right] comprising InGaAs or InGaAsP, but does not teach and a multiplication material comprising InP whereby the multiplication material generates additional charge carriers by avalanche gain.
See Haralson column 4 line 65 “In a preferred arrangement, the avalanche photodiode 10 is formed as an InGaAs-InP photodiode. In this case, each of the primary well 22, separator layer 24, decoupler layer 26, multiplication layer 28, charge sheet 30, graded layer 32, buffer layer 36, and substrate 38 comprise indium phosphide (InP), while the absorption layer 34 comprises indium gallium arsenide (InGaAs)”.
Thus it would be obvious to modify Li to include and a multiplication material comprising InP whereby the multiplication material generates additional charge carriers by avalanche gain.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to increase sensitivity to incoming light.
Claim(s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Dasgupta et al. (KR 20160063316 A) hereafter referred to as Dasgupta
In regard to claim 39 Li does not state wherein the CS material of the buffer material is configured by an initial nucleation growth on the surface region of the Si substrate to trap, annihilate, or filter defects near an interface region between the CS material and the surface region of the Si substrate.
See Li Fig. 10 see Ge 14A is on Si substrate 10 “FIG. 10 shows a bulk Si substrate embodiment that forms, by etching, a recess 10B in the Si substrate 10 wherein the photodetectors 50-56 are fabricated”.
See Cheng (cited in parent claim 13) paragraph 0019 “Conventional structures that employ Germanium (Ge) often start with a Ge parent substrate that is expensive to fabricate. A III-V material may be formed on the Ge parent substrate (usually GaAs). The Ge substrate will be processed to form an n+-layer and a p+-layer. Forming an n+ Ge layer is difficult to achieve. In addition, epitaxially growing a lattice-matched layer on Ge is difficult. The epitaxial interface between Ge and, say, GaAs is prone to anti-phase defects, and atoms interact at the boundary forming undesirable interfacial compounds. Further, Ge diffuses into a GaAs …”.
See Dasgupta Fig. 9 teaches III-V growth in a trench, see “the substrate 101 is a silicon substrate” “In an embodiment, there are several silicon mesa structures in the trenches on the silicon substrate” “In an embodiment, the nucleation layer 115 is used to trap interfacial defects formed due to lattice mismatch between the III-V material and silicon” “Methods and apparatus for manufacturing an electronic device are described herein. The insulating layer is conformally deposited on the plurality of mesa structures in the trenches on the substrate. The insulating layer fills the space outside the mesa structures. A nucleation layer is deposited on the mesa structures. The III-V material layer is deposited on the nucleation layer. The III-V material layer grows laterally on the insulating layer. In general, the III-V material is at least one of group III elements of the periodic table, such as aluminum ("Al"), gallium ("Ga"), indium ("In" Refers to a compound semiconductor material that includes at least one of nitrogen ("N"), phosphorus ("P"), arsenic ("As"), and antimony ("Sb", for example). In at least some embodiments, the substrate comprises silicon” “In an embodiment, the nucleation layer 115 is deposited using a MOCVD technique at temperatures greater than < RTI ID = 0.0 > 1000 C. < / RTI > In an embodiment, nucleation layer 115 is deposited using MBE technology at a temperature of about 750 ° C to about 800 ° C. In an embodiment, the nucleation layer of aluminum nitride ("AlN") is deposited on top surfaces of the mesa structures at a thickness of about 5 nm to about 200 nm. In an embodiment, the nucleation layer 115 of AlN is used to prevent the formation of silicon (e.g., GaSi) composites with Group III elements that may be formed when the III-V material layer is deposited directly on the silicon Is used. In an embodiment, the nucleation layer 115 is used to provide a seeded hexagonal crystal structure in a layer of III-V material formed later on the nucleation layer in the process. In an embodiment, the nucleation layer 115 is used to trap interfacial defects formed due to lattice mismatch between the III-V material and silicon” “In an embodiment, the III-V material layer 116 grows locally on the nucleation layer 115 using selective region epitaxy. The III-V material layer 116 may be formed using one of the epitaxial techniques known to those of ordinary skill in the art of electronic device fabrication, such as chemical vapor deposition (CVD), metalorganic chemical vapor deposition ("MOCVD & Layer deposition ("ALD"), or other epitaxial growth techniques known to those of ordinary skill in the art of electronic device fabrication. In an embodiment, the III-V material layer 116 grows vertically on the nucleation layer 115 using a MOCVD technique at a temperature in the approximate range of 1000 ° C to 1100 ° C. In an embodiment, the III-V material layer grown on the nucleation layer 115 extends laterally over the insulation layer 111 by modifying at least one of the epitaxial growth parameters such as temperature, pressure, and the like” see that epitaxial techniques known to those of ordinary skill in the art of electronic device fabrication includes doping.
Thus using the technique of Dasgupta on Fig. 10 of Li means that a plurality of III-V materials can be used to form photodetectors using a III-V nucleation layer in a trench in the Si substrate and for these devices the Ge 14, 14A is not needed.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include wherein the CS material of the buffer material is configured by an initial nucleation growth on the surface region of the Si substrate to trap, annihilate, or filter defects near an interface region between the CS material and the surface region of the Si substrate.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is grow III-V directly on Si and obtain a wide variety of III-V materials for photodetectors to choose from and also to avoid issues such as Ge diffusion.
Response to Arguments
Applicant's arguments filed 7/20/2026 have been fully considered but they are not persuasive.
On page 5 the Applicant argues that the amendments to claim 13 clarify the 112 issue “These claimed features distinguish the buffer material from any of the device layers, including the n-type material comprising GaAs”, however they do not, see the 112 rejection above and also these characteristics are not used or compared anywhere else in the claims.
On page 6-8 the Applicant argues that the amendments to claim 13 does not show the new limitations.
The Examiner responds that see rejection above, the new limitations are shown obvious in the amended rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
