Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
See the Terminal disclaimer Approved on 9/4/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites “a buffer material overlying the Si substrate, the buffer material comprising a compound semiconductor (CS) material” and “an array of photodetectors formed overlying the buffer material, and each of the photodetectors comprising: an n-type material comprising a GaAs material”, however the claim does not state that the buffer material is NOT “an n-type material comprising a GaAs material” which also satisfies the limitation of “the buffer material comprising a compound semiconductor (CS) material” , see also dependent claim 18 which states that the buffer can be GaAs, yet the Applicant argues , see Remarks filed “However, the bottom layer of this GaAs photodetector, shown in Figure 6A of Li, is an n-type GaAs layer. In fact, none of the layers of the photodetector 50 are described as a buffer layer. Thus, Li does not teach or disclose the claimed CS buffer material and claim 13 is not anticipated by Li” “For clarification, claim 13 is amended to recites "a buffer material overlying the Si substrate..." and "an array of photodetectors formed overlying the buffer material...". These amendments clarify the claimed device structure as having the photodetector materials spatially configured overlying the CS buffer material, which is spatially configured overlying the silicon substrate” and the Examiner asks the question: for the purpose of determining infringement, how is it possible to distinguish the buffer from the n-type GaAs material, is the claim saying that the buffer is NOT “an n-type material comprising a GaAs material” ? or is the claim saying the buffer can be “an n-type material comprising a GaAs material” but is just called by a different name ? or is the Applicant stating that a “buffer” layer must be undoped in order to buffer against defects formed due to mismatch with an underlying substrate, i.e. is the Applicant saying that it is not only the lattice constant but also the doping that defines a buffer layer ? For the purpose of examination, it is assumed that the buffer can be the same as or different than the n-type GaAs material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13, 15, 18, 21, 22, 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20160372502 A1) hereafter referred to as Li in view of Matsukura (US 20100289061 A1)
In regard to claim 13 [see 112 rejection above, for this reason the rejection is 103, however the Examiner explains how the prior art appears to anticipate the claim limitations] Li teaches a circuit for a photodetector [see Fig. 6E, Fig. 9, see paragraph 0012 “FIGS. 6A, 6B, 6C, 6D, 6E and 6F, collectively referred to as FIG. 6, each show an enlarged, non-limiting embodiment of a photodetector used in the front-side illuminated FPA embodiment of FIGS. 7-10” “FIG. 6E shows a non-limiting example of a quantum dot IR photodetector structure”, see Figs. 7-10, see paragraph 0046, 0056 “vertically stacked and lateral radiation detecting structures shown in FIGS. 4, 5, 9 and 10 each function as a single pixel in a multi-pixel radiation detector. In practice some thousands or millions of the stacked or lateral Ge P-I-N visible wavelength photodetectors and the stacked or lateral InGaAs P-I-N IR wavelength photodetectors (pixel structures) are fabricated on the common Si substrate 10 to form a FPA circuit”] comprising:
a first terminal [see Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”];
a second terminal [see Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”];
a silicon (Si) substrate [see Si substrate 10 see the detector region on the left] comprising a surface region;
an array of photodetectors formed overlying the substrate [see paragraph 0056 “The vertically stacked and lateral radiation detecting structures shown in FIGS. 4, 5, 9 and 10 each function as a single pixel in a multi-pixel radiation detector. In practice some thousands or millions of the stacked or lateral Ge P-I-N visible wavelength photodetectors and the stacked or lateral InGaAs P-I-N IR wavelength photodetectors (pixel structures) are fabricated on the common Si substrate 10 to form a FPA circuit” see that implicitly pixel is array, see “focal plane arrays (FPAs)”, “In embodiments of this invention there can be two, three, four or more discrete photodetectors provided per pixel, where each photodetector is responsive to a different range of EM radiation wavelengths (possibly overlapping a wavelength range or ranges of one or more other photodetectors within the pixel)”, see that in Fig. 9 the Fig. 6E is GaAs detector with quantum dots i.e. it is 50 in Fig. 9]
each of the photodetectors comprising:
an n-type material [see Fig. 6E n-type GaAs Si doped, showing concentration “FIG. 6E shows an example of a quantum dot IR photodetector structure wherein a region containing InAs quantum dots is interposed between an N-type GaAs layer and a P-type GaAs layer” ] comprising a GaAs material having an silicon impurity with a concentration ranging from 3E17 cm-3 to 5E18 cm-3;
an absorption material overlying the n-type material, the absorption material being primarily free [see paragraph 0051 “FIG. 6E shows an example of a quantum dot IR photodetector structure wherein a region containing InAs quantum dots is interposed between an N-type GaAs layer and a P-type GaAs layer, each having a thickness of, for example, about 200 nm”, see no doping is disclosed, Li is not doping the absorption region] from any impurity, and the absorption material comprising InAs quantum dot material or a quantum dash containing material;
a p-type material [see Fig. 6E see p-type GaAs Zn doped, showing concentration] overlying the absorption material, the p-type material comprising a zinc impurity or a beryllium impurity or a carbon impurity having a concentration ranging from 3E17 cm-3 to 1E20 cm-3;
a first electrode [see Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”] coupled to the n-type material and coupled to the first terminal;
a second electrode [see Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”] coupled to the p-type material and coupled to the second terminal to define [i.e. a photodetector] a two terminal device;
an illumination region [see Figs. 7-10 see paragraph 0052 “In this front-side illuminated embodiment the top surface acts as a receiving surface for incident EM radiation”] characterized by an aperture region,
but does not state a buffer material overlying the Si substrate, the buffer material comprising a compound semiconductor (CS) material; and that the array of photodetectors is formed overlying the buffer material.
However see 112 rejection above, for this reason the rejection is 103, however the Examiner explains how the prior art appears to anticipate the claim limitations,
see Li teaches a buffer material [see Fig. 9 see photodetector 50 is made by “An aperture 18A is then opened in the oxide layer 18 above the SOI layer where a first visible photodetector is desired, followed by the epitaxial growth of a GaAs photodetector 50 within the aperture 18A. The aperture 18A extends to the surface of the Ge layer 14”, see 112 rejection, see dependent claim 18 the “buffer” can be GaAs, thus a lowermost portion of n-type GaAs in Fig. 6E can be called as “buffer” under broadest reasonable interpretation] overlying the Si substrate, the buffer material comprising [see it is GaAs] a compound semiconductor (CS) material;
that the array of photodetectors is formed overlying the buffer material [the Examiner notes that the claim does not state that the buffer material is a single contiguous layer across all the pixels, see in Fig. 9 the Fig. 6E GaAs photodetector 50 is formed within the aperture 18A in every single pixel, see paragraph 0056 “The vertically stacked and lateral radiation detecting structures shown in FIGS. 4, 5, 9 and 10 each function as a single pixel in a multi-pixel radiation detector. In practice some thousands or millions of the stacked or lateral Ge P-I-N visible wavelength photodetectors and the stacked or lateral InGaAs P-I-N IR wavelength photodetectors (pixel structures) are fabricated on the common Si substrate 10 to form a FPA circuit” see that implicitly pixel is array, see “focal plane arrays (FPAs)”, “In embodiments of this invention there can be two, three, four or more discrete photodetectors provided per pixel, where each photodetector is responsive to a different range of EM radiation wavelengths (possibly overlapping a wavelength range or ranges of one or more other photodetectors within the pixel)”, thus the array of Fig. 6E photodetectors are formed overlying the buffer material, thus under broadest reasonable interpretation, the claim limitation is satisfied.
See this is common in the art, see Matsukura paragraph 0059 “First, on the substrate 10, such as GaAs, the buffer layer 12, such as GaAs, is grown by a known crystal growth technique, e.g., molecular beam epitaxy. The film thickness of the GaAs buffer layer 12 varies depending on the device structure design but may be, e.g., 100 nm” “Then, on the buffer layer 12, the lower contact layer 14, e.g. GaAs, is grown by a known crystal growth technique, e.g., molecular beam epitaxy (FIG. 8A). The film thickness of the lower contact layer 14 varies depending on the device structure design but may be, e.g., 500 nm. For doping the lower contact layer 14, Si, for example, is used as an impurity, and the concentration is, e.g., 1.times.10.sup.18 cm.sup.-3”, see that the GaAs buffer layer 12 is not doped, however the lower contact layer 14 is doped.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include a buffer material overlying the Si substrate, the buffer material comprising a compound semiconductor (CS) material; and that the array of photodetectors is formed overlying the buffer material.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a buffer layer similar to the device layer, which can be undoped, is a simple, easy way to isolate the device from the substrate so that the device layers are as good a quality as desired i.e. by growing a GaAs device layer on a similar layer such as another GaAs “buffer” layer.
In regard to claim 15 Li teaches wherein the illumination region is free [see Li Figs. 7-10, see illumination from top] from any portion of the Si substrate.
In regard to claim 18 Li teaches wherein the CS material comprises [see claim 13 it is GaAs] InP, InGaAs, GaAs, GaP, InGaAsP, InAs, InAlGaAs, InGaP, or a combination thereof.
In regard to claim 21 Li teaches [see Li Figs. 7-10, see illumination from top] is characterized as a front side illuminated (FSI) device.
In regard to claim 22 Li teaches further comprising: a readout integrated circuit [see Fig. 9 see paragraph 0050 “After forming the photodetectors 50-56 a mesa etch process is performed to expose edge surfaces (as in FIG. 4) and contacts are formed on the exposed edge surfaces. In this embodiment each photodetector 50-56 includes two edge contacts, one on the N-type material and one on the P-type material. Apertures are then opened, the CMOS readout circuit transistors have the contact silicide 16A formed (at a temperature of about 400° C.), followed by the formation of vertical conductive interconnects 34 (e.g., Cu, Al, Au, etc.) to the silicided contacts 16A and to the contacts formed on the edge portions of the photodetectors 50, 52, 54 and 56. Top-side horizontal metal traces are then added to connect the vertical conductive interconnects 34 of the photodetectors 50-54 to the vertical conductive interconnects 34 connected to the CMOS readout circuitry 16”] comprising: a first input terminal [see Fig. 9 see above] coupled to the first terminal; a second input terminal [see Fig. 9 see above] coupled to the second terminal; and a pixel output [see readout is for each pixel “generated photocarriers are transported to the CMOS readout circuitry 16 via the metal interconnect layer 36 and the vertical interconnects 34” “Additional circuitry, in addition to the CMOS readout circuitry 16, can also be provided such as conventional pixel row and column multiplexers, etc”].
In regard to claim 37 Li teaches wherein each photodetector in the array of photodetectors is separated from each other photodetector by one or more isolation [see Fig. 9 “FIG. 7 also shows the structure after the layer of protective oxide 18 (e.g., SiO.sub.2) is grown so as to cover the CMOS circuitry 16. An aperture 18A is then opened in the oxide layer 18 above the SOI layer where a first visible photodetector is desired” “Two additional apertures 18A are then opened in sequence (or simultaneously) to expose the top surface of the Ge layer 14. Into each aperture is deposited the InP/GaAs buffer layer 26 followed by the deposition of a first InGaAs photodetector 54 (shown in FIG. 6C) and a second InGaAs photodetector 56 (shown in FIG. 6D)”] structures, and wherein each isolation structure is configured between at least the p-type materials, the absorption materials, and the n-type materials of the photodetectors.
Claim(s) 14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li
In regard to claim 14 Li does not teach wherein the Si substrate is configured to allow the plurality of photons to traverse there through.
However see Li teaches both front side and back side illumination, see Fig. 4 see thinned Si substrate through which light passes.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include wherein the Si substrate is configured to allow the plurality of photons to traverse there through.
The motivation is to be able to detect light from either top or bottom as desired.
In regard to claim 20 Li as combined teaches [see Fig. 4 see thinned Si substrate through which light passes] is characterized as a back side illuminated (BSI) device.
Claim(s) 16, 17, 23, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Chen et al. (US 20190348460 A1) hereafter referred to as Chen
In regard to claim 16 Li does not teach further comprising a color filter overlying the illumination region.
However this common in the art, see Chen paragraph 0107, 0147 “Each of pixel cells 800 also includes optical components to control the properties of first light component 822 and second light component 824 of light 820. For example, each of pixel cells 800 includes a microlens 832 to focus light 820, as well as an optical filter 834 to select, for example, the wavelength range of second light component 824 (e.g., one of red, green, or blue colors) to be absorbed/measured by second photodiode 810”
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include further comprising a color filter overlying the illumination region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to better control what light is input to the detector to have more control of detection spectrum, and microlens helps absorb more light.
In regard to claim 17 Li and Chen as combined teaches [see combination claim 16] further comprising a lens overlying the color filter.
In regard to claim 23 Li does not teach further comprising an analog front end circuit coupled to the first input terminal and the second input terminal.
However this common in the art, see Chen paragraph 0107, 0147 “As shown in FIG. 19, pixel cell 800 includes a set of switches M0, M1, M2, first photodiode 808, second photodiode 810, charge storage device 616, a voltage buffer 1902, an analog-to-digital converter (ADC) 1904, and a controller 1906”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include an analog front end circuit coupled to the first input terminal and the second input terminal.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to process the signal detected to obtain maximum information.
In regard to claim 24 Li and Chen as combined teaches [see combination claim 23] further comprising analog to digital conversion.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Haralson et al. (US 6359322 B1) hereafter referred to as Haralson
In regard to claim 19 Li teaches wherein the each photodetector is configured with a separate absorption material [see Li Fig. 9 see plurality of detectors of different type, see InGaAs detectors on the right] comprising InGaAs or InGaAsP, but does not teach and a multiplication material comprising InP whereby the multiplication material generates additional charge carriers by avalanche gain.
See Haralson column 4 line 65 “In a preferred arrangement, the avalanche photodiode 10 is formed as an InGaAs-InP photodiode. In this case, each of the primary well 22, separator layer 24, decoupler layer 26, multiplication layer 28, charge sheet 30, graded layer 32, buffer layer 36, and substrate 38 comprise indium phosphide (InP), while the absorption layer 34 comprises indium gallium arsenide (InGaAs)”.
Thus it would be obvious to modify Li to include and a multiplication material comprising InP whereby the multiplication material generates additional charge carriers by avalanche gain.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to increase sensitivity to incoming light.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
On pages 1-2 the Applicant argues “On page 3, paragraph [0042] of Li is cited as disclosing the claimed buffer material comprising a compound semiconductor (CS) material with the cited buffer material being the bottom layer of "the epitaxial growth of a GaAs photodetector 50 within the aperture 1 8A" shown in Figure 7 of Li. As further justification, it was also stated that "the claim (13) does not state that the photodetector is not part of the buffer". However, the bottom layer of this GaAs photodetector, shown in Figure 6A of Li, is an n-type GaAs layer. In fact, none of the layers of the photodetector 50 are described as a buffer layer. Thus, Li does not teach or disclose the claimed CS buffer material and claim 13 is not anticipated by Li. For clarification, claim 13 is amended to recites "a buffer material overlying the Si substrate..." and "an array of photodetectors formed overlying the buffer material...". These amendments clarify the claimed device structure as having the photodetector materials spatially configured overlying the CS buffer material, which is spatially configured overlying the silicon substrate. Additionally, claim 13 is amended to remove the limitation relating to selective area heteroepitaxy for simplification, and claim 19 is amended to correct a typo of the missing term "with" in the phrase "configuredwith a multiplication material..."”
The Examiner responds that see the 112 rejection, the claims do not show a material difference between the buffer (see dependent claim 18, the buffer can be GaAs) and the n-type GaAs material above it. The Examiner responds that calling a layer a “buffer” layer is not novel and there needs to be a material difference so that any infringement of the claim language can be determined. The Examiner responds that see the amended rejection, use of a buffer is common in the art and thus the rejection shows that the use of a buffer layer is obvious to a person of ordinary skill in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
Prosecution Insights