Prosecution Insights
Last updated: April 19, 2026
Application No. 18/409,730

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jan 10, 2024
Examiner
TAVLYKAEV, ROBERT FUATOVICH
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
2y 4m
To Grant
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
529 granted / 875 resolved
-7.5% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
34 currently pending
Career history
909
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
70.2%
+30.2% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 875 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 – 4, 7 – 15, and 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al (US 2022/0365297 A1) in view of Polomoff et al (US 2023/0130467 A1). Regarding claim 1, Weng discloses (Figs. 13 – 22 and 28; para. 0032, 0033, 0060 – 0070 and 0076) a semiconductor device (comprising silicon; para. 0024 and 0033), comprising (with reference to Fig. 28): a substrate structure (comprises layers 121I, 121II and layers sandwiched therebetween) comprising a coupling member (121I and the layers between 121I and 121II); a photonic unit 50B (para. 0032 and 033) disposed in a first (lower) recess of the coupling member (as seen in Fig. 28); an optical fiber 168 (para. 0060) disposed in a second (upper) recess of the coupling member and optically coupled (via 154 and 70) to the photonic unit 50B (as shown in Figs. 21 and 22; para. 0033, 0045, 0065, 0069 and 0070); and a chip unit 50A (which corresponds to 162 in Fig. 13 and can be an amplifier; para. 0057) disposed on the substrate structure and electrically connected to the photonic unit 50B through the coupling member (via vertical vias and metallization pattern 126 that penetrate the coupling member; para. 0049). Weng illustrates (Figs. 13, 15A, and 28), by way of example but not limitation, that a wider (cladding) portion of the optical fiber 168 is disposed outside the second (upper) recess of the coupling member. However, Polomoff discloses (Figs. 1 – 6 and 10; para. 0030 – 0039 and 0043) a semiconductor device 100 (para. 0032), comprising: a substrate structure 110,170 comprising a coupling member 110; a photonic unit 112 (para. 0030) disposed in a first recess of the coupling member 110 (as seen in Fig. 1); an optical fiber 116 (para. 0030) disposed in a second (V-shaped) recess 150 and optically coupled to the photonic unit 112 (via a coupler 118; para. 0030); wherein a depth of the second recess 150 is greater than or equal to half a diameter of the optical fiber 116 (as seen in Figs. 2 – 5, 7, 8, 10, and 11). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the depth of the second recess in Weng can be selected to be greater than or equal to half a diameter of the optical fiber, as a suitable/workable design choice that is explicitly illustrated by Polomoff and improves the strength of mechanical (adhesive) connection between the optical fiber and the substrate structure due to a larger surface covered by adhesive material (166 in Weng (para. 0060); 160 in Polomoff (para. 0036)) that covers the widest part of the cladding of the optical fiber. In light of the foregoing analysis, the Weng – Polomoff combination teaches expressly or renders obvious all of the recited limitations. Regarding claim 11, the teachings of Weng and Polomoff combine (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited step limitations of a corresponding method of manufacturing the contemplated semiconductor device, as detailed above for claim 1. Regarding claims 2 and 20, the Weng – Polomoff combination considers that the optical fiber 168 (in Weng) comprises a core portion 168A and a cladding portion 168B, and the cladding portion 168B surrounds the core portion 168A (as shown in Fig. 15A). Polomoff provides the same details (para. 0036). Regarding claims 3, 12, and 15, the Weng – Polomoff combination considers that forming the substrate structure (comprises layers 121I, 121II and the layers sandwiched therebetween, as identified in Fig. 28 of Weng) comprises providing a substrate 121II and forming the coupling member on an upper surface of the substrate 121II. There are insulation layers (comprising 120,124, 128, 132, and 136, as detailed in Fig. 13 of Weng) comprised in the coupling member which thereby comprises a first insulating layer and a second insulating layer, wherein the first (bottom most) insulating layer is disposed on the substrate, the second (upper) insulating layer is disposed on the first insulating layer. A proper selection of thicknesses of the first and second insulating layers would be well within ordinary skill in the art. One of the thicknesses can be smaller or greater than the other or they can be equal, as a matter of suitable/workable design choices and depending on a particular application. Regarding claims 4 and 18, the Weng – Polomoff combination considers that the substrate structure further comprises: a though hole (for under-bump metallization 138; para. 0055) penetrating through the substrate 121II (as identified in Fig. 28 of Weng); and a conductive element 138 disposed in the though hole (Fig. 28; para. 0055). Weng teaches (para. 0056 and 0057) that the conductive bumps 150 are used for flip chip mounting of the semiconductor device to another device (another coupling member) and, hence, renders obvious that such combined device comprises another coupling member disposed on a lower surface of the substrate away from the upper surface, wherein the conductive element 138 is electrically connected (via the conductive bumps 150) to the coupling member and the another coupling member. Regarding claim 7, the Weng – Polomoff combination considers that the another coupling member comprises a bonding pad (in full analogy to the bonding pads 138 in Fig. 28 of Weng), and the bonding pad has a recessed surface (as seen in Fig. 28). Regarding claims 8 and 14, the Weng – Polomoff combination considers that the substrate comprise glass in full analogy with at least some dielectric layers (para. 0025). It is also noted that it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. See In re Leshin, 125 USPQ 416. Regarding claims 9 and 19, the Weng – Polomoff combination considers (e.g., Figs. 16, 17, and 20A of Weng; Fig. 1 of Polomoff) that in a cross-sectional view of the semiconductor device, a number of contact points of the optical fiber with the substrate structure is greater than three. Regarding claims 10 and 13, the Weng – Polomoff combination considers the photonic unit (112,118 in Fig. 1 of Polomoff) can comprise a photoelectric element (detector) and a waveguide element, and the optical fiber is optically coupled to the waveguide element (para. 0030 of Polomoff). Furthermore, Weng teaches that light output by the fiber 168 is guided via waveguides 154 (para. 0043) to the photonic unit 50B which is electrical connected to the chip unit 162/50A and that the latter can comprise a transimpedance amplifier (para. 0057), while such electronic device is commonly used to amplify the output of a photodetector. Regarding claim 17, the Weng – Polomoff combination renders obvious that a pair of dielectric layers within coupling member can have an interface/boundary within he second recess for the optical fibers (similarly to Figs. 2 – 4 and 6 of Polomoff). In this case, the first insulating layer comprises a first opening, the second insulating layer comprises a second opening, and the first opening and the second opening form the second recess. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Weng in view of Polomoff, and further in view of Kodama et al (US 2008/0317402 A1). Regarding claim 5, Weng teaches though holes (as seen in Figs. 13 and 28), but does not expressly teach that their inner surfaces can be roughened. However, Kodama discloses (Fig. 1) a device (an optoelectronic board which is the same device type as that in Weng) that comprises a coupling member formed by a plurality of layers 32,34, wherein the coupling member has though holes 32c (para. 0040). Kodama expressly teaches (para. 0048) that the inner surfaces of the though holes 32c can be roughened (as shown in the rightmost inset in Fig. 1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the inner surfaces of the though holes in the device of Weng can be roughened, in accordance with the teachings of Kodama, in order to improve/increase the adhesion of a metal material within the though holes and thereby avoid peeling and cracking (para. 0048 of Kodama). The Weng – Polomoff – Kodama combination considers that a roughness of a (roughened) sidewall of the though hole differs from (is greater than) a roughness of the (unroughened) upper surface of the substrate. Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Weng in view of Polomoff, and further in view of Colgan et al (US 2008/0282742 A1). Regarding claims 6 and 16, the Weng – Polomoff combination illustrates only embodiments wherein the sidewalls of the second recess for the optical fiber has a constant angle across multiple insulating layers (Figs. 2 – 6 and 11 of Polomoff). However, Colgan discloses an optical fiber disposed in a recess, illustrates a prior art design (Fig. 3) similar to that in Weng and Polomoff, and teaches an improved design (Figs. 4 and 5; para. 0052 – 0059) wherein the sidewalls 32,33 of a recess 31 for an optical fiber 22 has two portions 32,33 with different angles of inclination. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the sidewalls of the second recess for the optical fiber of the Weng – Polomoff combination can be shaped to have two portions with different angles of inclination, as a suitable/workable shape that is explicitly illustrated by Colgan and improves alignment of the optical fiber in the second recess due to the presence of the (vertical) portion 32 which provides more accurate lateral/horizontal alignment of the fiber (“The shape of the recessed v-groove channel 42 serves to precisely locate the optical fiber 22” at para. 0059 of Colgan). As an aside, it is also noted that the second recess 31/42 for the optical fiber in Figs. 4 and 5 of Cogan has about the same shape as that in Fig. 3 of the instant application. Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 2020/0006304 A1) in view of England et al (US 10,224,286 B1). Regarding claims 1 and 11, Chang discloses (Fig. 2A; para. 0017 – 0024) a semiconductor device (comprising silicon; para. 0018), comprising: a substrate structure comprising a coupling member (above the two bottommost layers/substrate with bumps 332; para. 0018); a photonic unit 102 (para. 0017) disposed in a first (lower) recess of the coupling member (as seen in Fig. 2A); an optical fiber 124 (para. 0019) disposed in a second recess 126 (V-groove; para. 0032) of the coupling member and optically coupled (via coupler/converter 121 and waveguides 120; para. 0019) to the photonic unit 102; and a chip unit 110/114 (which can be an] transimpedance amplifier; para. 0024) disposed on the substrate structure and electrically connected to the photonic unit 102 through the coupling member (via vertical vias and metallization pattern that penetrate the coupling member; “The EIC die 114 may communicate with photonic devices of the IPS 102 using electrical signals” at para. 0024). Fig. 2A appears to show that a depth of the second recess 126 (V-groove) is greater than or equal to half a diameter of the optical fiber 124, but Chang does not expressly state so. However, England discloses (Fig. 10) a device 300 comprising: a substrate structure 100,200 comprising a coupling member; and an optical fiber 310 disposed in a second (V-shaped) recess 110; wherein a depth of the second recess 110 (e.g., 75 mm) is greater than or equal to half a diameter of the optical fiber 116 (120 mm; 5:20 – 47). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the depth of the second recess in Chang can be selected to be greater than or equal to half a diameter of the optical fiber, as a suitable/workable design choice that is explicitly illustrated by England and improves the strength of mechanical (adhesive; 10:52 – 67) connection between the optical fiber and the substrate structure due to a larger surface covered by adhesive material. In light of the foregoing analysis, the Chang – England combination teaches expressly or renders obvious all of the recited limitations. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20190250326 A1 US 11,614,592 B2 US 2023/0194778 A1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Jan 10, 2024
Application Filed
Jan 09, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+11.9%)
2y 4m
Median Time to Grant
Low
PTA Risk
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