Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detail Action
This office action is in response to amendment filed on 12/26/2025.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-10, 13, 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harland et al. (US 10,860,305 B 1).
Per claim 9,
Harland discloses
receiving, via a serial interface, a hold command to hold the first node in a reset mode, the first node being connected to the update controller via the serial interface; (c11:51-c12:63, discloses using BMC to perform management of firmware via communication channels including Serial Peripheral Interface (SPI); Fig. 1, c7: 27-65, see dispatch reset request to place server modules into reset mode.)
receiving, via the serial interface, a code image at a memory of the first node, the memory being connected to the serial interface; (Fig. 3, shows various components connected via SPI. C18: 10-50, where programmable logic device 616 can be CPLD and connected to SPI. c7: 47-64, Fig. 1, see flow element G, SPI channel firmware deployed)
receiving, via the serial interface, a release command from the update controller to release the first node from the reset mode; (c7:46- 64, see release reset command )
and
based on the release command, rebooting the first node and executing the code image. (continue, see restoring power…emerge from reset mode and restore the normal operation)
Per claim 10, the rejection of claim 9 is incorporated;
Harland discloses
wherein the first node receiving the code image at the memory of the first node is based on a serial interface target of the first node receiving a write request from a serial interface host of the update controller. (c7:35-45 discloses “Whether the server 100 has just been powered on or is in run-time, the process then proceeds in a similar fashion. The
control module 150 can dispatch a reset request at flow element D to the CPLD 130 for one or more of the server modules 110, 120-M.” appears to disclose a host and target )
Per claim 13, the rejection of claim 9 is incorporated;
Harland discloses
receiving the hold command is based on the first node receiving a reboot command from the update controller and receiving the reboot command is based on the reboot command being received by a group of nodes that include the first node. (continue, C7:30-45, see one or more server modules corresponding to a group of nodes.)
Per claim 15, the rejection of claim 9 is incorporated;
Harland discloses
wherein the serial interface is a serial peripheral interface or a quad serial peripheral interface. (c12:15-30, see SPI)
Per claim 16, the rejection of claim 9 is incorporated;
Harland discloses
wherein the memory of the first node is an on-chip volatile memory communicatively connected to the serial interface as a writeable target. (c13: 15-45, see System-on-chip (Soc) and volatile memory)
Per claim 17, the rejection of claim 9 is incorporated;
Harland discloses
wherein the first node is a first system on chip of a solid-state drive. (c9:15-45, or c22: 25-35, see SSD)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-8 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harland et al. (US 10,860,305 B 1) in view of Li (US 20160365109 A1)
Per claim 1,
Harland discloses
sending, via a serial interface, a hold command to hold a first node in a reset mode, the first node being connected to the update controller via the serial interface;(c11:51-c12:63, discloses using BMC to perform management of firmware via communication channels including Serial Peripheral Interface (SPI); Fig. 1, c7: 27-65, see dispatch reset request to place server modules into reset mode.)
writing, via the serial interface, a code image to a memory of the first node, the memory being connected to the serial interface; (c7: 47-64, see flow element G, SPI channel firmware deployed)
upon determining the code image is written to the memory, sending, via the serial interface, a release command to the first node to release the first node from the reset mode; (c7:46- 64, see release reset command after update complete)
Harland discloses
modifying, via the serial interface the code image of the first node. (continue, c7: 47-64, see flow element G, SPI channel firmware deployed)
Harland does not, however, Li discloses
based on detecting the first node is rebooted. ([0064]-[0067], see BMC detecting power signal from server…indicating rebooting and generate command for controlling of the server.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Li into the teachings of Harland to include the limitation disclosed by Li. The modification would be obvious to one of ordinary skill in the art to want to issue commands to device to properly setting the device as suggested by Li. ([0064-67])
Per claim 2, the rejection of claim 1 is incorporated.
Harland/ Li discloses
wherein writing the code image to the memory of the first node is based on a serial interface host of the update controller issuing a write request to a serial interface target of the first node. (Harland, c7:35-45 discloses “Whether the server 100 has just been powered on or is in run-time, the process then proceeds in a similar fashion. The
control module 150 can dispatch a reset request at flow element D to the CPLD 130 for one or more of the server modules 110, 120-M.” appears to disclose a host and target image, or unauthorized attempts.)
Per claim 3, the rejection of claim 1 is incorporated.
Harland/ Li discloses
wherein sending the hold command is based on the update controller sending a reboot command to the first node. (Harland, Fig. 1, c7: 27-65, see dispatch reset request to place server modules into reset mode... c7:46- 64, see release reset command… restoring power…emerge from reset mode and restore the normal operation)
Per claim 4, the rejection of claim 3 is incorporated.
Harland/ Li discloses
wherein sending the reboot command includes sending the reboot command to a group of nodes that include the first node. (continue, C7:30-45, see one or more server modules corresponding to a group of nodes.)
Per claim 7, the rejection of claim 1 is incorporated.
Harland/ Li discloses
wherein the serial interface is a serial peripheral interface or a quad serial peripheral interface. (Harland, c12:15-30, see SPI)
Per claim 8, the rejection of claim 1 is incorporated.
Harland/ Li discloses
wherein the update controller is a baseboard management controller (BMC). (Harland, c11:51-c12:63, discloses using BMC to perform management of firmware via communication channels including Serial Peripheral Interface (SPI)
Per claim 18, see rejection of claim 1.
Per claim 19, the rejection of claim 18 is incorporated;
Harland/ Li discloses,
wherein writing the code image to the memory of the first node is based on a serial interface host of the update controller issuing a write request to a serial interface target of the first node. (Harland, c7:35-45 discloses “Whether the server 100 has just been powered on or is in run-time, the process then proceeds in a similar fashion. The control module 150 can dispatch a reset request at flow element D to the CPLD 130 for one or more of the server modules 110, 120-M.” appears to disclose a host and target)
Per claim 20, the rejection of claim 18 is incorporated;
Harland/ Li discloses, wherein sending the hold command is based on the update controller sending a reboot command to the first node. (Fig. 1, c7: 27-65, see dispatch reset request to place server modules into reset mode…. release reset command and restoring power…emerge from reset mode and restore the normal operation)
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harland et al. (US 10,860,305 B 1) in view of Li (US 20160365109 A1) and further in view of Lee (KR 101815121 B1)
Per claim 6, the rejection of claim 1 is incorporated.
Harland/ Li does not disclose, however, Lee discloses
wherein sending the hold command is based on the update controller detecting that the first node is rebooting. (pp13, disclose rebooting object determining and then transmit reset command to perform reboot.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Lee into the teachings of Harland/Li to include the limitation disclosed by Lee. The modification would be obvious to one of ordinary skill in the art to want to resolve failure of device by carrying out reboot as suggested by Lee (see end of page 3)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harland et al. (US 10,860,305 B 1) in view of Newell (US 20150012737 A1)
Per claim 11, the rejection of claim 9 is incorporated;
Harland does not, however, Newell discloses
wherein executing the code image is based on a mask read-only memory of the first node initiating execution of an executable included in the code image that is stored in the memory. ([0018], discloses secure boot via on-chip mask ROM )
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Newell into the teachings of Harland to include the limitation disclosed by Newell. The modification would be obvious to one of ordinary skill in the art to want to enhance security via secure boot using mask ROM as suggested by Newell ([0018])
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harland et al. (US 10,860,305 B 1) in view of Lin (CN 109814900 A)
Per claim 12, the rejection of claim 9 is incorporated;
Harland discloses after rebooting. (c7:46- 64, see release reset command see restoring power…emerge from reset mode and restore the normal operation)
Harland does not, however Lin discloses
determining, that a status of the memory indicates the code image is removed from the memory. (pp. 7 last paragraph – pp. 8, 1st paragraph, discloses deleting firmware in a memory and set a flag value to 0.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Lin into the teachings of Harland to include the limitation disclosed by Lin. The modification would be obvious to one of ordinary skill in the art to want to – provide status of the memory in order to confirm deletion as suggested by Lin (see above)
Response to Arguments
Per claim 9 (and 10,13, 15-17), Applicant argues the hold command and the release command is not via a serial interface.
Applicant’s argument is based on Fig. 1 where Element G shown as associated with SPI firmware update. And reset and release is associated with CPLD 130 and CPLD is separated from SPI in Fig. 1.
In Fig. 1, the displayed flow elements A, B,…G, and H are steps as part of a process flow, which is not an illustration of communication channels including SPI.
For further clarification, the examiner wants to direct the attention to Harland, Fig. 3 showing how BMC connects to Peripheral device (370), Non-Volatile Memory (190), and other components of the system. They are connected via communication channel (310) including serial interface SPI (c12: 15-30). And therefore, data/commands communicating among components of a server can be considered using the same communication channel (310) including SPI which is considered serial interface.
Further, Harland, C18: 23-27, discloses commands are routed through the programmable logic device 616 using…SPI. C: 18:47-51, discloses the programmable logic device 616 may include …Complex Programmable Logic Device (CPLD)
Based on the above, CPLD 103 in Fig. 1 is connected to same SPI as explained above. And therefore, the reset and release commands are both communicated via the same SPI associated with CPLD.
Per claims 1-8 and 18-20, revised rejection with additional prior art is included.
Allowable Subject Matter
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
It is noted that any citation [[s]] to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. [[See, MPEP 2123]]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Wang whose telephone number is 571-272-5934. The examiner can normally be reached on Monday – Friday 8:00AM -4:00PM. Any inquiry of general nature or relating to the status of this application should be directed to the TC2100 Group receptionist: 571-272-2100.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock, can be reached at 571-272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHILIP WANG/Primary Examiner, Art Unit 2199
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