Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18410068 filed on 01/11/2024
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Election/Restrictions
Applicant’s election without traverse of (species 1 with figure 13B), claims 1-6, 8-10 and 12-15 in the reply filed on 5/12/2026 is acknowledged.
Allowable subject matter
Claim 15 is objected to as being dependent upon a rejected base claim (independent claim 9), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner' s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Xie et al. (US Pat 2022/0406715 A1).
With respect to dependent claim 15, the cited prior art does not anticipate or make obvious, inter alia, the step of: “a contact metal directly above and insulated from the second S/D region, the contact metal extending from a frontside S/D contact of the fourth S/D region of the second stack of transistors”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public
use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 6, 9 & 12-14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Xie et al. (US 2022/0406715 A1).
Regarding independent claim 1, Xie et al. teach a semiconductor structure comprising:
a first transistor (figs. 1, 2, 10A & 14A transistor comprises bottom most elements 6, 18, 80, 92 [0041] [0043] [0067] [0069]) having
a first source/drain (S/D) region (figs. 14A -14D, element 80 [0067]);
a second transistor (figs. 1, 2, 10A, 14A transistor comprises topmost elements 4, 18, 80, 92 [0041] [0043] [0067] [0069]) having
a second S/D region (figs. 14A -14D, element 1210 [0085]),
the second S/D region being on top of the first S/D region (fig. 14D element 1210 being top of element 80); and
a shared S/D contact (figs. 14A-14D element 1310 [0085]),
the shared S/D contact having a first portion (figs. 14A-14D, portion of element 1310 in element 72 which is labeled in fig. 13B [0064]) being in direct contact with a bottom surface (fig. 14D, bottom portion of element 1310 in element 1210 being in contact with bottom surface of element 1210) of the second S/D region of the second transistor and
a second portion (figs. 14A-14D, portion of element 1310 in element 80) being wrapped around by the first S/D region of the first transistor (fig. 14D, portion of element 1310 being wrapped around by element 80).
Regarding claim 2, Xie et al. teach the semiconductor structure further comprising
a backside S/D contact (element 1000 labeled in fig. 11 [0074]) in contact with a bottom surface of the second portion (figs. 14A-14D, portion of element 1310 in element 80 in contact with element 1000) of the shared S/D contact (figs. 14A-14D).
Regarding claim 3, Xie et al. teach the semiconductor structure,
wherein the first portion (figs. 14A-14D, portion of element 1310 in element 72 which is labeled in fig. 13B [0064]) of the shared S/D contact (figs. 14A-14D, element 1310 [0085]) has a first horizontal cross-section (figs. 14A-14D cross-section of element 1310 in element 72),
and the second portion (figs. 14A-14D, portion of element 1310 in element 80) of the shared S/D contact has a second horizontal cross-section (cross-section of element 1310 in element 80),
the first horizontal cross-section being larger than the second horizontal cross-section (fig. 14D, cross-section of element 1310 in element 72 is larger than the cross-section of element 1310 in element 80).
Regarding claim 4, Xie et al. teach the semiconductor structure,
wherein the backside S/D contact (element 1000 labeled in fig. 11 [0074]) has a third horizontal cross-section (cross-section of element 1000 labeled in fig. 11), the third horizontal cross-section being larger than the second horizontal cross-section (cross-section of element 1000 labeled in fig. 11 is larger than the cross-section of element 1310 in element 80 in figs. 14A-14D).
Regarding claim 5, Xie et al. teach the semiconductor structure,
wherein the first portion (figs. 14A-14D, portion of element 1310 in element 72 which is labeled in fig. 13B [0064]) of the shared S/D contact is in direct contact with a top surface of the first S/D region (figs. 14A -14D, top portion of element 80 [0067] [0085]) that surrounds the second portion (fig. 14D, portion of element 1310 in element 80) of the shared S/D contact.
Regarding claim 6, Xie et al. teach the semiconductor structure,
wherein the backside S/D contact (element 1000 labeled in fig. 11 [0074]) is in direct contact with a bottom surface (figs. 14A-14D, bottom surface of element 80) of the first S/D region (figs. 14A-14D, bottom surface of element 80 in contact with element 1000) that surrounds the second portion (figs. 14A-14D, portion of element 1310 in element 80) of the shared S/D contact.
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Regarding independent claim 9, Xie et al. teach a semiconductor structure comprising:
a first stack of transistors (see annotated figure above) having a first source/drain (S/D) region (see annotated figure above)
and a second S/D region (see annotated figure above), the second S/D region being on top of the first S/D region (see annotated figure above);
a second stack of transistors (see annotated figure above) having a third S/D
region (see annotated figure above) and
a fourth S/D region (see annotated figure above), the fourth S/D region being on top of the third S/D region (see annotated figure
above),
the second stack of transistors being adjacent (see annotated figure above) to the first stack of transistors; and
a shared S/D contact (figs. 14A-14D, element 1310 [0085]),
the shared S/D contact having a first portion (figs. 14A-14D, portion of element 1310 in element 72 which is labeled in fig. 13B [0064]) being in direct contact with a bottom surface of the second S/D region (fig. 14D, bottom portion of element 1310 in element 1210)
and a second portion (figs. 14A-14D, portion of element 1310 in element 80) being wrapped around by the first S/D region (fig. 14D, portion of 1310 being wrapped around by element 80).
Regarding claim 12, Xie et al. teach the semiconductor structure, further comprising
a backside interconnect structure (figs. 14A-14D, element 1020 [0074]), underneath the first and the second stack of transistors (fig.14A -14D),
and a backside S/D contact (element 1000 labeled in fig. 11 [0074]),
wherein the second portion of the shared S/D contact (fig. 14A-14D, portion of element 1310 in element 80) is conductively connected to the backside interconnect structure by the backside S/D contact (figs. 14 A-14D).
Regarding claim 13, Xie et al. teach the semiconductor structure,
the first portion of the shared S/D contact (figs. 14A-14D, portion of element 1310 in element 72 which is labeled in fig. 13B) is in direct contact with a top surface (figs. 14A-14D, top portion of element 80 [0085]) of the first S/D region that surrounds the second portion (fig. 14A-14D, portion of element 1310 in element 80) of the shared S/D contact.
Regarding claim 14, Xie et al. teach the semiconductor structure,
wherein backside S/D contact (element 1000 labeled in fig. 11 [0074]) is in direct contact with a bottom surface (figs. 14A-14D, bottom surface of element 80) of the first S/D region (figs. 14A -14D, element 80 [0067]) that surrounds the second portion (fig. 14A-14D, portion of element 1310 in element 80) of the shared S/D contact.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2022/0406715 A1) in view of Morrow et al. (US 2019/0259699 A1).
Regarding claim 8, Xie et al. teach the semiconductor structure, further comprising
a contact metal (figs. 14A-14D, element 1300 [0080]) directly above the second S/D region (figs. 14A -14D, element 1210 [0085]) of the second transistor,
Xie et al. do not explicitly teach a contact metal insulated from the second S/D region and extending from a frontside S/D contact of a nearby transistor.
However, Morrow et al. is a pertinent art which teaches a contact metal (fig. 13B, element 990 [0041]) insulated (fig. 13B, element 980 [0041]) from the second S/D region (fig. 13B, element 260 [0030]) and extending from a frontside S/D contact (fig. 13B, element 250 labeled in fig. 9B [0041]) of a nearby transistor (fig. 13B, element 240 [0041])
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective date of claimed invention to modify the semiconductor device of Xie et al. to include the metal interconnect as taught by Morrow et al. with the motivation to provide interconnection inside the semiconductor device.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2022/0406715 A1).
Regarding claim 10, Xie et al. teach the semiconductor structure,
wherein the third S/D region (see annotated figure above) is insulated from the fourth S/D region (see annotated figure above) of the second stack of transistors (see annotated figure above) by a middle- dielectric-insulator (MDI) layer (fig. 14A-14D, element 72 which is labeled in fig. 13B [0089]).
a thickness of the MDI layer is substantially same as a thickness of the first portion of the shared S/D contact. (Xie et al. teach the thickness of a semiconductor layer and die electric layer can be varied [0049] [0078], a portion of the ILD has remained to isolate the bottom S/D epi to top S/D epi, and the remaining thickness of the ILD is thicker or with comparable thickness as MDL [0078]. Xie et al. further teach the thickness of the MDI layer to be substantially same as a thickness of the first portion of the shared S/D contact in order to retain enough of the ILD to isolate the top S/D epi from the bottom S/D epi while keeping the internal stitch contact between them as short as possible [0078] [0081]. Therefore, the thickness of MDI layer and first portion of S/D contact is a result effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness of the MDI layer is substantially same as a thickness of the first portion of the shared S/D contact in order for the contact to extend across the remaining thickness of the ILD that separates the top S/D epi from the bottom S/D epi and thereby provide the internal connection between them as taught by Xie et al. MPEP 2144.05. Additionally, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thickness).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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