CTNF 18/410,182 CTNF 91895 2842 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Henson (US 3,805,092) in view of Gilbert (US 7,310,656) . Regarding claims 1 and 19 , Henson teaches a logarithmic current to voltage converter and corresponding method (Abstract; Col. 1, lines 40-45). Henson discloses an input terminal configured to receive an input current (e.g., i x + I R applied to the collector electrodes) (FIG. 2; FIG. 3; Col. 3, lines 38-42). Henson teaches a logarithmic bipolar transistor (e.g., Q1) having a collector connected to the input terminal and an emitter configured to generate a logarithmic output voltage (using the exponential/logarithmic current-voltage relationship of the base-emitter junction) (FIG. 1; Col. 2, lines 34-55). Furthermore, Henson teaches an emitter resistance compensation circuit that generates a compensation signal (current i c flowing through compensation resistor R c ) operable to adjust the logarithmic voltage to correct for an error arising from the ohmic emitter resistance (R e ) of the logarithmic bipolar transistor (FIG. 2; FIG. 3; Col. 3, lines 46-55; Col. 4, lines 18-29). PNG media_image1.png 435 633 media_image1.png Greyscale Fig. 3 of Henson : Compensatory biasing techniques for Q1-Q4. Henson does not disclose a "photocurrent detection system" comprising a "photodetector configured to generate an input current" as required by claim 16 . Additionally, for claims 1, 16, and 19 , Henson does not disclose that the emitter resistance compensation circuit comprises a "replica" or "scaled replica" of the logarithmic bipolar transistor, nor does it disclose that this circuit is configured to receive a "copy" or "scaled copy of the input current" to generate the compensation signal. PNG media_image2.png 309 490 media_image2.png Greyscale Fig. 12 of Gilbert : an adaptive bias 20 scheme for a sensor for a logarithmic circuit. Gilbert, which is in the same field of endeavor (logarithmic circuits and amplifiers), teaches the missing limitations. Regarding claim 16 , Gilbert teaches a photocurrent detection system comprising a photodetector (a photodiode 22) that generates an input signal current (I 1 or I PD ) for the logarithmic circuit (FIG. 12; Col. 6, lines 10-34). Regarding claims 1, 16, and 19, Gilbert teaches an emitter resistance (R E ) compensation circuit that utilizes a "suitably scaled" replica of the primary logarithmic bipolar transistor (transistor Q 3 , which is a scaled-down replica, e.g., one-fiftieth the size of Q 1 ) (FIG. 10; FIG. 11; Col. 5, lines 39-49; Col. 5, lines 52-60). Gilbert further teaches that this replica transistor (Q 3 ) operates at a lower current level and receives a scaled copy of the input current (because its base is connected directly to the base of Q 1 ) to generate a compensating voltage across a resistor (R3) that "precisely cancels the voltage across R E (FIG. 10; Col. 5, lines 39-44). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the logarithmic converter and emitter resistance compensation circuit of Henson by incorporating a photodetector to supply the input current, and by implementing the emitter resistance compensation circuit using a scaled replica transistor configured to receive a scaled copy of the input current, as taught by Gilbert. The motivation to modify Henson's circuit to receive an input current from a photodetector is to allow the logarithmic circuit to measure signal currents from photodiodes, because the logarithmic characteristic allows a "very wide range of signal currents to be represented in a conveniently compressed format," which is highly beneficial in fiber-optic systems (Gilbert: Col. 6, lines 14-20). Furthermore, the motivation to implement the emitter resistance compensation using a scaled replica transistor driven by a scaled copy of the input current is to accurately translate the intrinsic base-emitter voltage while avoiding the need for extremely small, inaccurate resistors, thereby preventing the use of "excessive die area" on an integrated circuit and minimizing "the total current consumed by the integrated circuit" (Gilbert: Col. 5, lines 47-49; Col. 5, lines 55-58). A person of ordinary skill in the art would recognize that combining Gilbert's scaled replica topology with Henson's logarithmic converter yields the predictable result of highly accurate logarithmic conversion at high current levels while optimizing both power consumption and physical chip area. Regarding claims 2, 17, and 20 (Compensation Signal Proportional to Emitter Resistance), Henson teaches an electronic analog multiplier acting as a logarithmic converter that includes an emitter resistance compensation circuit generating a compensation current (ic) to correct for loop errors arising from the emitter resistances (Re) of the transistors. Henson, however, does not disclose the specific replica transistor framework established in the baseline rejection. Gilbert, in the same filed of endeavor, teaches an emitter resistance compensation scheme where a compensating voltage is generated across a resistor (R3) to match the magnitude of the error voltage (I1*R E ), inherently making the compensation signal directly proportional to the emitter resistance (R E ). It would have been obvious to modify Henson’s compensation loop to generate a compensation signal proportional to the emitter resistance as taught by Gilbert to precisely track and dynamically cancel out the non-linear errors introduced by the internal emitter resistance across a wide range of operating currents. Regarding Claims 7 and 8 (Scaled Current Copy and Scaled Replica Transistor), Henson teaches an emitter resistance compensation circuit but utilizes full-sized loop transistors operating at nominal current levels. Henson, however, fails to teach scaling down the replica transistor or scaling down the copy of the input current. Gilbert, in a similar filed of endeavor, explicitly teaches that the replica transistor (Q3) is "suitably scaled" down in size relative to the primary log transistor (Q1), such as being one-fiftieth of its size, which consequently forces it to receive a scaled-down copy of the input current. It would have been obvious to modify Henson’s circuit layout by scaling down the compensation components in accordance with Gilbert’s teachings. Scaling down the replica transistor raises the required value of the compensation resistor proportionally, which prevents the need to fabricate highly inaccurate, low- value resistors on-chip, thereby saving substantial "die area" and minimizing "the total current consumed by the integrated circuit". Regarding Claim 15 (Input Current Source), Henson discloses input terminals that receive input signals expressed as currents (i x , i y ). Henson, however, does not explicitly illustrate an independent current source component generating the current within the baseline framework. Gilbert, in a similar field of endeavor, explicitly illustrates an input current source (I1) connected to the input terminal to generate the input current driving the log transistor. It would have been obvious to configure Henson’s input terminals with a dedicated current source as shown by Gilbert because It represents a ubiquitous and standard design choice in the field of analog design to provide a reliable, stable, and predictable input current to a logarithmic compression network. Allowable Subject Matter Claim 3-6, 9-14 and 18 are objected to as being dependent upon a rejected base claim 1 and 16 respectively but would be allowable if rewritten in independent form including all the limitations of the base claim 1 and 16 respectively and any intervening claims. The following claims are allowable because the cited prior arts fail to disclose or render obvious specific structural configurations as claimed: Claim Number(s) Key Structural Limitation(s) Missing from Prior Art Detailed Reason for Allowability Claims 3, 4, 5, 6, and 18 Compensation circuit using a pair of bipolar transistors to sense a difference voltage based on the emitter resistance times a scaled current; current density ratio 4:1; PTAT biasing. Absent Topology: Gilbert’s compensation circuit relies on a single replica transistor (Q3) and a single resistor (R3) connected between its collector and base to drop the error voltage. Neither Gilbert nor Henson teaches or suggests a compensation sub-circuit comprising a pair of transistors configured to differentially sense a voltage drop driven by a current density ratio or a PTAT bias current. Claims 9, 10, and 11 Logarithmic output voltage taken differentially between the emitters of the log transistors; Output amplifier receiving this differential voltage. Opposite Circuit Topology: In Gilbert’s differential log-ratio circuit (FIG. 7), the emitters of the log transistors (Q1, Q2) are tied directly to a fixed ground reference, and the differential output voltage ( d V BE ) is taken strictly from their bases . The references offer no disclosure or motivation to rearrange the core translinear layout to extract a differential voltage across the emitters while driving the collectors. Claims 12, 13, and 14 Bipolar transistor connected to the emitter of the log transistor; emitter resistor to ground; FET gate connected to the log transistor collector and source connected to the base of the secondary BJT. Missing Interconnected Feedback Sub-circuit: While Gilbert generically mentions that a MOS source-follower can be used to prevent base current errors, neither reference discloses or renders obvious this specific, multi-element interconnected buffer configuration (FET driving the base of a secondary BJT cascode/buffer connected directly to the log transistor's emitter). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843. 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