DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The use of the term Wi-Fi®, which is a trade name or a mark used in commerce, has been noted in this application (Paragraph 43, line 3). The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 and 11 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sato et al. (Patent Publication Number US 2021/0242836 A1), hereafter referred to as Sato.
Regarding claim 1, Sato discloses:
A semiconductor device (Sato, Fig. 1, 10), comprising: a plurality of unit transistors (Fig. 1, 101-10n), each of which is disposed on a semiconductor substrate (Paragraph 40, lines 1-3) and comprises a collector electrode (Fig. 1, see collectors of 101-10n) configured to output an output signal (Fig. 1, see signal output 171 and connection to collectors of 101-10n), a base electrode (Fig. 1, see bases of 101-10n) configured to receive an input signal (Fig. 1, see signal input 161 and connection to bases of 101-10n), and an emitter electrode (Fig. 1, see emitters of 101-10n); and an emitter junction wiring (Fig. 3, consider 351 and layers of W1) interconnecting emitter electrodes of the plurality of unit transistors (Fig. 3, see emitter wirings 351 and W1 connecting transistors 101 and 102), wherein, in a thickness direction of the semiconductor substrate, a portion of the emitter junction wiring positioned between at least two unit transistors adjacent to each other among the plurality of unit transistors (Fig. 3, consider section of emitter wiring formed by W1 and 351 between transistors 101 and 102) and another portion of the emitter junction wiring positioned outside of the two unit transistors (Fig. 3, consider section of emitter wiring formed by W1 and 351 outside transistors 101 and 102) have different thicknesses (Fig. 3, consider that thickness of W1 between transistors 101 and 102 is different than thickness of W1 outside of transistors 101 and 102 due to insulating layer 323 removing some thickness of W1 outside of transistors 101 and 102).
Regarding claim 2, Sato further discloses:
wherein: the emitter junction wiring comprises a junction portion (Sato, Fig. 3, 351) connected to the emitter electrode of one unit transistor of the plurality of unit transistors (Fig. 3, see connection between 351 and emitter electrode 333) and a wiring portion (Fig. 3, W1) extending to connect the emitter electrode of another unit transistor of the plurality of unit transistors (Fig. 3, see connection between emitter electrodes of 101 and 102 via W1); and a first thickness of a portion of the wiring portion positioned outside the two unit transistors is different from a second thickness of another portion of the wiring portion positioned between the two unit transistors (Fig. 3, see that thickness of W1 between transistors 101 and 102 is different than thickness of W1 outside of 101 and 102 due to insulating layer 323 removing some thickness of W1 outside of transistors 101 and 102).
Regarding claim 3, Sato further discloses:
wherein the wiring portion extends in a direction perpendicular to the thickness direction of the semiconductor substrate (Sato, Fig. 3, see that W1 extends beyond 101 and 102 in x-direction of Fig. 3), and the junction portion protrudes from the wiring portion in the thickness direction of the semiconductor substrate (Fig. 3, see that 351 protrudes from W1 in z-direction of Fig. 3).
Regarding claim 4, Sato further discloses:
wherein the second thickness is greater than the first thickness (Sato, Fig. 3, see that thickness of W1 between transistors 101 and 102 is greater than thickness of W1 outside of 101 and 102 due to insulating layer 323 removing some thickness of W1 outside of transistors 101 and 102).
Regarding claim 5, Sato further discloses:
further comprising a collector wire (Sato, Fig. 3, 341 and 3411) connected to the collector electrode (Fig. 3, see connection between 341 and collector electrode 332), and disposed between the collector electrode and the emitter junction wiring (Fig. 3, see connection between collector electrode 332 and emitter junction wiring W1 via 341 and 322), wherein, in the thickness direction of the semiconductor substrate, a portion of the collector wire positioned outside of the two unit transistors (Fig. 3, consider portion 3411a of 3411 in modified Fig. 3 below) and another portion of the collector wire positioned between the two unit transistors (Fig. 3, consider portion 341b of 341 in modified Fig. 3 below) have different thicknesses (Fig. 3, consider that thickness of 3411a is different than thickness of 341b in modified Fig. 3 below).
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Regarding claim 6, Sato further discloses:
wherein: the collector wire comprises a connection portion (Sato, Fig. 3, see 3411 and 341) connected to the collector electrode (Fig. 3, see connection between 341 and 332); and a third thickness of the connection portion positioned outside of the two unit transistors is different from a fourth thickness of the connection portion positioned between the two unit transistors (Fig. 3, see that thickness of portion 3411a outside of transistors 101 and 102 is different than thickness of portion 341b between transistors 101 and 102 in modified Fig. 3 above).
Regarding claim 7, Sato further discloses:
wherein the third thickness is greater than the fourth thickness (Sato, Fig. 3, see that thickness of portion 3411a is greater than thickness of portion 341b in modified Fig. 3 above).
Regarding claim 8, Sato further discloses:
further comprising an insulation material (Sato, Fig. 3, 322) covering the collector wire on the semiconductor substrate (Fig. 3, see connection between 322 and collector wires 341 and 3411), wherein the emitter junction wiring is disposed to form an interface, and be in contact, with the insulation material (Fig. 3, see connection between emitter junction wirings W1 and 351 with 322).
Regarding claim 9, Sato further discloses:
wherein each of the plurality of unit transistors is a bipolar transistor (Sato, Fig. 1, see that transistors 101-10n are bipolar transistors) that comprises a collector layer corresponding to the collector electrode (Fig. 3, 332), a base layer corresponding to the base electrode (Fig. 3, 331), and an emitter layer corresponding to the emitter electrode (Fig. 3, 333).
Regarding claim 11, Sato further discloses:
wherein the emitter junction wiring comprises gold (Au) (Sato, Paragraph 79, lines 5-10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sato as applied to claim 1 above, and further in view of Sasaki et al. (Patent Publication Number TW 202025621 A), hereafter referred to as Sasaki.
Regarding claim 10, Sato fails to disclose:
further comprising a metal pillar disposed to be in contact with the emitter junction wiring.
However, Sasaki teaches further comprising a metal pillar (Sasaki, Fig. 4, 52) disposed to be in contact with the emitter junction wiring (Fig. 4, see connection between 52 and 74).
Sato and Sasaki are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Sato to incorporate the teachings of Sasaki to include the metal pillar of Sasaki in the circuit of Sato, which would have the effect of increasing thermal stability (Sato, Page 2, Paragraph 5, lines 1-5).
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Kondo et al. (Patent Publication Number CN 110,391,196 A), hereafter referred to as Kondo.
Regarding claim 12, Sato further discloses:
A power amplifier (Sato, Fig. 1, 10) for amplifying an RF input signal (Fig. 1, see RFin) and outputting an RF output signal (Fig. 1, see RFout), the power amplifier comprising: a plurality of unit transistors (Fig. 1, 101-10n), each of which is disposed on a semiconductor substrate (Paragraph 40, lines 1-3) and comprises a collector electrode (Fig. 1, see collectors of 101-10n) configured to output the RF output signal (Fig. 1, see signal output 171 and connection to collectors of 101-10n), a base electrode (Fig. 1, see bases of 101-10n) configured to receive the RF input signal (Fig. 1, see signal input 161 and connection to bases of 101-10n), and an emitter electrode (Fig. 1, see emitters of 101-10n); an emitter junction wiring (Fig. 3, consider 351 and layers of W1) interconnecting the emitter electrodes of the plurality of unit transistors (Fig. 3, see emitter wirings 351 and W1 connecting transistors 101 and 102); wherein, in a thickness direction of the semiconductor substrate, a portion of the emitter junction wiring positioned between at least a two unit transistors adjacent to each other among the plurality of unit transistors (Fig. 3, consider section of emitter wiring formed by W1 and 351 between transistors 101 and 102) and another portion of the emitter junction wiring positioned outside of the two unit transistors (Fig. 3, consider section of emitter wiring formed by W1 and 351 outside transistors 101 and 102) have different thicknesses (Fig. 3, consider that thickness of W1 between transistors 101 and 102 is different than thickness of W1 outside of transistors 101 and 102 due to insulating layer 323 removing some thickness of W1 outside of transistors 101 and 102), but fails to disclose and a circuit board on which the plurality of unit transistors are mounted.
However, Kondo teaches and a circuit board (Kondo, Fig. 1C, 20) on which the plurality of unit transistors are mounted (Fig. 1C, consider connection between circuit board 20 and power amplifier circuit 30).
Sato and Kondo are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Sato to incorporate the teachings of Kondo to include the circuit board of Kondo to mount the transistors of Sato, which would have the effect of providing a well-known implementation to incorporate the circuit of Sato as a semiconductor device (Kondo, Page 5, Paragraph 5, lines 1-2).
Regarding claim 13, Sato further discloses:
wherein: the emitter junction wiring comprises a junction portion (Sato, Fig. 3, 351) connected to the emitter electrode of one unit transistor of the plurality of unit transistors (Fig. 3, see connection between 351 and emitter electrode 333) and a wiring portion (Fig. 3, W1) extending to connect the emitter electrode of another unit transistor of the plurality of unit transistors (Fig. 3, see connection between emitter electrodes of 101 and 102 via W1); and a first thickness of a portion of the wiring portion positioned outside the two unit transistors is different from a second thickness of another portion of the wiring portion positioned between the two unit transistors (Fig. 3, see that thickness of W1 between transistors 101 and 102 is different than thickness of W1 outside of 101 and 102 due to insulating layer 323 removing some thickness of W1 outside of transistors 101 and 102).
Regarding claim 14, Sato further discloses:
further comprising a collector wire (Sato, Fig. 3, 341 and 3411) connected to the collector electrode (Fig. 3, see connection between 341 and collector electrode 332), and disposed between the collector electrode and the emitter junction wiring (Fig. 3, see connection between collector electrode 332 and emitter junction wiring W1 via 341 and 322), wherein, in the thickness direction of the semiconductor substrate, a portion of the collector wire positioned outside of the two unit transistors (Fig. 3, consider portion 3411a of 3411 in modified Fig. 3 above) and another portion of the collector wire positioned between the two unit transistors (Fig. 3, consider portion 341b of 341 in modified Fig. 3 below) have different thicknesses (Fig. 3, consider that thickness of 3411a is different than thickness of 341b in modified Fig. 3 below).
Regarding claim 15, Sato further discloses:
wherein: the collector wire comprises a connection portion (Sato, Fig. 3, see 3411 and 341) connected to the collector electrode (Fig. 3, see connection between 341 and 332); and a third thickness of the connection portion positioned outside of the two unit transistors is different from a fourth thickness of the connection portion positioned between the two unit transistors (Fig. 3, see that thickness of portion 3411a outside of transistors 101 and 102 is different than thickness of portion 341b between transistors 101 and 102 in modified Fig. 3 above).
Regarding claim 16, Sato further discloses:
wherein each of the plurality of unit transistors is a bipolar transistor (Sato, Fig. 1, see that transistors 101-10n are bipolar transistors) that comprises a collector layer corresponding to the collector electrode (Fig. 3, 332), a base layer corresponding to the base electrode (Fig. 3, 331), and an emitter layer corresponding to the emitter electrode (Fig. 3, 333).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wood (Patent Publication Number US 2017/0287721 A1) discloses (Fig. 38B) a semiconductor power amplifier device.
Kurokawa et al. (Patent Number US 12,009,273 B2) discloses (Fig. 1) a semiconductor power amplifier device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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