DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US 2011/0148376) in view of Feil et al. (US 2019/0326277).
Regarding Claim 1, Xu discloses an electronic circuit (Figures 1-8), comprising:
a first transistor device (102, Figure 1, 318, Figure 3, corresponding element/s in other Figures) comprising a first drive node, a second drive node, and a load path (comprising gate, source and a load path between 104 and 106, Figure 1, 318 having a gate, source, and a load path between320 and 334, Figure 3); and
a protection circuit (comprising 110 and its biasing circuit, Figure 1, comprising 326 and its biasing circuit, Figure 3) coupled to the first and second drive nodes and the load path of the first transistor device (comprising 110 and its biasing circuit coupled to 112/gate and 116/source and to load path between 104, 106, Figure 1, 326 and its biasing circuit coupled to 322/gate and 334/source and to load path between 320, 334, Figure 3), wherein the protection circuit comprises:
a second transistor device (110, Figure 1, 326, Figure 3) comprising a first drive node, a second drive node, and a load path connected between the first and second drive nodes of the first transistor device (110 having a first drive node/gate, second drive node/source and a load path between 112, 116 , Figure 1, 326 having a first drive node/gate, second drive node/source and a load path between 322,/330 and 332/334, Figure 3); and
a capacitor (118, Figure 1, 336, Figure 3) coupled between the load path of the first transistor device and the first drive node of the second transistor device (118 coupled between 104 and 114, Figure 1, 336 coupled between 320 and 328, Figure 3).
Xu does not specifically disclose that a capacitance of the capacitor is voltage dependent such that the capacitance decreases as a voltage across the capacitor increases.
Feil discloses an electronic circuit (Figures 1-17), comprising:
a first transistor device (comprising 1, Figures 1-4, 6-8) comprising a first drive node, a second drive node, and a load path (comprising gate G1, source S1 and a load path between D1, S1); and
a protection circuit (comprising 2, 3, Figures 1-4, 6, 12A-17) coupled to the first and second drive nodes and the load path of the first transistor device (2, 3 coupled between D1, S1), wherein the protection circuit comprises:
a second transistor device (2, Figures 1-4, 6, 12A-17) comprising a first drive node, a second drive node, and a load path (2 having a first drive node/G2, second drive node/S2 and a load path D2-S2); and a threshold detection circuit (3, Figures 1-4, 6) comprising
a capacitor (31, Figures 1-4, 6, 12A-17) coupled between the load path of the first transistor device and the first drive node of the second transistor device (31 coupled between D1, G2, Figures 1-4, 12, 14A-14B,16-17) and a resistor (32, Figures 1-4, 6, 12A-17) coupled between the first and second drive nodes of the second transistor (32 coupled between G2 and S2 nodes of 2, Figures 1-4, 12, 14A-14B,16-17), wherein the resistor comprises a plurality of resistive conductors arranged in respective trenches in a semiconductor body and electrically insulated from the semiconductor body by an insulating layer (comprising 341, Figures 12A-12B, Paragraph 65, “….the resistor 32 includes several conductors arranged in several trenches and connected in parallel….”),
wherein a capacitance of the capacitor is voltage dependent (31 formed as trench capacitors having capacitor electrodes 311, 43, Figures 12A-12B, 13-16, Paragraph 51, “….capacitor electrode 311 arranged in a trench of the semiconductor body 100…a second electrode of the capacitor cell is formed by the common drain electrode 43 and those regions 314, 315 of the semiconductor body 100 arranged between the common drain electrode 43 and the capacitor dielectric 312 …”, Paragraph 61, note that capacitor of Feil, being a MOS structure, capacitance depends on the voltage applied on the metal/gate, and referred as CV characteristic/curve).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the capacitor in the electronic circuit of Xu as a capacitor having voltage dependent capacitance as taught by Feil, such that capacitor and resistor (biasing elements in the protection circuit) can be implemented on same substrate using same technology as transistors and to select the type of semiconductor substrate and doped regions to achieve desired capacitor CV characteristics such that the capacitance decreases as a voltage across the capacitor increases (note that Feil disclose n-type transistors in Figures, and discloses in Paragraph 41 p-type transistors, capacitance of a PMOS capacitor decreases as a voltage across the capacitor increases).
Regarding Claim 2, combination of Xu discloses the electronic circuit of Claim 1, wherein the protection circuit further comprises a resistor (120, Figure 1, 338, Figure 3) connected between the first and second drive nodes of the second transistor device (120 coupled between 114, 116, Figure 1, 326 coupled between the first dive nide 328 and the second drive node 332 of 326, Figure 3).
Regarding Claim 3, combination of Xu and Feil discloses the electronic circuit of Claim 1, wherein the capacitor comprises:
a plurality of capacitor trenches each extending from a first surface into a semiconductor body (semiconductor body 100 having a first surface 101 and second surface 102 shown in Figure 6, Figures 12A-12BC, Paragraph 51, “….capacitor electrode 311 arranged in a trench of the semiconductor body 100…a second electrode of the capacitor cell is formed by the common drain electrode,,,”); a plurality of semiconductor mesa regions, wherein each semiconductor mesa region is formed between a respective pair of the plurality of capacitor trenches (comprising region around 312, Figures 12A-12B); and a trench electrode arranged in each of the capacitor trenches and dielectrically insulated from the semiconductor body (comprising 311 insulated from 100 by capacitor dielectric 312, Figures 12A-12B, Paragraphs 52-53), wherein the semiconductor mesa regions are connected to a first node of the capacitor (connection to common drain nide 43, Figures 12A-12B), and wherein the trench electrodes are connected to a second node of the capacitor (311 connected to 61, Figures 12A-12B, Paragraphs 52-53).
Regarding Claim 4, combination of Xu and Feil discloses the electronic circuit of Claim 3, wherein the semiconductor mesa regions are doped regions of a first doping type (Paragraph 41, “…The source region 12 and the drift region 11 have the same doping type and the body region 13 has a doping type complementary to the first doping type…an n-type MOSFET, the source region 12 and the drift region 11 are n-doped regions while the body region 13 is a p-doped region”, Paragraphs 49, 51), wherein the capacitor further comprises a plurality of doped regions of a second doping type complementary to the first doping type, wherein each of the doped regions of the second doping type adjoins a respective one of the semiconductor mesa regions and is connected to the second node of the capacitor (Paragraph 41, “the drain region 14 has the same doping type as the drift region 11 and the source region 12…”, Paragraphs 49, 51).
Regarding Claim 5, combination of Xu and Feil discloses the electronic circuit of Claim 3, wherein the semiconductor body comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer (first semiconductor layer 315 and second semiconductor layer 314 of 100, Figure 12A, Paragraph 51), wherein the capacitor trenches are formed in the second semiconductor layer (capacitor trenches formed in 314, Figure 12A, Paragraph 51).
Regarding Claim 6, combination of Xu and Feil discloses the electronic circuit of Claim 5, wherein the capacitor further comprises a first electrode layer formed on a surface of the first semiconductor layer facing away from the second semiconductor layer (comprising 313, 316, 61, Figure 12A, Paragraph 53), and wherein the first electrode layer forms the first circuit node of the capacitor (Figure 12A, Paragraph 53).
Regarding Claim 7, combination of Xu and Feil discloses the electronic circuit of Claim 6, wherein the capacitor further comprises a second electrode layer formed on a surface of the second semiconductor layer facing away from the first semiconductor layer (comprising 43, Figure 12A, Paragraph 51), and wherein the second electrode layer forms the second circuit node of the capacitor (Paragraph 51, “…second capacitor electrode of the capacitor cell is formed by the common drain electrode 43 and those regions 314, 315 of the semiconductor body 100 arranged between the common drain electrode 43…”).
Regarding Claim 8, combination of Xu and Feil discloses the electronic circuit of Claim 3, wherein the first transistor device comprises a plurality of transistor cells integrated in a semiconductor body (Xu, Figure 2, Paragraphs 24-25, Feil, Figure 6, Paragraph 38, transistor cell 10, Figures 7-8), wherein each transistor cell comprises a field electrode (17, Figures 8) arranged in a field electrode trench extending from a first surface into the semiconductor body and dielectrically insulated from a drift region of the transistor cell (( 17 arranged in trenches extending from first surface 101 into body region 13 and electrically insulated from drift region 11, Figure 8).
Regarding Claim 9, combination of Xu and Feil discloses the electronic circuit of Claim 8, wherein at least one of the following applies: a depth of the capacitor trenches is larger than a depth of the field electrode trenches, a width of the capacitor trenches is larger than a width of the field electrode trenches (capacitor trenches in Figure 12A shown with larger width than field electrode trenches in Figure 8), a width of the semiconductor mesa regions between the capacitor trenches is smaller than a width of semiconductor mesa regions between field electrode trenches (mesa region/space between trenches in Figure 12A smaller than that between the trenches in Figure 8).
Regarding Claim 10, combination of Xu and Feil discloses the electronic circuit of Claim 1, wherein the first transistor device, the second transistor device, and the capacitor are integrated in a same semiconductor body (Xu, Figure 2, Paragraphs 24-25, Feil, Figure 6 shows transistor 1, transistor 2 and protection circuit 3 on semiconductor body 100, Paragraph 38).
Regarding Claim 11, combination of Xu and Feil discloses the electronic circuit of Claim 10, wherein the second transistor device is integrated in a semiconductor region that is dielectrically insulated from a remainder of the semiconductor body (Feil, Figure 6, 2, 3 integrated in a second region 120 and 1 integrated in a first region 110, Paragraph 38).
Regarding Claim 12, combination of Xu and Feil discloses the electronic circuit of Claim 10, wherein the semiconductor body includes an inner region, wherein the transistor cells of the first transistor device are integrated in the inner region, and wherein the protection circuit is integrated in the inner region (Figure 6, Paragraph 38).
Regarding Claim 13, combination of Xu and Feil discloses the electronic circuit of Claim 10, wherein the semiconductor body includes an inner region, in which the transistor cells of the first transistor device are integrated (Figures 6-8, Paragraphs 38-43), and an edge region, and wherein the protection circuit is integrated in the edge region (Figures 6,12A-12C, Paragraphs 38, 47)
Regarding Claim 14, combination of Xu and Feil discloses the electronic circuit of Claim 1, wherein the load path of the first transistor device comprises a first load path node (104, Figure 1, 320, Figure 3) and a second load path node (106, Figure 1, 334, Figure 3), and wherein the capacitor is connected between the first load path node of the first transistor device and the first drive node of the second transistor device (118 connected between 104 and 114, Figure 1, 336 connected between 320 and 328, Figure 3).
Claim 15 recites a method corresponding the electronic circuit of Claim 1 (Xu, Paragraph 24 discloses the operation of the electronic circuit describing turning off the first transistor). Therefore Claim 15 is rejected at least for the same reasons as for Claim 1.
Regarding Claim 16, Xu discloses an electronic circuit (Figures 1-8), comprising:
a first transistor device (102, Figure 1, 318, Figure 3, corresponding element/s in other Figures) comprising a first drive node, a second drive node, and a load path (comprising gate, source and a load path between 104 and 106, Figure 1, 318 having a gate, source, and a load path between320 and 334, Figure 3); and
a protection circuit (comprising 110 and its biasing circuit, Figure 1, comprising 326 and its biasing circuit, Figure 3) coupled to the first and second drive nodes and the load path of the first transistor device (comprising 110 and its biasing circuit coupled to 112/gate and 116/source and to load path between 104, 106, Figure 1, 326 and its biasing circuit coupled to 322/gate and 334/source and to load path between 320, 334, Figure 3), wherein the protection circuit comprises:
a second transistor device (110, Figure 1, 326, Figure 3) comprising a first drive node, a second drive node, and a load path connected between the first and second drive nodes of the first transistor device (110 having a first drive node/gate, second drive node/source and a load path between 112, 116 , Figure 1, 326 having a first drive node/gate, second drive node/source and a load path between 322,/330 and 332/334, Figure 3); and
a capacitor (118, Figure 1, 336, Figure 3) coupled between the load path of the first transistor device and the first drive node of the second transistor device (118 coupled between 104 and 114, Figure 1, 336 coupled between 320 and 328, Figure 3),
wherein a first capacitor node is connected to the load path node of the first transistor device and a second capacitor node is connected to the first drive node of the second transistor (a first capacitor node of 118 connected to the load path node 104 a second capacitor node of 118 connected to the drive node 114 of the second transistor 326, Figure 1, a first node of 336 connected to load path node 320 and a second capacitor node of 336 connected to the drive node 328 of the second transistor 326, Figure 3).
Xu does not specifically disclose that the capacitor is implemented as a MOSFET.
Feil discloses a semiconductor device (Figures 1-17) comprising a first transistor device (comprising 1, Figures 1-4, 6-8) comprising a first drive node, a second drive node, and a load path (comprising gate G1, source S1 and a load path between D1, S1); and
a protection circuit (comprising 2, 3, Figures 1-4, 6, 12A-17) coupled to the first and second drive nodes and the load path of the first transistor device (2, 3 coupled between D1, S1), wherein the protection circuit comprises:
a second transistor device (2, Figures 1-4, 6, 12A-17) comprising a first drive node, a second drive node, and a load path (2 having a first drive node/G2, second drive node/S2 and a load path D2-S2); and a threshold detection circuit (3, Figures 1-4, 6) comprising
a capacitor (31, Figures 1-4, 6, 12A-17) coupled between the load path of the first transistor device and the first drive node of the second transistor device (31 coupled between D1, G2, Figures 1-4, 12, 14A-14B,16-17) and resistor (32, Figures 1-4, 6, 12A-17) coupled between the first and second drive nodes of the second transistor (32 coupled between G2 and S2 nodes of 2, Figures 1-4, 12, 14A-14B,16-17), wherein the resistor comprises a plurality of resistive conductors arranged in respective trenches in a semiconductor body and electrically insulated from the semiconductor body by an insulating layer (comprising 341, Figures 12A-12B, Paragraph 65, “….the resistor 32 includes several conductors arranged in several trenches and connected in parallel….”),
wherein the capacitor is implemented as a MOSFET, a gate electrode of the MOSFET is connected to an electrode arranged in a trench of the semiconductor body and insulated from the semiconductor body by an insulator, forms a second capacitor electrode that is connected to the first drive node of the second transistor device, and a common drain electrode coupled to drift regions of the semiconductor body arranged between the common drain electrode and an insulator forms a first capacitor electrode that is connected to the load path node of the first transistor device (31 formed as trench capacitors having capacitor electrodes 311, 43, Figures 12A-12B, 13-16, Paragraph 51, “….capacitor electrode 311 arranged in a trench of the semiconductor body 100…a second electrode of the capacitor cell is formed by the common drain electrode 43 and those regions 314, 315 of the semiconductor body 100 arranged between the common drain electrode 43 and the capacitor dielectric 312 …”, Paragraph 61, it is noted that a capacitor implemented as a MOSFET is the MOSFET connected as two terminal device, the MOSFET gate as one electrode and MOSFET drain, source or drain, source/body together forming a second electrode, with an insulator between the two electrodes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to select the capacitor in the electronic circuit of Xu, as the capacitor taught by Feil, such that capacitor and resistor (biasing elements in the protection circuit) can be implemented on same substrate using same technology as transistors, and to select the type of the semiconductor/MOSFET and terminal configurations to obtain the desired capacitance or Capacitance – voltage (CV) characteristics.
Regarding Claim 17, combination of Xu and Feil discloses the electronic circuit of Claim 16, wherein the capacitor comprises a first contact electrode which forms the second capacitor node of the capacitor (Feil, comprising first contact electrode 311, Figures 12A-12B), and a second contact electrode which forms the first capacitor node of the capacitor (Feil, comprising 43, Figures 12A-12B), wherein the first contact electrode is formed above a first surface of a semiconductor body (Feil, body 100, Figure 6, Paragraph 51) and is separated from the semiconductor body by a first insulating layer (Feil, comprising 312, Figures 12A-12B), wherein the second contact electrode is formed below a second surface of the semiconductor body opposite the first surface (Feil, comprising 43, Figures 12A-12B).
Regarding Claim 18, combination of Xu and Feil discloses the electronic circuit of Claim 16, wherein the capacitor comprises a first doped region corresponding to a drift region of the first transistor device (314, Figures 12A, 14A, 14B, Paragraph 61), second doped regions corresponding to body regions of the first transistor device (315 Figures 12A, 14A, 14B, Paragraph 61), third doped regions corresponding to source regions of the first transistor device (doped region around 316, Figures 12A, 14A, 14B, Paragraph 61), and a fourth doped region corresponding to a drain region of the first transistor device (43, Figure 12A Paragraph 61).
Regarding Claim 19, Xu discloses an electronic circuit (Figures 1-8), comprising:
a first transistor device (102, Figure 1, 318, Figure 3, corresponding element/s in other Figures) comprising a first drive node, a second drive node, and a load path (comprising gate, source and a load path between 104 and 106, Figure 1, 318 having a gate, source, and a load path between320 and 334, Figure 3); and
a protection circuit (comprising 110 and its biasing circuit, Figure 1, comprising 326 and its biasing circuit, Figure 3) coupled to the first and second drive nodes and the load path of the first transistor device (comprising 110 and its biasing circuit coupled to 112/gate and 116/source and to load path between 104, 106, Figure 1, 326 and its biasing circuit coupled to 322/gate and 334/source and to load path between 320, 334, Figure 3), wherein the protection circuit comprises:
a second transistor device (110, Figure 1, 326, Figure 3) comprising a first drive node, a second drive node, and a load path connected between the first and second drive nodes of the first transistor device (110 having a first drive node/gate, second drive node/source and a load path between 112, 116 , Figure 1, 326 having a first drive node/gate, second drive node/source and a load path between 322,/330 and 332/334, Figure 3); and
a capacitor (118, Figure 1, 336, Figure 3) coupled between the load path of the first transistor device and the first drive node of the second transistor device (118 coupled between 104 and 114, Figure 1, 336 coupled between 320 and 328, Figure 3), and
a resistor (120, Figure 1, 338, Figure 3) connected between the first and second drive nodes of the second transistor device (120 coupled between 114, 116, Figure 1, 326 coupled between the first dive nide 328 and the second drive node 332 of 326, Figure 3).
Xu does not specifically disclose the resistor comprises a plurality of resistive conductors arranged in respective trenches in a semiconductor body and electrically insulated from the semiconductor body by an insulating layer.
Feil discloses a semiconductor device (Figures 1-17) comprising a first transistor device (comprising 1, Figures 1-4, 6-8) comprising a first drive node, a second drive node, and a load path (comprising gate G1, source S1 and a load path between D1, S1); and
a protection circuit (comprising 2, 3, Figures 1-4, 6, 12A-17) coupled to the first and second drive nodes and the load path of the first transistor device (2, 3 coupled between D1, S1), wherein the protection circuit comprises:
a second transistor device (2, Figures 1-4, 6, 12A-17) comprising a first drive node, a second drive node, and a load path (2 having a first drive node/G2, second drive node/S2 and a load path D2-S2); and a threshold detection circuit (3, Figures 1-4, 6) comprising
a capacitor (31, Figures 1-4, 6, 12A-17) coupled between the load path of the first transistor device and the first drive node of the second transistor device (31 coupled between D1, G2, Figures 1-4, 12, 14A-14B,16-17) and resistor (32, Figures 1-4, 6, 12A-17) coupled between the first and second drive nodes of the second transistor (32 coupled between G2 and S2 nodes of 2, Figures 1-4, 12, 14A-14B,16-17),
wherein the capacitor is implemented as a MOS capacitor, a gate node of the MOS capacitor is connected to an electrode arranged in a trench of the semiconductor body and insulated from the semiconductor body by an insulator, forms a second capacitor electrode that is connected to the first drive node of the second transistor device, and a drain node of the MOS capacitor forms a first capacitor electrode that is connected to the load path node of the first transistor device (31 formed as trench capacitors having capacitor electrodes 311, 43, Figures 12A-12B, 13-16, Paragraph 51, “….capacitor electrode 311 arranged in a trench of the semiconductor body 100…a second electrode of the capacitor cell is formed by the common drain electrode 43 and those regions 314, 315 of the semiconductor body 100 arranged between the common drain electrode 43 and the capacitor dielectric 312 …”, Paragraph 61)
wherein the resistor comprises a plurality of resistive conductors arranged in respective trenches in a semiconductor body and electrically insulated from the semiconductor body by an insulating layer (comprising 341, Figures 12A-12B, Paragraph 65, “….the resistor 32 includes several conductors arranged in several trenches and connected in parallel….”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the resistor in the electronic circuit of Xu comprising resistive conductors arranged in trenches as taught by Feil, such that resistor and capacitor can be implemented on same substrate using same technology as transistors and to have the advantage of a resistor with adjustable resistance (see, Feil, Paragraph 65, “….The resistance of the first resistor 32 can be adjusted by the number of conductors 321 connected in parallel, the material of the at least one conductor 321, but also a length of the at least one conductor 321, that is, a distance between the first metallization 61 and the gate runner 44”).
Response to Arguments
Applicant's arguments filed on 7/07/2026 have been fully considered and are rendered moot in view of the current rejection updated to address arguments toward motivation.
Applicant’s arguments, on Pages 1-2 of the pre-appeal toward the rejection of Claim 1 and the motivation to combine Xu and Feil are rendered moot in view of the updated motivation.
Regarding Applicant’s arguments on Pages 1-2 of the Pre-appeal Brief toward the limitation of, “such that the capacitance decreases as a voltage across the capacitor increases”, examiner respectfully notes that the limitations is specifies the CV characteristic of a capacitor, and by selecting the type of semiconductor substrate and doped regions the desired capacitor CV characteristics - such that the capacitance decreases as a voltage across the capacitor increases can be achieved (note that Feil disclose n-type transistors in Figures, and discloses in Paragraph 41 p-type transistors, capacitance of a PMOS capacitor decreases as a voltage across the capacitor increases).
The Applicant argues, on Page 2 of the Pre-appeal Brief that even if Feil's first capacitor 31 has a voltage-dependent capacitance, it is part of a voltage clamping circuit and that Xu's capacitor 118/336 is part of a pull-down circuit, and these two circuits function in different ways, to achieve different purposes (voltage spike prevention versus improved voltage converter efficiency).
In response, examiner respectfully notes that Feil’s second transistor 2 and its biasing circuit 3 comprising 31 and resistor 32 (see Figure 3) similarly structured as that of Xu’s protection circuit comprising second transistor 110, 326 in Figures 1, 3 and its biasing circuit to protect the first transistor 2 from damaging voltage during switching off as described in Paragraph 34, and the biasing circuit of both Xu and Feil control the turn on and off of the second transistor.
The Applicant argues, on Pages 2-5 of the Pre-appeal Brief, toward the rejection of Claims 16-18 that the Feil reference teaches that first capacitor 31 may be implemented as a MOS capacitor, not as a MOSET with the gate node of the MOSFET connected to the source node of the MOSFET, the drain node of the MOSFET forming a first capacitor node, and the source node of the MOSFET forming a second capacitor node and that a MOS capacitor and a capacitor implemented as a MOSFET are not the same thing.
In response, examiner respectfully notes a capacitor implemented as a MOSFET is the MOSFET connected as two terminal device, the MOSFET gate as one capacitor electrode and MOSFET drain, source coupled together, or drain, source, body coupled together forming a second capacitor electrode, with an insulator between the two electrodes (see Senthikumar et al. (US 2003/0132809), 202, Figures 2, 402, Figure 4, Paragraph 21, “…Capacitors C0 to C4 are enhancement mode P-type MOSFETs (PMOS) with the drain nodes connected to the source nodes. The gate of the MOSFET functions as one terminal of the capacitor, and the drain/source node functions as the other terminal”, also see, Kerber et al. (US 2013/0069131), Figures 1-4, Paragraph 18, “….at least one of the decoupling capacitors 20 is a metal-oxide-semiconductor field-effect transistor 24 (MOSFET)”, Kumar (US 2015/0270393)).
Feil discloses in Figures 12A-12B, 13-16, Paragraph 51, a gate electrode of the MOSFET connected to an electrode arranged in a trench of the semiconductor body and insulated from the semiconductor body by an insulator, forming a second capacitor electrode that is connected to the first drive node of the second transistor device, and a common drain electrode coupled to drift regions of the semiconductor body arranged between the common drain electrode and an insulator forming a first capacitor electrode that is connected to the load path node of the first transistor device. Please note that in Feil, a capacitor electrode is formed by the common drain electrode (same drain electrode of MOSFET transistor) and drift regions of the semiconductor body (same drift region forming the drift regions of the transistors).
Examiner further respectfully notes that the argued upon claimed limitation of the MOSFET node connections, “MOSFET with a gate node of the MOSFET connected to source node of the MOSFET, the drain electrode of the MOSFET forming a first capacitor electrode, and the source node of the MOSFET that connected to the gate node of the MOSFET forming a second capacitor electrode”, is a diode implemented using a MOSFET, the diode having a diode capacitance.
Regarding Applicant’s arguments, on Pages 15-16 of the Remarks toward Claim 19 and the combination of Xu and Feil reference are similar to those presented toward Claim 1 limitations, please see the response to arguments toward Claim 1 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Voldman (US 5,789,964) discloses an electronic circuit in Figure 5 comprising transistor 52 and a gate control circuit comprising a capacitor 54 and a resistor 53, wherein the capacitor is implemented as a MOS capacitor/NFET and the resistor is implemented as a MOS resistor/PFET.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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/LUCY M THOMAS/Examiner, Art Unit 2838, 8/20/2026
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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