Prosecution Insights
Last updated: April 19, 2026
Application No. 18/410,536

SYSTEMS AND METHODS FOR SIGNAL SAMPLING USING A SAMPLING ARRAY

Non-Final OA §102§103
Filed
Jan 11, 2024
Examiner
HE, AMY
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Alphacore, Inc.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
85%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
425 granted / 523 resolved
+13.3% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
20 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
44.6%
+4.6% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 523 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 5, 7-9, 11-12, 15 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (U. S. Pub. 2015/0263756). As for claim 1, Chiu et al. discloses a system (see Fig. 2 and [0034]—[0041]) comprising: a capacitive sampling array (see the capacitive sampling array of 22) having an input interface (see 21a, 21b inputted to 22; and Vr and Vgnd), an output interface (see the output of 22 connected to the comparator 24), and capacitive sampling channels (see the plurality of capacitive sampling channels in 22)connected in parallel between the input interface and the output interface, wherein each capacitive sampling channel has a channel-specific capacitor (see the plurality of capacitors 220a—220h)having a channel-specific capacitance (e.g., see 4C for 220a; 2C for 220b and 1C for 220c in Fig. 2); a readout system (combination of comparator 24 and SAR 26) coupled to the output interface of the capacitive sampling array and configured to generate digital data (digital output from SAR 26) in response to a signal (Vip, Vin) received on the input interface of the capacitive sampling array; and a controller (control circuit 28) coupled to the readout system (24 and 26) to receive the digital data and configured to select capacitive sampling channels (by using the plurality of switches shown in Fig. 2) of the capacitive sampling array to sample the signal in response to the digital data (see the feedback connection from control circuit 28 to the capacitive sampling array of 22 in Fig. 2). As for claim 11, Chiu et al. discloses a method (see Fig. 2 and [0034]—[0041]) comprising: obtaining a sample of a signal from a capacitive sampling array (sampling the input signals vin, vip using the capacitive sampling array of 22) having an input interface (see 21a, 21b inputted to 22; and Vr and Vgnd), an output interface (see the output from 22 connected to the comparator 24), and capacitive sampling channels(see the plurality of capacitive sampling channels in 22) connected in parallel between the input interface and the output interface, wherein each capacitive sampling channel has a channel-specific capacitor(see the plurality of capacitors 220a—220h)having a channel-specific capacitance (e.g., see 4C for 220a; 2C for 220b and 1C for 220c in Fig. 2); selecting (using the plurality of switches 20a, 20b, 222a—222g) a capacitive sampling channel from the capacitive sampling array for a subsequent sampling instance in response to the sample; and controlling (using the control circuit 28) the capacitive sampling array to sample the signal in the subsequent sampling instance using the selected capacitive sampling channel. As for claims 2 and 12, Chiu et al. discloses the system/method of claims 1 and 11, wherein the controller (the control circuit 28) is configured to change a pattern of sampling instances in a frame of sampling instances in response to a magnitude of the signal received on the input interface (Vip, Vin, Vr, Vgnd), wherein a sampling instance includes a selected capacitive sampling channel (see the plurality of capacitive sampling channels in 22 selected by the switching circuit). As for claims 5 and 15, Chiu et al. discloses the system/method of claims 1 and 11, wherein the controller (the control circuit 28) is configured to select (using switches shown in 22) a capacitive sampling channel from the capacitive sampling channel array for a subsequent sampling instance in response to a magnitude of the signal received on the input interface (i.e., based on received signal Vip, vin, or Vr). As for claim 7, Chiu et al. discloses the system of claim 1, wherein the channel-specific capacitors (220a—220h) of each capacitance sampling channel is a function of a unit capacitor (unit capacitor C; see [0035], lines 7-9). As for claim 8, Chiu et al. discloses the system of claim 7, wherein a first capacitive sampling channel in the capacitive sampling array has more unit capacitors (i.e., 4C) than a second capacitive sampling channel array (i.e., 2C or 1C) such that the first capacitive sampling channel has a larger capacitance than the second capacitive sampling channel (see 4C and 2C, 1C in Fig. 2). As for claim 9, Chiu et al. discloses the system of claim 1, wherein the capacitive sampling channels of the capacitive sampling array include channel-specific switches (switches 222a—222g) that enable the capacitive sampling channels to be individually activated for sampling the input Signal (see Fig. 2). As for claim 17, Chiu et al. discloses a method (see Fig. 2 and [0034]—[0041]) for operating a system that samples an input signal (Vip; Vin), the method comprising: selecting (using switch 222a) capacitive sampling channels with large channel-specific capacitance (i.e., 4C) from a capacitive sampling array (see the plurality of capacitive sampling array shown in Fig. 2) to sample portions of a signal (Vip, Vin) that have low magnitude; and selecting (using switch 222b) capacitive sampling channels with small channel-specific capacitance (2C) from the capacitive sampling array to sample portions of the signal (Vip; Vin) that have high magnitude; wherein the capacitive sampling array includes an input interface (see 21a, 21b inputted to 22; and Vr and Vgnd) to receive the signal, an output interface (see the output from 22 connected to the comparator 24), and capacitive sampling channels (see the plurality of capacitive sampling channels in 22)connected in parallel between the input interface and the output interface, wherein each capacitive sampling channel has a channel-specific capacitor(see the plurality of capacitors 220a—220h)having a channel-specific capacitance(e.g., see 4C for 220a; 2C for 220b and 1C for 220c in Fig. 2); and wherein the large channel-specific capacitance has larger capacitance (4C) than the small channel-specific capacitance (2C; 1C), and the portions of the signal (Vip, Vin) that have low magnitude have lower magnitude than the portions of the signal that have high magnitude. As for claim 18, Chiu et al. discloses the method of claim 17, wherein the capacitive sampling channels are selecting (using the control circuit 28 and switches in 22) in response to digital data (digital data outputted from SAR 26) generated in response to samples of the signal generated by the capacitive sampling array. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (U. S. Pub. 2015/0263756). As for claim 10, Chiu et al. discloses the system of claim 1 as discussed above. Chiu et al. does not specifically disclose wherein the controller is further configured to: increase a sampling rate of the system in response to a portion of the signal that has a higher magnitude; and decrease the sampling rate of the system in response to a portion of the signal that has a lower magnitude. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the controller in Chiu et al. to: increase/decrease a sampling rate of the system in response to a portion of the signal that has a higher/lower magnitude, since such adaptive sampling is desired to accurately capture transients, edges, or peaks of the signal and to save power and memory needed for the system. Allowable Subject Matter Claims 3-4, 6, 13, 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claims 3, 4, 13 and 14 are allowable because none of the prior art discloses or fairly suggests a system/method further comprising: change a capacitive sampling channel of a sampling instance in the frame to a capacitive sampling channel with a smaller capacitance in response to a portion of the signal that has a higher magnitude than a previous portion of the signal; and change a capacitive sampling channel of a sampling instance in the frame to a capacitive sampling channel with a larger capacitance in response to a portion of the signal that has a lower magnitude than a previous portion of the signal; or to: select a capacitive sampling channel with a smaller capacitance to correspond to a portion of the signal with a higher magnitude; and select a capacitive sampling channel with a larger capacitance to correspond to a portion of the signal with a lower magnitude, and in the combination as claimed in claims 2 and 12. Claims 6 and 16 are allowable because none of the prior art discloses or fairly suggests a system/method, further comprising: select a capacitive sampling channel for a subsequent sampling instance that has a larger capacitance than a previous sampling instance in response to digital data that indicates a rising edge of the signal; and select a capacitive sampling channel for a subsequent sampling instance that has a smaller capacitance than a previous sampling instance in response to digital data that indicates a falling edge of the signal, and in the combination as claimed in claims 5 and 15. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY HE whose telephone number is (571)272-2230. The examiner can normally be reached 9:00am--5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMY HE/ Primary Examiner, Art Unit 2858
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Prosecution Timeline

Jan 11, 2024
Application Filed
Jan 08, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
85%
With Interview (+4.1%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 523 resolved cases by this examiner. Grant probability derived from career allow rate.

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