DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting (Non-Statutory)
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Double patenting between App. 18/410,539 and App. 18/410,552
Claims 1-4, 6, 8, 10-13, 15, and 18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5-7, 9, 11, 13, 14, 16, and 17 of copending Application No. 18/410,552. Although the claims at issue are not identical, they are not patentably distinct from each other because they are broader in scope than the co-pending application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 5, 7, 9, 14 and 16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 7, 10, and 14 of copending Application No. 18/410,552 in view of Sharma (US 2024/0094907 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Application 18/410,552 to use the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 17 and 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of copending Application No. 18/410,552 in view of Liu (US 2020/0293661 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Application 18/410,552 to use the complex logic device firmware restoration features of Liu to allow for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for greater flexibility for more secure and efficient storing and processing of data.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 19 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of copending Application No. 18/410,552 in view of Sharda (US 9,190,989 B1). Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Application 18/410,552 to use the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Application 18/410,539
Application 18/410,552
Claim 1
Claim 1
Claim 2
Claim 2
Claim 3
Claim 5
Claim 4
Claim 6
Claim 5
Claim 5 + Sharma
Claim 6
Claim 6
Claim 7
Claim 1 + Sharma
Claim 8
Claim 7
Claim 9
Claim 7+ Sharma
Claim 10
Claim 9
Claim 11
Claim 13
Claim 12
Claim 13
Claim 13
Claim 11
Claim 14
Claim 10 + Sharma
Claim 15
Claim 14
Claim 16
Claim 14 + Sharma
Claim 17
Claim 16 + Liu
Claim 18
Claim 17
Claim 19
Claim 16 + Sharda
Claim 20
Claim 16 + Liu
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sharda (US 9,190,989 B1, hereinafter referenced “Sharda”) in view of Liu (US 2020/0293661 A1, hereinafter referenced “Liu”).
In regards to claim 1. Sharda discloses a system on a chip (SoC) (Sharda, Fig.1) comprising:
-SoC memory (Sharda, Fig. 1; Reference illustrates Random Access Memory 110);
-one or more processor subsystems, wherein each processor subsystem includes a processor connected to the SoC memory (Sharda, Fig.1 and Column 3, lines 20-24; Reference discloses a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103);
-and a low power subsystem integrated as a separate subsystem in the SoC, wherein the low power subsystem includes a microcontroller and a power management unit (PMU) (Sharda, Fig. 1 and Column 3, lines 20-24 and 46-51; Reference at lines 20-24 discloses a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103 (i.e. the different domains have been interpreted as integrated separate subsystems in the SoC. Lines 46-51 disclose the main domain 101 also includes a central controller 115 (i.e. microcontroller) which controls an operating mode of the SOC and a central clock generator 116. The SMS domain 102 also includes low power mode controller 117 (i.e. power management unit) which controls the SMS domain in a reduced computing mode of operation and in a full power, asynchronous subsystem mode of operation…The low power mode controller 117 is operably coupled to the central controller 115),
-wherein the PMU is connected to each processor subsystem, the PMU operating under the control of the microcontroller to control the power to each processor subsystem (Sharda, Figs. 1 and 3 Column 4, lines 58-67 and Column 5, lines 1-3; References disclose a method of power management of an integrated circuit (such as the SOC described with reference to FIG. 1) by switching between full power and reduced power modes of operation will now be described with reference to the flow chart of FIG. 3 and to FIG. 1. In a full power mode of operation, both the main domain 101 and low power (SMS) domain 102 are powered up and active (i.e., alive). In a low power, reduced computing mode of operation, the main domain is inactive (i.e., power-gated) and the low power, (SMS) domain is active. Switching between full power and low power modes of operation is initiated by writing into a register in either the central controller or the low power mode controller. Fig. 1 illustrates the connection of the low power mode controller 117 to the microcontroller as the switching between full and reduced power states interpreted as the PMU operating under the control of the microcontroller to control the power to each processor subsystem).
Sharda does not explicitly disclose but Liu teaches
-wherein the microcontroller executes a real-time operating system (RTOS) (Liu, para [0036]; Reference discloses turning now to FIG. 2, an example of a boot management controller is illustrated, according to one or more embodiments. As shown, BMC 185 may include a processor 220, a volatile memory medium 250, a non-volatile memory medium 270, and an interface 280. As illustrated, non-volatile memory medium 270 may include a BMC firmware (FW) 273, which may include an OS 262 and APPs 264-268, and may include BMC data 277. In one example, OS 262 may be or include a real-time operating system (RTOS) (i.e. microcontroller executing RTOS)),
Sharda and Liu are combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda to include the complex logic device firmware restoration features of Liu in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Sharda.
In regards to claim 2. Sharda in view of Liu teach the SoC of claim 1.
Sharda further discloses
-wherein the SoC memory includes Static Random-Access Memory (SRAM) (Sharda, Column 4, lines 20-32; Reference discloses in FIG. 2, a first power domain 201 and a second power domain 202 of an SOC are both connected to isolation circuitry 203…The power-gated domain 202 includes an SRAM 210, central clock controller 211 and flash memory 212 and a core 213).
In regards to claim 6. Sharda in view of Liu teach the SoC of claim 1.
Sharda does not explicitly disclose but Liu teaches
-wherein the SoC memory includes Dynamic Random-Access Memory (DRAM) (Liu, para [0024]; Reference discloses volatile memory medium 150 may include volatile storage such as, for example, RAM, DRAM (dynamic RAM), EDO RAM (extended data out RAM), SRAM (static RAM), etc.).
Sharda and Liu are combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda to include the complex logic device firmware restoration features of Liu in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Sharda.
Claim 3 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sharda (US 9,190,989 B1) in view of Liu (US 2020/0293661 A1) as applied to claim 1 above, and further in view of Lo (US 2021/0173648 A1, hereinafter referenced “Lo”).
In regards to claim 3. Sharda in view of Liu teach the SoC of claim 2.
Sharda and Liu does not explicitly disclose but Lo teaches
-wherein the SRAM is distributed to each processor subsystem as local memory, wherein the local memory for each processor subsystem is addressable as shared memory (Lo, para [0051]; Reference at [0051] discloses in summary, the embodiment of the processor of this disclosure uses an arbitration unit 4 so that the processor core 2 and the neural network accelerator 3 can share the scratchpad memory 1, and further uses a generic I/O interface (e.g., MMIO, PMIO, etc.) to communicate with the neural network accelerator 3, so as to reduce the cost for developing specialized toolchains and hardware (i.e. distribution of memory among processors as preceding para [0028] discloses the scratchpad memory as an SRAM)) .
Sharda and Liu are combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda to include the complex logic device firmware restoration features of Liu in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Sharda.
Sharda and Lo are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda, in view of the complex logic device firmware restoration features of Liu, to include the neural network processor features of Lo in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Further incorporating the neural network processor features of Lo allows for use of a processor architecture adapted for a neural network including a scratchpad memory, a processor core, and an arbitration unit for sharing of scratchpad memory to avoid the disadvantages of peripheral engine IC design where the system utilizes private SRAM instead of sharing the available SRAM of the embedded processor cores, applicable to improving processing systems such as those taught in Sharda and Liu.
Claims 4 and 5 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sharda (US 9,190,989 B1) in view of Liu (US 2020/0293661 A1) in view of Lo (US 2021/0173648 A1) as applied to claim 3 above, and further in view of Sharma (US 2024/0094907 A1, hereinafter referenced “Sharma”).
In regards to claim 4. Sharda in view of Liu teach the SoC of claim 3.
Sharda, Liu, and Lo does not explicitly disclose but Sharma teaches
-wherein each local memory is allocated as a virtualized static memory (VSMEM), with a portion of the local memory serving as a physical address space for the VSMEM and a portion of off-die memory serving as storage for compressed data blocks that were replaced in the physical address space of VSMEM (Sharma, para [0113]; Reference discloses in some example approaches, SMEM 565 is virtualized as VSMEM, and the activation data is compressed. SMEM redirection is therefore used to direct writes of activation data initially directed to SMEM 565 to compression block 704 for compression. The compressed data is then forwarded to either SMEM 565 of local memory of the appropriate subsystem or to off-die memory 566 via DDR CTRL 712. As shown in FIG. 7 , data to be written to memory 566 may be stored temporarily in a system cache (one of SYSCACHEs 0:3) before being transmitted via downstream NoC 714 to the appropriate section of memory 566).
Sharda and Liu are combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda to include the complex logic device firmware restoration features of Liu in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Sharda.
Sharda and Lo are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda, in view of the complex logic device firmware restoration features of Liu, to include the neural network processor features of Lo in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Further incorporating the neural network processor features of Lo allows for use of a processor architecture adapted for a neural network including a scratchpad memory, a processor core, and an arbitration unit for sharing of scratchpad memory to avoid the disadvantages of peripheral engine IC design where the system utilizes private SRAM instead of sharing the available SRAM of the embedded processor cores, applicable to improving processing systems such as those taught in Sharda and Liu.
Sharda and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda, in view of the complex logic device firmware restoration features of Liu in further view of the neural network processor features of Lo, to include the systems on chip lossless compression features of Sharma in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Further incorporating the neural network processor features of Lo allows for use of a processor architecture adapted for a neural network including a scratchpad memory, a processor core, and an arbitration unit for sharing of scratchpad memory to avoid the disadvantages of peripheral engine IC design where the system utilizes private SRAM instead of sharing the available SRAM of the embedded processor cores. Adding the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Sharda, Liu, and Lo.
In regards to claim 5. Sharda in view of Liu teach the SoC of claim 3.
Sharda, Liu, and Lo does not explicitly disclose but Sharma teaches
-wherein each local memory is allocated as a virtualized static memory (VSMEM), with a portion of the local memory serving as a physical address space for the VSMEM and a portion of off-die memory serving as storage for compressed data blocks that are aged out of the physical address space (Sharma, para [0113]; Reference discloses in some example approaches, SMEM 565 is virtualized as VSMEM, and the activation data is compressed. SMEM redirection is therefore used to direct writes of activation data initially directed to SMEM 565 to compression block 704 for compression. The compressed data is then forwarded to either SMEM 565 of local memory of the appropriate subsystem or to off-die memory 566 via DDR CTRL 712. As shown in FIG. 7 , data to be written to memory 566 may be stored temporarily in a system cache (one of SYSCACHEs 0:3) before being transmitted via downstream NoC 714 to the appropriate section of memory 566).
Sharda and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda, in view of the complex logic device firmware restoration features of Liu in further view of the neural network processor features of Lo, to include the systems on chip lossless compression features of Sharma in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Further incorporating the neural network processor features of Lo allows for use of a processor architecture adapted for a neural network including a scratchpad memory, a processor core, and an arbitration unit for sharing of scratchpad memory to avoid the disadvantages of peripheral engine IC design where the system utilizes private SRAM instead of sharing the available SRAM of the embedded processor cores. Adding the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Sharda, Liu, and Lo.
Claims 7-9 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sharda (US 9,190,989 B1) in view of Liu (US 2020/0293661 A1) as applied to claim 1 above, and further in view of Sharma (US 2024/0094907 A1).
In regards to claim 7. Sharda in view of Liu teach the SoC of claim 6.
Sharda and Liu does not explicitly disclose but Sharma teaches
-wherein the SoC memory further includes Static Random-Access Memory (SRAM), the SRAM distributed to each processor subsystem as local memory (LMEM), wherein pages of virtual memory stored in LMEM are stored to and retrieved from the DRAM (Sharma, para [0042] and [0048]; Reference at [0042] discloses each subsystem includes compute elements 152 (processors or coprocessors) and corresponding local memory 154 (e.g., SRAM) collocated with the compute elements 152. In some such SoCs, portions of on-die SRAM are physically distributed throughout the SoC as Local Memory (LMEM) 154, with a different instance of LMEM 154 located close to each compute element 152. Para [0048] discloses VSMEM 155 may be allocated as virtual memory, with a physical portion of the memory allocated as SMEM in LMEM 15 and with data swapped out to an external volatile memory such as DRAM 160 as needed (i.e. storing and retrieved from DRAM)).
In regards to claim 8. Sharda in view of Liu teach the SoC of claim 1.
Sharda and Liu does not explicitly disclose but Sharma teaches
-wherein the processors execute a multi-tasking operating system (MTOS) (Sharma, para [0059]; Reference discloses In this example, HMD 112 includes one or more processors 302 and memory 304 that, in some examples, provide a computer platform for executing an operating system 305, which may be an embedded, real-time multitasking operating system, for instance, or other type of operating system).
Sharda and Liu are combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda to include the complex logic device firmware restoration features of Liu in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data applicable to the processing systems as taught in Sharda.
Sharda and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda, in view of the complex logic device firmware restoration features of Liu, to include the systems on chip lossless compression features of Sharma in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Further the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Sharda and Liu.
In regards to claim 9. Sharda in view of Liu teach the SoC of claim 1.
Sharda and Liu does not explicitly disclose but Sharma teaches
-wherein the processors execute an augmented reality operating system (MTOS) (Sharma, para [0005] and [0059]; Reference at [0005] discloses examples of artificial reality systems may incorporate a head-mounted display (HMD) worn by a user and configured to output artificial reality content to the user. Para [0059] discloses in this example, HMD 112 includes one or more processors 302 and memory 304 that, in some examples, provide a computer platform for executing an operating system 305, which may be an embedded, real-time multitasking operating system, for instance, or other type of operating system).
Sharda and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit power management system of Sharda, in view of the complex logic device firmware restoration features of Liu, to include the systems on chip lossless compression features of Sharma in order to provide the user with a system that allows for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off as taught by Sharda while incorporating the complex logic device firmware restoration features of Liu to allow for processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Further the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Sharda and Liu.
Claims 10, 13, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2017/0011555 A1, hereinafter referenced “Li”) in view of Sharda (US 9,190,989 B1) in further view of Liu (US 2020/0293661 A1).
In regards to claim 10. Li discloses an artificial reality system (Li, Abstract) comprising:
-a display screen for a head-mounted display (HMD) (Li, para [0073] discloses the HMD 100 includes the image display section 20 that displays an image, and a control section 10 (controller 10) that controls the image display section 20. The image display section 20 is a mounting body mounted in a head portion of the user, and has a shape of glasses. The image display section 20 includes a right holder 21, a right display driver 22, a left holder 23, a left display driver 24, a right optical image display section 26, a left optical image display section 28, and a camera 61);
-and at least one system on a chip (SoC) connected to the HMD display screen and configured to output artificial reality content on the HMD display screen (Li, para [0073] and [0089]; Reference at [0073] discloses the HMD 100 includes the image display section 20 that displays an image, and a control section 10 (controller 10) (i.e. system on chip) that controls the image display section 20 (i.e. connected to HMD display screen). The image display section 20 is a mounting body mounted in a head portion of the user, and has a shape of glasses. The image display section 20 includes a right holder 21, a right display driver 22, a left holder 23, a left display driver 24, a right optical image display section 26, a left optical image display section 28, and a camera 61. Para [0089] discloses as a result, the user can view an augmented reality (AR) image so that at least one of its position, size, and pose is aligned with the object through the image display section 20 (i.e. outputting artificial reality content)), wherein the at least one SoC comprises:
Li does not explicitly disclose but Sharda teaches
-SoC memory (Sharda, Fig. 1; Reference illustrates Random Access Memory 110);;
-one or more processor subsystems, wherein each processor subsystem includes a processor connected to the SoC memory (Sharda, Fig.1 and Column 3, lines 20-24; Reference discloses a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103);
-and a low power subsystem integrated as a separate subsystem in the SoC, wherein the low power subsystem includes a microcontroller and a power management unit (PMU) (Sharda, Fig. 1 and Column 3, lines 20-24 and 46-51; Reference at lines 20-24 discloses a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SoC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103 (i.e. the different domains have been interpreted as integrated separate subsystems in the SoC. Lines 46-51 disclose the main domain 101 also includes a central controller 115 (i.e. microcontroller) which controls an operating mode of the SOC and a central clock generator 116. The SMS domain 102 also includes low power mode controller 117 (i.e. power management unit) which controls the SMS domain in a reduced computing mode of operation and in a full power, asynchronous subsystem mode of operation…The low power mode controller 117 is operably coupled to the central controller 115),
-wherein the PMU is connected to each processor subsystem, the PMU operating under the control of the microcontroller to control the power to each processor subsystem (Sharda, Figs. 1 and 3 Column 4, lines 58-67 and Column 5, lines 1-3; References disclose a method of power management of an integrated circuit (such as the SOC described with reference to FIG. 1) by switching between full power and reduced power modes of operation will now be described with reference to the flow chart of FIG. 3 and to FIG. 1. In a full power mode of operation, both the main domain 101 and low power (SMS) domain 102 are powered up and active (i.e., alive). In a low power, reduced computing mode of operation, the main domain is inactive (i.e., power-gated) and the low power, (SMS) domain is active. Switching between full power and low power modes of operation is initiated by writing into a register in either the central controller or the low power mode controller. Fig. 1 illustrates the connection of the low power mode controller 117 to the microcontroller as the switching between full and reduced power states interpreted as the PMU operating under the control of the microcontroller to control the power to each processor subsystem).
Li and Sharda does not explicitly disclose but Liu teaches
-wherein the microcontroller executes a real-time operating system (RTOS) (Liu, para [0036]; Reference discloses turning now to FIG. 2, an example of a boot management controller is illustrated, according to one or more embodiments. As shown, BMC 185 may include a processor 220, a volatile memory medium 250, a non-volatile memory medium 270, and an interface 280. As illustrated, non-volatile memory medium 270 may include a BMC firmware (FW) 273, which may include an OS 262 and APPs 264-268, and may include BMC data 277. In one example, OS 262 may be or include a real-time operating system (RTOS) (i.e. microcontroller executing RTOS)),
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
In regards to claim 13. Li in view of Sharda in further view of Liu teach the artificial reality system of claim 10.
Li does not explicitly disclose but Sharda teaches
-wherein the SoC memory includes Dynamic Random-Access Memory (DRAM) (Sharda, Column 4, lines 20-32; Reference discloses in FIG. 2, a first power domain 201 and a second power domain 202 of an SOC are both connected to isolation circuitry 203…The power-gated domain 202 includes an SRAM 210, central clock controller 211 and flash memory 212 and a core 213).
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
In regards to claim 17. Li discloses in an artificial reality system (Li, Abstract) having a display screen for a head-mounted display (HMD) (Li, para [0073] discloses the HMD 100 includes the image display section 20 that displays an image, and a control section 10 (controller 10) that controls the image display section 20. The image display section 20 is a mounting body mounted in a head portion of the user, and has a shape of glasses. The image display section 20 includes a right holder 21, a right display driver 22, a left holder 23, a left display driver 24, a right optical image display section 26, a left optical image display section 28, and a camera 61) and at least one system on a chip (SoC) connected to the HMD display screen and configured to output artificial reality content on the HMD display screen (Li, para [0073] and [0089]; Reference at [0073] discloses the HMD 100 includes the image display section 20 that displays an image, and a control section 10 (controller 10) (i.e. system on chip) that controls the image display section 20 (i.e. connected to HMD display screen). The image display section 20 is a mounting body mounted in a head portion of the user, and has a shape of glasses. The image display section 20 includes a right holder 21, a right display driver 22, a left holder 23, a left display driver 24, a right optical image display section 26, a left optical image display section 28, and a camera 61. Para [0089] discloses as a result, the user can view an augmented reality (AR) image so that at least one of its position, size, and pose is aligned with the object through the image display section 20 (i.e. outputting artificial reality content)),
Li does not explicitly disclose but Sharda teaches
-wherein the at least one SoC includes SoC memory (Sharda, Fig. 1; Reference illustrates Random Access Memory 110),
-one or more compute subsystems connected to the SoC memory (Sharda, Fig.1 and Column 3, lines 20-24; Reference discloses a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103),
-and a low power subsystem connected to the SoC memory and to the compute subsystems, the low power subsystem including a microcontroller and a power management unit (PMU),
-the low power subsystem integrated as a separate subsystem in the SoC (Sharda, Fig. 1 and Column 3, lines 20-24 and 46-51; Reference at lines 20-24 discloses a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103 (i.e. the different domains have been interpreted as integrated separate subsystems in the SoC. Lines 46-51 disclose the main domain 101 also includes a central controller 115 (i.e. microcontroller) which controls an operating mode of the SOC and a central clock generator 116. The SMS domain 102 also includes low power mode controller 117 (i.e. power management unit) which controls the SMS domain in a reduced computing mode of operation and in a full power, asynchronous subsystem mode of operation…The low power mode controller 117 is operably coupled to the central controller 115), a method comprising:
-executing one or more processes in a microcontroller of the low power subsystem, each process having a state (Sharda, Figs. 1 and 3 Column 4, lines 58-67 and Column 5, lines 1-3; References disclose a method of power management of an integrated circuit (such as the SOC described with reference to FIG. 1) by switching between full power and reduced power modes of operation will now be described with reference to the flow chart of FIG. 3 and to FIG. 1. Fig. 1 illustrates the connection of the low power mode controller 117 to the microcontroller as the switching between full and reduced power states indicates the process having different states),
-determining, in the microcontroller, whether one or more of the compute subsystems should be activated (Sharda, Column 3, lines 39-44 and Column 5, lines 51-61; Reference at column 3 discloses the third domain 103 in this example is an “always on” or “standby” domain which can be alive even when both the first and second domains 101, 102 are inactive. Typically, the third domain includes several timer modules, wake-up circuitry and corresponding state machines as required to control power and isolations. Column 5 discloses The low power domain is being powered by the low-power regulator 122, controlled by the low power mode controller 117 and receiving clocking signals from the low power generator 118. Optionally, after step 306, the main domain can then go back again to a power-gated mode (step 303) and can recursively go through power cycles while any application running in the low-power domain continues to operate seamlessly. This can be controlled through the state machine 119. As a main domain can cycle while an SMS domain is active, this helps to maintain the continuity of operation. State machine interpreted as assisting in determination of which subsystems should be activated),
-if one or more of the compute subsystems should be activated, selecting one or more of the processes executing in the microcontroller, saving the state of the selected processes to SoC memory, activating the one or more compute subsystems via the PMU, transferring the state of the selected processes to the activated compute systems, and executing instructions in the activated compute subsystems to execute the selected processes based on the transferred state (Sharda, Figs. 1 and 3 Column 3, lines 59-61 and Column 4, lines 58-67 and Column 5, lines 1-3; Reference at column 3 discloses the low power mode controller 117 includes a state machine 119 for controlling mode transitions. Columns 4 and 5 disclose a method of power management of an integrated circuit (such as the SOC described with reference to FIG. 1) by switching between full power and reduced power modes of operation will now be described with reference to the flow chart of FIG. 3 and to FIG. 1. In a full power mode of operation, both the main domain 101 and low power (SMS) domain 102 are powered up and active (i.e., alive). In a low power, reduced computing mode of operation, the main domain is inactive (i.e., power-gated) and the low power, (SMS) domain is active. Switching between full power and low power modes of operation is initiated by writing into a register in either the central controller or the low power mode controller. Fig. 1 illustrates the connection of the low power mode controller 117 to the microcontroller as the switching between full and reduced power states interpreted as saving the state of the selected processes to SoC memory, activating the one or more compute subsystems via the PMU, transferring the state of the selected processes to the activated compute systems, and executing instructions in the activated compute subsystems to execute the selected processes based on the transferred state).
Li and Sharda does not explicitly disclose but Liu teaches
-the microcontroller executing a first operating system / the compute subsystems executing a second operating system different from the first operating system (Liu, para [0036]; Reference discloses turning now to FIG. 2, an example of a boot management controller is illustrated, according to one or more embodiments. As shown, BMC 185 may include a processor 220, a volatile memory medium 250, a non-volatile memory medium 270, and an interface 280. As illustrated, non-volatile memory medium 270 may include a BMC firmware (FW) 273, which may include an OS 262 and APPs 264-268, and may include BMC data 277. In one example, OS 262 may be or include a real-time operating system (RTOS)),
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
In regards to claim 18. Li in view of Sharda in further view of Liu teach the method of claim 17.
Li does not explicitly disclose but Sharda teaches
-wherein the compute subsystem includes a CPU (Sharda, Column 3, lines 20-26; Reference discloses referring now to FIG. 1, a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103. The main domain includes a (main) core 104).
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
In regards to claim 19. Li in view of Sharda in further view of Liu teach the method of claim 17.
Li does not explicitly disclose but Sharda teaches
-wherein executing instructions in the activated compute subsystems includes selecting one or more of the activated compute subsystems for deactivation, wherein selecting includes determining active processes in the compute subsystems selected for deactivation, storing the state of the active processes in SoC memory, transferring the state of the selected processes to SoC memory, executing instructions in the microcontroller to execute the selected processes based on the transferred state, and deactivating the compute subsystems selected for deactivation via the PMU (Sharda, Fig. 3 steps 304-305 and Column 5, lines 15-30; Reference discloses at 304 the low power mode of operation is entered which is typically one of reduced computing capability whereby only the SMS 102 is active (or alive). This transition involves switching control of the low power (SMS) domain from the central controller to the low power controller mode 117 and gating the main domain so that it becomes inactive. More specifically, the main core 104 and peripherals (e.g. Flash 105 and modules 106, 107) of the main domain 101 are stopped. Generation of clocking signals is switched over to the low power clock generator 118 and IO states corresponding to the main domain are latched. An isolation layer around the stopped main domain is enabled by the isolation control circuitry 121. Power of the stopped domain is removed. The low power domain now receives power from the low power regulator 122 and clock signals from the low power clock generator 118 (i.e. instructions for using low power controller to switch from full power mode to low power mode interpreted as the processes of executing instructions in the microcontroller to execute the selected processes based on the transferred state, and deactivating the compute subsystems selected for deactivation via the PMU).
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
In regards to claim 20. Li in view of Sharda in further view of Liu teach the method of claim 17.
Li and Sharda does not explicitly disclose but Liu teaches
-wherein the first operating system is a real time operating system and wherein the second operating system is not a real time operating system (Liu, para [0036]; Reference discloses turning now to FIG. 2, an example of a boot management controller is illustrated, according to one or more embodiments. As shown, BMC 185 may include a processor 220, a volatile memory medium 250, a non-volatile memory medium 270, and an interface 280. As illustrated, non-volatile memory medium 270 may include a BMC firmware (FW) 273, which may include an OS 262 and APPs 264-268, and may include BMC data 277. In one example, OS 262 may be or include a real-time operating system (RTOS). In a second example, OS 262 may be or include an Unix-like operating system (i.e. not real time OS)).
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
Claims 11 and 12 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Li (US 2017/0011555 A1) in view of Sharda (US 9,190,989 B1) in further view of Liu (US 2020/0293661 A1) as applied to claim 10 above, and further in view of Lo (US 2021/0173648 A1).
In regards to claim 11. Li in view of Sharda in further view of Liu teach the artificial reality system of claim 10.
Li, Sharda, and Liu does not explicitly disclose but Lo teaches
-wherein the SoC memory includes Static Random-Access Memory (SRAM), the SRAM distributed to each processor subsystem as local memory (Lo, para [0051]; Reference at [0051] discloses in summary, the embodiment of the processor of this disclosure uses an arbitration unit 4 so that the processor core 2 and the neural network accelerator 3 can share the scratchpad memory 1, and further uses a generic I/O interface (e.g., MMIO, PMIO, etc.) to communicate with the neural network accelerator 3, so as to reduce the cost for developing specialized toolchains and hardware (i.e. distribution of memory among processors as preceding para [0028] discloses the scratchpad memory as an SRAM)).
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
Li and Lo are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda in further view of the complex logic device firmware restoration features of Liu, to include the neural network processor features of Lo in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Adding the neural network processor features of Lo allows for use of a processor architecture adapted for a neural network including a scratchpad memory, a processor core, and an arbitration unit for sharing of scratchpad memory to avoid the disadvantages of peripheral engine IC design where the system utilizes private SRAM instead of sharing the available SRAM of the embedded processor cores, applicable to improving processing systems such as those taught in Li, Sharda, and Liu.
In regards to claim 12. Li in view of Sharda in further view of Liu teach the artificial reality system of claim 11.
Li, Sharda, and Liu does not explicitly disclose but Lo teaches
-wherein the local memory for each processor subsystem is addressable as shared memory (Lo, para [0051]; Reference at [0051] discloses in summary, the embodiment of the processor of this disclosure uses an arbitration unit 4 so that the processor core 2 and the neural network accelerator 3 can share the scratchpad memory 1, and further uses a generic I/O interface (e.g., MMIO, PMIO, etc.) to communicate with the neural network accelerator 3, so as to reduce the cost for developing specialized toolchains and hardware (i.e. distribution of memory among processors as preceding para [0028] discloses the scratchpad memory as an SRAM)).
Li and Lo are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda in further view of the complex logic device firmware restoration features of Liu, to include the neural network processor features of Lo in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Adding the neural network processor features of Lo allows for use of a processor architecture adapted for a neural network including a scratchpad memory, a processor core, and an arbitration unit for sharing of scratchpad memory to avoid the disadvantages of peripheral engine IC design where the system utilizes private SRAM instead of sharing the available SRAM of the embedded processor cores, applicable to improving processing systems such as those taught in Li, Sharda, and Liu.
Claims 14-16 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Li (US 2017/0011555 A1) in view of Sharda (US 9,190,989 B1) in further view of Liu (US 2020/0293661 A1) as applied to claim 10 above, and further in view of Sharma (US 2024/0094907 A1).
In regards to claim 14. Li in view of Sharda in further view of Liu teach the artificial reality system of claim 13.
Li, Sharda, and Liu does not explicitly disclose but Sharma teaches
-wherein the SoC memory further includes Static Random-Access Memory (SRAM), the SRAM distributed to each processor subsystem as local memory (LMEM), wherein pages of virtual memory stored in LMEM are stored to and retrieved from the DRAM (Sharma, para [0042] and [0048]; Reference at [0042] discloses each subsystem includes compute elements 152 (processors or coprocessors) and corresponding local memory 154 (e.g., SRAM) collocated with the compute elements 152. In some such SoCs, portions of on-die SRAM are physically distributed throughout the SoC as Local Memory (LMEM) 154, with a different instance of LMEM 154 located close to each compute element 152. Para [0048] discloses VSMEM 155 may be allocated as virtual memory, with a physical portion of the memory allocated as SMEM in LMEM 15 and with data swapped out to an external volatile memory such as DRAM 160 as needed (i.e. storing and retrieved from DRAM)).
Li and Sharda are combinable because they are in the same field of endeavor regarding data processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li to include the integrated circuit power management system of Sharda in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance, applicable to the graphics processing system as taught in Li.
Li and Liu are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda, to include the complex logic device firmware restoration features of Liu in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system allowing for more secure and efficient storing and processing of data, applicable to the processing systems as taught in Li and Sharda.
Li and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda in further view of the complex logic device firmware restoration features of Liu, to include the systems on chip lossless compression features of Sharma in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Adding the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Li, Sharda, and Liu.
In regards to claim 15. Li in view of Sharda in further view of Liu teach the artificial reality system of claim 10.
Li, Sharda, and Liu does not explicitly disclose but Sharma teaches
-wherein each local memory is allocated as a virtualized static memory (VSMEM), with a portion of the local memory serving as a physical address space for the VSMEM and a portion of off-die memory serving as storage for compressed data blocks that were replaced in the physical address space of VSMEM (Sharma, para [0113]; Reference discloses in some example approaches, SMEM 565 is virtualized as VSMEM, and the activation data is compressed. SMEM redirection is therefore used to direct writes of activation data initially directed to SMEM 565 to compression block 704 for compression. The compressed data is then forwarded to either SMEM 565 of local memory of the appropriate subsystem or to off-die memory 566 via DDR CTRL 712. As shown in FIG. 7 , data to be written to memory 566 may be stored temporarily in a system cache (one of SYSCACHEs 0:3) before being transmitted via downstream NoC 714 to the appropriate section of memory 566).
Li and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda in further view of the complex logic device firmware restoration features of Liu, to include the systems on chip lossless compression features of Sharma in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Adding the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Li, Sharda, and Liu.
In regards to claim 16. Li in view of Sharda in further view of Liu teach the artificial reality system of claim 10.
Li, Sharda, and Liu does not explicitly disclose but Sharma teaches
-wherein the local memory is allocated as a virtualized static memory (VSMEM), with a portion of the local memory serving as a physical address space for the VSMEM and a portion of off-die memory serving as storage for compressed data blocks that are aged out of the physical address space (Sharma, para [0113]; Reference discloses in some example approaches, SMEM 565 is virtualized as VSMEM, and the activation data is compressed. SMEM redirection is therefore used to direct writes of activation data initially directed to SMEM 565 to compression block 704 for compression. The compressed data is then forwarded to either SMEM 565 of local memory of the appropriate subsystem or to off-die memory 566 via DDR CTRL 712. As shown in FIG. 7 , data to be written to memory 566 may be stored temporarily in a system cache (one of SYSCACHEs 0:3) before being transmitted via downstream NoC 714 to the appropriate section of memory 566).
Li and Sharma are also combinable because they are in the same field of endeavor regarding subsystem processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the head mounted display system of Li, in view of the integrated circuit power management system of Sharda in further view of the complex logic device firmware restoration features of Liu, to include the systems on chip lossless compression features of Sharma in order to provide the user with a head mounted display device for displaying augmented reality content to a user as taught by Li, while incorporating the integrated circuit power management system of Sharda to allow for use of a power management system that permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off to optimize power management and system performance. Further incorporating the complex logic device firmware restoration features of Liu allows for use of processes that may determine multiple digital signatures of respective multiple portions of information handling system firmware that is stored in a non-volatile memory medium of an information handling system. Adding the systems on chip lossless compression features of Sharma allows for use of multiple subsystems and a compression block where the system compresses spill data using an encoder and stores the compressed data in a data block in local memory to allow for more efficient handling of large data sets via a virtual memory system, applicable to improving data processing systems such as those taught in Li, Sharda, and Liu.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: See the Notice of References Cited (PTO-892)
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/TERRELL M ROBINSON/Primary Examiner, Art Unit 2614