DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Response to Arguments
Applicant’s arguments with respect to claim(s) 2/27/26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In regards to applicants argument that Sharda et al does not teach the newly added limitation of “the low power subsystem is configured to perform a secure boot of the SoC via the microcontroller executing out of the SRAM of the SoC memory”. Liu et al teaches an SoC (110 [0035] "In one or more embodiments, processor 120 and one or more components of IHS 110 may be included in a system-on-chip (SoC)"), that is booted by a microcontroller ([0019] "a boot management controller (BMC) 185") executing a real-time operating system ([0036] “In one example, OS 262 may be or include a real-time operating system (RTOS)"). All of Sharda et al, Liu et al and Lim et al teach a SRAM none expressly teach “secure boot” “out of the SRAM”. Therefore plural references are being cited that teach secure booting out of a memory and list a SRAM as an example of the possible memory. Hind et al teaches ([0053] “At 310, processor 132 may load the custom boot codes provided by HRoT device 102. For example, the custom boot codes may be loaded on secure memory, such as, for example, SRAM 134. Once loaded, processor 132 may execute or otherwise cause execution of the custom boot codes. The custom boot codes may be executed as part of a secure boot process of processor 132”). It would have been obvious to perform a secure boot out of a SRAM because a secure boot prevents the boot process from being corrupted and a SRAM is a faster memory device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008 and Hird et al PN 2021/0192050.
In regards to claim 1: Sharda et al teaches a system on a chip (SoC) ("a System on Chip device 100") comprising: SoC memory (105, 110, 210,212) including a SRAM memory 210; one or more processor subsystems (104), wherein each processor subsystem includes a processor (104) connected to the SoC memory (105); and a low power subsystem (102 “Referring now to FIG. 1, a System on Chip device 100 in accordance with an embodiment of the present invention is shown. In this example, the SOC 100 has a first (main) domain 101, a second (low power) domain 102 and a third, alive domain 103”) integrated as a separate subsystem in the SoC (101 is separate from 102), wherein the low power subsystem includes a state machine 119 (Sharda et al teaches a state machine instead of a micro controller. While all microcontrollers are state machines not all state machines are microcontrollers) and a power management unit (PMU) (low power mode controller 117), wherein the PMU is connected to each processor subsystem (117 is connected to 104 via central controller 115), the PMU operating under the control of the state machine (119) to control the power to each processor subsystem (104) (“A method of power management of an integrated circuit (such as the SOC described with reference to FIG. 1) by switching between full power and reduced power modes of operation will now be described with reference to the flow chart of FIG. 3 and to FIG. 1. Ina full power mode of operation, both the main domain 101 and low power (SMS) domain 102 are powered up and active (i.e., alive). In a low power, reduced computing mode of operation, the main domain is inactive (i.e., power-gated) and the low power, (SMS) domain is active. Switching between full power and low power modes of operation is initiated by writing into a register in either the central controller or the low power mode controller”). Sharda et al teaches a state machine instead of a microcontroller. Sharda et al also does not teach a microcontroller booting the SoC. Liu et al teaches an SoC (110 [0035] “In one or more embodiments, processor 120 and one or more components of IHS 110 may be included in a system-on-chip (SoC)”), that is booted by a microcontroller ([0019] “a boot management controller (BMC) 185”) executing a real-time operating system ([0036] “In one example, OS 262 may be or include a real-time operating system (RTOS)”). It would have been obvious to have the state machine be a microcontroller that also controls booting because this would integrate functions in a low power system. Lim et al teaches a power controlled processor 210 that has a plurality of processors 211-21N. It would have been obvious to have Sharda et al's subsystem 101 have a plurality of processors/cores because this would have allowed greater processing power in the system. See also MPEP 2144.04 VI B Duplication of parts. All of Sharda et al, Liu et al and Lim et al teach a SRAM none expressly teach “secure boot” “out of the SRAM”. Hind et al teaches ([0053] “At 310, processor 132 may load the custom boot codes provided by HRoT device 102. For example, the custom boot codes may be loaded on secure memory, such as, for example, SRAM 134. Once loaded, processor 132 may execute or otherwise cause execution of the custom boot codes. The custom boot codes may be executed as part of a secure boot process of processor 132”). It would have been obvious to perform a secure boot out of a SRAM because a secure boot prevents the boot process from being corrupted and a SRAM is a faster memory device.
In regards to claim 3: Liu et al teaches a DRAM ([0024] “Volatile memory medium 150 may include volatile storage such as, for example, RAM, DRAM (dynamic RAM), EDO RAM (extended data out RAM), SRAM (static RAM), etc")”).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008 and Hird et al PN 2021/0192050 as applied to claim 3 above, and further in view of Knoth PN 2007/0113013.
In regards to claim 4: Neither Sharda et al nor Liu et al teaches the SoC including a memory management unit. Knoth teaches a SoC with both a Power Management Unit (118) and a memory management unit (110). It would have been obvious to include a memory management unit because this would have increased the amount of memory allowable on the SoC.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008 and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Lo et al PN 2021/0173648.
In regards to claim 5: Sharda et al teaches one processor with one SRAM. Sharda et al does not expressly teach a SRAM distributed to plural processors. Lo et al teaches ([0007] “The PE architecture is disadvantageous in utilizing private SRAM instead of sharing the available SRAM of the embedded processor cores. Typically, embedded processor cores for loT devices are equipped with approximately 64 to 160 KB of tightly coupled memory (TCM) that is made of SRAM and that can support concurrent code executions and data transfers. TCM is also known as tightly integrated memory, scratchpad memory, or local memory”). It would have been obvious to distribute/share the SRAM among the processors because this would have allowed for shared memory.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, Hird et al PN 2021/0192050 and Lo et al PN 2021/0173648 as applied to claim 5 above, and further in view of Iwakiri et al PN 5,321,661.
In regards to claim 6: Sharda et al teaches a SRAM but does not teach a VSMEM. Iwakiri et al teaches (Column I line 9 et seq. “Generally referred to as a pseudo-static random- access memory or a virtual-static random-access memory, a self-refreshing memory has dynamic memory cells that require periodic refreshing, and also has circuits that refresh the memory cells at intervals controlled by a built-in timer. The growing demand for a self- refreshing memory, which combines the ease of use of a static random-access memory (SRAM) with the low cost of a dynamic random-access memory (DRAM), has made it necessary to produce and test self- refreshing memory devices in large quantities”). It would have been obvious to use a VSRAM because this would allow for reallocation of memory to the processors.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Ward et al PN 4,802,116.
In regards to claim 7: Sharda et al does not expressly teach a multi-tasking operating system. Ward et al teaches (column 54 line 34 et seq. “Multi-tasking operating systems (MTOS) used as the basis for real time software are well known” .) It would have been obvious to use a MTOS because this would have allowed for multitasking.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Lee et al PN 2020/0363850.
In regards to claim 8: Sharda et al teaches power management state change from active to low power but does not teach the details of a power management state change. Lee et al teaches (Column 6 line 21 et seq. “As a result of the active suspend request, GENIO generates a power management interrupt (PMI) 92 to the GENCPU 20. The PMI 92 is transmitted to GENCPU 20 as shown in FIG. 1. On receipt of the PMI, GENCPU saves the processing state of the system. This save operation includes saving the contents of system registers and stack pointers in a power management memory area”). It would have been obvious to receive the processing state of the processors that are made inactive by the power management unit because this would have allowed for restoring the state when the processor are re-activated.
Claim(s) 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Mindlin et al PN 2019/0385613.
In regards to claim 9: Sharda et al in view of Liu et al teaches the power management processor as described above but does not teach it in an artificial reality system. Mindlin et al teaches an artificial reality system including a head mounted display ([0087] "As shown, the implementation of media player device 210 shown in FIG. 7A may be implemented as a head- mounted artificial reality device (e.g., a virtual reality gaming device) that includes a head- mounted display screen"). It would have been obvious to allow the power management system to be in an artificial reality system because this would have prevented limiting the system in which the power management is provided.
In regards to claim 11: Liu et al teaches a DRAM ([0024] “Volatile memory medium 150 may include volatile storage such as, for example, RAM, DRAM (dynamic RAM), EDO RAM (extended data out RAM), SRAM (static RAM), etc”).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, Hird et al PN 2021/0192050 and Mindlin et al PN 2019/0385613. as applied to claim 11 above, and further in view of Knoth PN 2007/0113013.
In regards to claim 12: Neither Sharda et al nor Liu et al teaches the SoC including a memory management unit. Knoth teaches a SoC with both a Power Management Unit (118) and a memory management unit (110). It would have been obvious to include a memory management unit because this would have increased the amount of memory allowable on the SoC.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, Hird et al PN 2021/0192050 and Mindlin et al PN 2019/0385613 as applied to claim 9 above, and further in view of Lo et al PN 2021/0173648.
In regards to claim 13: Sharda et al teaches one processor with one SRAM. Sharda et al does not expressly teach a SRAM distributed to plural processors. Lo et al teaches ([0007] “The PE architecture is disadvantageous in utilizing private SRAM instead of sharing the available SRAM of the embedded processor cores. Typically, embedded processor cores for lo devices are equipped with approximately 64 to 160 KB of tightly coupled memory (TCM) that is made of SRAM and that can support concurrent code executions and data transfers. TCM is also known as tightly integrated memory, scratchpad memory, or local memory”). It would have been obvious to distribute/share the SRAM among the processors because this would have allowed for shared memory.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, Hird et al PN 2021/0192050, Mindlin et al PN 2019/0385613 and Lo et al PN 2021/0173648 as applied to claim 13 above, and further in view of Iwakiri et al PN 5,321,661.
In regards to claim 14: Sharda et al teaches a SRAM but does not teach a VSMEM. Iwakiri et al teaches Column | line 9 et seq. “Generally referred to as a pseudo-static random- access memory or a virtual-static random-access memory, a self-refreshing memory has dynamic memory cells that require periodic refreshing, and also has circuits that refresh the memory cells at intervals controlled by a built-in timer. The growing demand for a self- refreshing memory, which combines the ease of use of a static random-access memory (SRAM) with the low cost of a dynamic random-access memory (DRAM), has made it necessary to produce and test self- refreshing memory devices in large quantities”). It would have been obvious to use a VSRAM because this would allow for reallocation of memory to the processors.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, Hird et al PN 2021/0192050 and Mindlin et al PN 2019/0385613 as applied to claim 9 above, and further in view of Ward et al PN 4,802,116.
In regards to claim 15: Sharda et al does not expressly teach a multi-tasking operating system. Ward et al teaches (column 54 line 34 et seq. “Multi-tasking operating systems (MTOS) used as the basis for real time software are well known”.) It would have been obvious to use a MTOS because this would have allowed for multitasking.
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008, Hird et al PN 2021/0192050 and Mindlin et al PN 2019/0385613 as applied to claim 9 above, and further in view of Lee et al PN 2020/0363850.
In regards to claim 16: Sharda et al in view of Liu et al and Mindlin et al teaches the power management in a VR system as described above. Sharda et al teaches power management state change from active to low power but does not teach the details of a power management state change. Lee et al teaches (Column 6 line 21 et seq. “As a result of the active suspend request, GENIO generates a power management interrupt (PMI) 92 to the GENCPU 20. The PMI 92 is transmitted to GENCPU 20 as shown in FIG. 1. On receipt of the PMI, GENCPU saves the processing state of the system. This save operation includes saving the contents of system registers and stack pointers in a power management memory area”). It would have been obvious to receive the processing state of the processors that are made inactive by the power management unit because this would have allowed for restoring the state when the processor are re-activated.
In regards to claim 17: Sharda et al teaches a CPU(core).
In regards to claim 18: Mindlin et al teaches a graphics engine. A graphics engine is known as a graphics accelerator. It would have been obvious to have a graphics accelerator because this would have allowed for quicker graphics.
In regards to claim 19: Liu et al teaches a DRAM ([0024] "Volatile memory medium 150 may include volatile storage such as, for example, RAM, DRAM (dynamic RAM), EDO RAM (extended data out RAM), SRAM (static RAM), etc").
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008 and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Tan et al PN 2019/0172047.
In regards to claim 20: Sharda et al teaches a processor in the low power subsystem. Hird et al teaches a secure boot but neither teaches the processor in the low power subsystem may be a security processor. Tan et al teaches ([0106] “When there is no security software application needing to be executed, the security processor system 23 or some components in the security processor system 23, for example, the security processor 31, may enter a low power consumption state, that is, a standby state. The security processor 31 may suspend working in this state, to reduce power consumption”). It would have been obvious to have at least one of the processors in the low power subsystem be a security processor because this would have allowed for power saving “when there is no security software application needing to be executed”.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008 and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Krishnamoorthy et al PN 2009/0067851.
In regards to claim 21: Sharda et al teaches wake-up circuitry to wake up the processors in the low power subsystem but does not expressly state the wake up is in “accordance with a determination that additional computing resources are needed”. Krishnamoorthy et al teaches ([0009] “Additionally, individual processor cores can be selectively enabled, thereby allowing unused processor cores to be put into a sleep mode to conserve power and then awakened when they are needed”). It would have been obvious to wake the processors when they are needed because this would have prevented the processors being asleep when they are needed.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharda et al PN 9,190,989 in view of Liu et al PN 2020/0293661, Lim et al PN 2017/0139008 and Hird et al PN 2021/0192050 as applied to claim 1 above, and further in view of Kumar Addepalli et al PN 2020/0250510.
In regards to claim 22: While Sharda et al teaches an operating system, Sharda et al is silent on any details of the functionality of the operating system. Kumar Addepalli et al teaches ([0047] “Therefore, this implementation will not require a full stack, OS, or VM software overhead. In one aspect, the present disclosure provides an AI solution model processing hardware that can intake an AI solution model and the corresponding training/inference data directly into hardware without any full stack software overhead in the processing path”). It would have been obvious to use a smaller operating system without a full stack because this would have lessened the amount of memory needed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Multiple references are cited that teach secure boot from a memory and the memory may be a SRAM.
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/Paul R. MYERS/ Primary Examiner, Art Unit 2176