DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I for examination on which claims 1-9, 11-16, and 18-20 in the reply filed on 04/02/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-9, 11, 14-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. 20210257275.
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Regarding claim 1, fig. 7 of Park discloses a semiconductor package comprising:
a first semiconductor chip 212;
at least one second semiconductor chip (318, 328, 338) on a top surface of the first semiconductor chip;
a molding layer (114 and 300) on the at least one second semiconductor chip; and
a marking layer (side vertical layer portion of 400) on at least one side of the molding layer, the marking layer comprising a hydrophobic material ([0062] the other may exhibit hydrophobicity),
wherein inner sidewalls of the marking layer contact a lower portion of sidewalls of the molding layer (see vertical side portion of 400 contact lower portions 114 and 300).
Regarding claim 3, fig. 7 of Park discloses wherein the molding layer exposes the marking layer.
Regarding claim 6, fig. 7 of Park discloses wherein the marking layer surrounds the molding layer when viewed in a plan view (this is necessary the case), and wherein outer sidewalls of the marking layer are coplanar with sidewalls of the first semiconductor chip (not that a horizontal plane passes through both elements making it coplanar).
Regarding claim 7, fig. 7 of Park discloses wherein the first semiconductor chip has a first width in a first horizontal direction, and wherein the molding layer has a second width (width of 300 around width of 318) smaller than the first width in the first horizontal direction.
Regarding claim 8, fig. 7 of Park disclose wherein the marking layer is on edge regions (the region around 114) of the first semiconductor chip, and wherein a top surface of the molding layer (top of 300) is at a higher level than a top surface of the marking layer in a vertical direction (higher than portion of 400 in 114 region).
Regarding claim 9, fig. 7 of Park discloses wherein the first semiconductor chip 212 has a first width in a first horizontal direction, wherein a top surface of the molding layer has a second width equal to the first width in the first horizontal direction, and wherein a bottom surface of the molding layer has a third width (width between each of 312)) smaller than the second width in the first horizontal direction.
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Regarding claim 11, fig. 7 of Park discloses a semiconductor package comprising:
a first semiconductor chip 212;
a plurality of second semiconductor chips (318/328/338) on a top surface of the first semiconductor chip;
a marking layer (side vertical layer of 400) on peripheral regions of the top surface of the first semiconductor chip, surrounding the plurality of second semiconductor chips when viewed in a plan view (this is necessary the case), and spaced apart from the plurality of second semiconductor chips; and
a molding layer (300/114) on the plurality of second semiconductor chips and comprising sidewalls contacting inner sidewalls of the marking layer,
wherein a level of a top surface of the marking layer (as labeled by examiner above) is lower than a level of the top surface of the molding layer in a vertical direction.
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Regarding claim 14, fig. 7 of Park discloses wherein the marking layer surrounds the molding layer when viewed in a plan view, and wherein outer sidewalls of the marking layer are coplanar with sidewalls of the first semiconductor chip.
Regarding claim 15 (see rejection of claim 7 above), Park discloses wherein the first semiconductor chip has a first width in a first horizontal direction, and wherein the molding layer has a second width smaller than the first width in the first horizontal direction.
Regarding claim 16 (see rejection of claim 9 above), Park discloses wherein the first semiconductor chip has a first width in a first horizontal direction, wherein a top surface of the molding layer has a second width equal to the first width in the first horizontal direction, and wherein a bottom surface of the molding layer has a third width smaller than the second width in the first horizontal direction.
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Regarding claim 18, fig. 12 of Park a semiconductor package comprising:
a redistribution layer (RDL) interposer 220;
a buffer chip comprising a first substrate 212 and a plurality of first through electrodes 216 at least partially penetrating through the first substrate, an active surface of the first substrate facing the RDL interposer and in contact with the RDL interposer;
a plurality of memory cell chips (par [0104] - third to sixth semiconductor chips 732, 742, 752, and 762 may be, for example, memory chips) respectively comprising a second substrate 722 and a plurality of second through electrodes 726 at least partially penetrating through the second substrate, the plurality of memory cell chips being sequentially on the buffer chip, such that an active surface of the second substrate faces the buffer chip;
a plurality of front surface connection pads on bottom surfaces of the plurality of memory cell chips (see fig. 12 for connection configuration);
a plurality of rear surface connection pads 246 on an inactive surface of the first substrate and an inactive surface of the second substrate (see fig. 12 for connection configuration);
a plurality of chip connection terminals 704 between the plurality of front surface connection pads and the plurality of rear surface connection pads;
an insulating adhesive layer 712 between the buffer chip and the plurality of memory cell chips;
a molding layer 770/702 surrounding the plurality of memory cell chips and the insulating adhesive layer; and
a marking layer 404 (this marks the top surface of molding layer 770) on at least one side of the molding layer on the buffer chip and comprising a hydrophobic material (par [0060] - the other may exhibit hydrophobicity).
Regarding claim 20, fig. 12 of Park discloses wherein the buffer chip has a first width in a first horizontal direction, and wherein the molding layer has a second width smaller than the first width in the first horizontal direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Urban 20180127533.
Regarding claims 2, 12 and 19, Park discloses claim 18. Park discloses wherein a surface of the marking layer has hydrophobic characteristics (par [0060] - the other may exhibit hydrophobicity).
Park does not disclose wherein the marking layer comprises a fluorocarbon layer.
However, par [0077] that hydrophobic monomers represented the series of fluorinated acrylates and methacrylates (M.sub.F) with the fluorinated carbon sidechains of CF.sub.2CF.sub.3, CH(CF.sub.3).sub.2, and CF.sub.2CF.sub.2CF.sub.3. As the number of fluorocarbons increased, higher hydrophobicity and sparse water solubility changed, thus affecting in-situ phase separation in the aqueous phase as well as polymerization kinetics of the block copolymer formation.
As such it would have been obvious to form a package of Park comprising wherein the marking layer comprises a fluorocarbon layer such as taught by Urban in order to form a hydrophobic material layer.
Claims 4-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park.
Regarding claims 4-5 and 13, Park does not disclose wherein a thickness of the marking layer ranges from 10 angstroms to 5000 angstroms, and wherein a width of the marking layer ranges from 10 micrometers to 500 micrometers.
However, Park structure inherently comprises wherein a thickness of the marking layer ranges from unknown angstroms to another unknown angstroms, and wherein a width of the marking layer ranges from an unknown micrometers to another unknown micrometers.
In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a package of park comprising wherein a thickness of the marking layer ranges from 10 angstroms to 5000 angstroms/wherein a width of the marking layer ranges from 10 micrometers to 500 micrometers in order to meet the applicant design dimensions.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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