Prosecution Insights
Last updated: October 02, 2026
Application No. 18/410,716

Noise Mitigation in Dynamic Quantum Circuits by Inserting Context-Dependent Dynamical Decoupling Sequences

Non-Final OA §103
Filed
Jan 11, 2024
Examiner
NIMOX, RAYMOND LONDALE
Art Unit
2857
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Non-Final)
71%
Grant Probability
Favorable
2-3
OA Rounds
4m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
344 granted / 487 resolved
+2.6% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
43 currently pending
Career history
526
Total Applications
across all art units

Statute-Specific Performance

§101
37.6%
-2.4% vs TC avg
§103
26.2%
-13.8% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 487 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 6, 8, 9, 13, 15, 16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CAPELLUTO ET AL. (US 20220188182 A1) (hereinafter “CAPELLUTO”) in view of BERNIEN ET AL. (US 20260044767 A1) (hereinafter “BERNIEN”). With respect to Claim(s) 1, 8, 15, CAPELLUTO teaches embodiments for error mitigation in quantum programs. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components can include a noise assessment component that identifies a noise condition of a qubit device based on a noise property of quantum hardware configured to operate on the qubit device. The qubit device is represented in a quantum program executable on the noisy quantum hardware. The computer-executable components also can include a compilation component that modifies the quantum program by inserting a defined sequence of error-mitigating operations into the quantum program based on the noise condition and the BRI of: A system (See, e.g., Fig(s). 1A-2, 4, 6, 7, 9, 11-13), comprising: a memory for storing a computer program (See, e.g., Fig(s). 1A-2, 4, 6, 7, 9, 11-13) for implementing noise mitigation in dynamic quantum circuits (See, e.g., ¶ ABSTRACT); and a processor connected to said memory (See, e.g., Fig(s). 1A-2, 4, 6, 7, 9, 11-13), wherein said processor is configured to execute program instructions of the computer program comprising: identifying a condition in a quantum circuit (See, e.g., ¶ ABSTRACT, 0048, 0064, 0067; See also, e.g., Fig(s). 1A-13); and inserting a context-dependent dynamical decoupling sequence in said quantum circuit based on said identified condition (See, e.g., ¶ ABSTRACT, 0026; See also, e.g., Fig(s). 1A-13). However, CAPELLUTO is lacking the explicit language of: a dynamic quantum circuit. DILUOFFO teaches executing logic for quantum computing and the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). It would have been obvious to one ordinary skill in the art, at the time before the effective filing date of the claimed invention, to modify CAPELLUTO to include a dynamic quantum circuit. One of ordinary skill in the art would have been motivated to modify CAPELLUTO because it would be beneficial to perform measurements in the middle of the circuit. Further, it would be obvious to combine prior art elements according to known methods to yield predictable results, simply substitute one known element for another to obtain predictable results, use known techniques to improve similar devices in the same way, and/or apply a known technique to a known device ready for improvement to yield predictable results. With respect to Claim(s) 2, 9, 16, CAPELLUTO, DILUOFFO teaches the BRI of the parent claim(s). DILUOFFO teaches the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). CAPELLUTO further teaches the BRI of: said condition comprises one of the following in the group consisting of an idling time, spectator qubits and idling qubits in cross-talk resistant states in said quantum circuit (See, e.g., ¶ 0039, 0040, 0045, 0047, 0048, 0054, 0056; See also, e.g., Fig(s). 3). With respect to Claim(s) 6, 13, 20, CAPELLUTO, DILUOFFO teaches the BRI of the parent claim(s). DILUOFFO teaches the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). CAPELLUTO further teaches the BRI of: said dynamical decoupling sequence is inserted in said quantum circuit during an occurrence of a unitary gate in said dynamic quantum circuit (See, e.g., ¶ 0031). Claim(s) 3, 4, 10, 11, 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the cited reference(s) of the parent claim(s) in view of BERNIEN ET AL. (US 20260044767 A1) (hereinafter “BERNIEN”). With respect to Claim(s) 3, 10, 17, CAPELLUTO, DILUOFFO teaches the BRI of the parent claim(s). CAPELLUTO teaches the BRI of: said dynamical decoupling sequence is inserted in said quantum circuit. DILUOFFO teaches the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). However, CAPELLUTO is lacking the explicit language of: during a mid-circuit measurement. BERNIEN teaches a data quantum circuit with data qubits and the BRI of: mitigating the effects of noise during a mid-circuit measurement (See, e.g., ¶ 0072). It would have been obvious to one ordinary skill in the art, at the time before the effective filing date of the claimed invention, to modify CAPELLUTO to include during a mid-circuit measurement. One of ordinary skill in the art would have been motivated to modify CAPELLUTO because it would be beneficial to mitigating the effects of noise. Further, it would be obvious to combine prior art elements according to known methods to yield predictable results, simply substitute one known element for another to obtain predictable results, use known techniques to improve similar devices in the same way, and/or apply a known technique to a known device ready for improvement to yield predictable results. With respect to Claim(s) 4, 11, 18, CAPELLUTO, DILUOFFO teaches the BRI of the parent claim(s). CAPELLUTO teaches the BRI of: said dynamical decoupling sequence is inserted in said quantum circuit. DILUOFFO teaches the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). However, CAPELLUTO is lacking the explicit language of: during an occurrence of a feed-forward operation. BERNIEN teaches a data quantum circuit with data qubits and the BRI of: mitigating the effects of noise during an occurrence of a feed-forward operation (See, e.g., ¶ 0072) It would have been obvious to one ordinary skill in the art, at the time before the effective filing date of the claimed invention, to modify CAPELLUTO to include during an occurrence of a feed-forward operation. One of ordinary skill in the art would have been motivated to modify CAPELLUTO because it would be beneficial to mitigating the effects of noise. Further, it would be obvious to combine prior art elements according to known methods to yield predictable results, simply substitute one known element for another to obtain predictable results, use known techniques to improve similar devices in the same way, and/or apply a known technique to a known device ready for improvement to yield predictable results. Claim(s) 5, 7, 12, 14, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the cited reference(s) of the parent claim(s) in view of SOLANO ET AL. (US 20260037849 A1) (hereinafter “SOLANO”). With respect to Claim(s) 5, 12, 19, CAPELLUTO, DILUOFFO teaches the BRI of the parent claim(s). CAPELLUTO teaches the BRI of: said dynamical decoupling sequence is inserted in said quantum circuit. DILUOFFO teaches the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). However, CAPELLUTO is lacking the explicit language of: during an occurrence of qubit shuttling or qubit swapping. SOLANO teaches a digital quantum algorithm and the BRI of: error-mitigation techniques during an occurrence of qubit shuttling or qubit swapping (See, e.g., ¶ 0131-0137). It would have been obvious to one ordinary skill in the art, at the time before the effective filing date of the claimed invention, to modify CAPELLUTO to include during an occurrence of qubit shuttling or qubit swapping. One of ordinary skill in the art would have been motivated to modify CAPELLUTO because it would be beneficial to mitigating the effects of noise. Further, it would be obvious to combine prior art elements according to known methods to yield predictable results, simply substitute one known element for another to obtain predictable results, use known techniques to improve similar devices in the same way, and/or apply a known technique to a known device ready for improvement to yield predictable results. With respect to Claim(s) 7, 14, CAPELLUTO, DILUOFFO teaches the BRI of the parent claim(s). DILUOFFO teaches the BRI of: a dynamic quantum circuit (See, e.g., ¶ 0034). CAPELLUTO further teaches the BRI of: scheduling said quantum circuit to be executed, wherein said condition is identified in said scheduled quantum circuit (See, e.g., ¶ 0024-0030, 0044, 0045, 0069). However, CAPELLUTO is lacking the explicit language of: decomposing said dynamic quantum circuit into native gates and mapping of said dynamic quantum circuit onto a native topology. SOLANO teaches a digital quantum algorithm and the BRI of: decomposing said dynamic quantum circuit into native gates and mapping of said dynamic quantum circuit onto a native topology (See, e.g., ¶ 0075). It would have been obvious to one ordinary skill in the art, at the time before the effective filing date of the claimed invention, to modify CAPELLUTO to include decomposing said dynamic quantum circuit into native gates and mapping of said dynamic quantum circuit onto a native topology. One of ordinary skill in the art would have been motivated to modify CAPELLUTO because it would be beneficial to mitigating the effects of noise. Further, it would be obvious to combine prior art elements according to known methods to yield predictable results, simply substitute one known element for another to obtain predictable results, use known techniques to improve similar devices in the same way, and/or apply a known technique to a known device ready for improvement to yield predictable results. Response to Arguments Applicant's argument(s)/remark(s), see page(s) 2-7, filed 04/27/2026, with respect to the art rejection(s) has/have been fully considered. -Applicant states “REJECTIONS UNDER 35 U.S.C. Q102: The Examiner has rejected claims 1-2, 6, 8-9, 13, 15-16 and 20 under 35 U.S.C. § 102(a)(1) as being anticipated by Capelluto et al. (U.S. Patent Application Publication No. 2022/0188182) (hereinafter "Capelluto"). Applicant respectfully traverses these rejections for at least the reasons stated below and respectfully requests the Examiner to reconsider and withdraw these rejections. For a claim to be anticipated under 35 U.S.C. §102, each and every claim limitation must be found within the cited prior art reference and arranged as required by the claim. M.P.E.P. §2131.”. -Applicant states “Applicant respectfully asserts that Capelluto does not disclose "identifying a condition in a dynamic quantum circuit" as recited in claim 1 and similarly in claims 8 and 15. The Examiner cites the Abstract, paragraphs [0048, 0064 and 0067] and Figures 1A-13 of Capelluto as disclosing the above-cited claim limitation. Office Action (4/3/2026), page 3. Applicant respectfully traverses. Capelluto discloses a noise assessment component that identifies a noise condition of a qubit device based on a noise property of quantum hardware configured to operate on the qubit device. Abstract. Capelluto further discloses that the qubit device is represented in a quantum program executable on the noisy quantum hardware. Abstract. Capelluto additionally discloses that the compiler system 120 can then determine, using the magnitude of the idling period 330 and the noise condition that satisfies the error-mitigation rule, a DD sequence of pulses to be inserted into the quantum circuit 300. [0048]. Furthermore, Capelluto discloses that at least one of the processor(s) 910 can execute the machine-accessible components to cause the compiler system 120 to identify a noise condition of a quantum device (e.g., a qubit device or a qudit device), and modify the quantum program by inserting a sequence of error- mitigating operations into the quantum program in response to the noise condition satisfying a noise-mitigation rule during compilation of the quantum program, in accordance with aspects of this disclosure. [0064]. Additionally, Capelluto discloses that at block 1010, the computing system can identify a noise condition of a qubit device based on a noise property of noisy quantum hardware configured to operate on the qubit device. [0067]. In addition, Capelluto discloses that such a noise condition can be identified by the noise assessment component 220 (Figure 2), for example. [0067]. Capelluto further discloses that the qubit device is represented in a quantum program for execution on the noisy quantum hardware. [0067]. Capelluto additionally discloses that identifying such a noise condition can include, for example, continually receiving data indicating a contemporaneous characteristic of noise affecting the qubit device. [0067]. Hence, Capelluto discloses identifying a noise condition of a qubit device based on a noise property of quantum hardware configured to operate on the qubit device. Capelluto further discloses that the qubit device is represented in a quantum program executable on the noisy quantum hardware. Capelluto additionally discloses that the compiler system can then determine, using the magnitude of the idling period and the noise condition that satisfies the error-mitigation rule, a DD sequence of pulses to be inserted into the quantum circuit. Furthermore, Capelluto discloses causing the compiler system to identify a noise condition of a quantum device (e.g., a qubit device or a qudit device), and modify the quantum program by inserting a sequence of error- mitigating operations into the quantum program in response to the noise condition satisfying a noise-mitigation rule during compilation of the quantum program. Additionally, Capelluto discloses that the computing system can identify a noise condition of a qubit device based on a noise property of noisy quantum hardware configured to operate on the qubit device. In addition, Capelluto discloses that the qubit device is represented in a quantum program for execution on the noisy quantum hardware. There is no language in the cited passages or in the description of Figures 1A- 13 of Capelluto that discloses identifying a condition in a dynamic quantum circuit. Instead, Capelluto simply discloses identifying a noise condition of a qubit device based on a noise property of quantum hardware configured to operate on the qubit device, where the qubit device is represented in a quantum program executable on the noisy quantum hardware. Thus, Capelluto does not disclose all of the limitations of claims 1, 8 and 15, and thus Capelluto does not anticipate claims 1, 8 and 15. M.P.E.P. §2131.”. Examiner agrees with the underlined argument(s)/remark(s). Although CAPELLUTO teaches the BRI of the claimed method for a ‘quantum circuit’, CAPELLUTO fails to explicitly limit the particular type of ‘quantum circuit’ to ‘static’ or ‘dynamic’. Therefore, Examiner has updated the rejection(s) to 103 obviousness rejection(s). Said rejection(s) has/have been withdrawn/updated. New grounds of rejection(s) was not necessitated by amendment(s). Therefore, this will be a 2nd Non-Final. See updated rejection(s) above. -Applicant states “Applicant further asserts that Capelluto does not disclose "inserting a context- dependent dynamical decoupling sequence in said dynamic quantum circuit based on said identified condition" as recited in claim 1 and similarly in claims 8 and 15. The Examiner cites the Abstract, paragraph [0026] and Figures 1A-13 of Capelluto as disclosing the above-cited claim limitation. Office Action (4/3/2026), page 3. Applicant respectfully traverses. Capelluto discloses a noise assessment component that identifies a noise condition of a qubit device based on a noise property of quantum hardware configured to operate on the qubit device. Abstract. Capelluto further discloses that the qubit device is represented in a quantum program executable on the noisy quantum hardware. Abstract. Capelluto additionally discloses a compilation component that modifies the quantum program by inserting a defined sequence of error-mitigating operations into the quantum program based on the noise condition. Abstract. Furthermore, Capelluto discloses that the compiler system can then determine if the noise condition satisfies an error-mitigation rule. [0026]. Additionally, Capelluto discloses that an affirmative determination can cause the compiler system to modify the quantum program by inserting a defined sequence of error-mitigating operations into the quantum program. [0026]. In addition, Capelluto discloses that such a sequence can be specific to the noise condition in order suppress a coupling between the quantum device and a noise source (environmental or otherwise). [0026]. Capelluto further discloses that in some cases, the defined sequence of error-mitigating operations can include one or many iterations of an XY sequence (e.g., XY4 or XY8 sequence); one or many iterations of a Can-Purcell (CP) sequence; one or many iterations of a Carr-Purcell-Meiboom-Gill (CPMG) sequence; one or many iterations of a Uhrig dynamical decoupling (UDD) sequence; one or more iterations of a concatenated dynamical decoupling (CDD) sequence; Knill dynamical decoupling (KDD) sequence. [0026]. Capelluto additionally discloses that in addition, or in other cases, the defined sequence of error- mitigating operations can include a multi-qubit sequence, such as one or more iterations of a nested UDD (NUDD) sequence or one or more iterations of a nested CDD (NCDD) sequence. [0026]. Hence, Capelluto discloses identifying a noise condition of a qubit device based on a noise property of quantum hardware configured to operate on the qubit device. Capelluto further discloses that the qubit device is represented in a quantum program executable on the noisy quantum hardware. Capelluto additionally discloses a compilation component that modifies the quantum program by inserting a defined sequence of error-mitigating operations into the quantum program based on the noise condition. Furthermore, Capelluto discloses that the compiler system can then determine if the noise condition satisfies an error-mitigation rule. Additionally, Capelluto discloses that an affirmative determination can cause the compiler system to modify the quantum program by inserting a defined sequence of error-mitigating operations into the quantum program. In addition, Capelluto discloses that such a sequence can be specific to the noise condition in order suppress a coupling between the quantum device and a noise source (environmental or otherwise). Capelluto further discloses that in some cases, the defined sequence of error-mitigating operations can include one or many iterations of a Uhrig dynamical decoupling (UDD) sequence; one or more iterations of a concatenated dynamical decoupling (CDD) sequence; or a Knill dynamical decoupling (KDD) sequence. There is no language in the cited passages or in the description of Figures 1A- 13 of Capelluto that discloses inserting a context-dependent dynamical decoupling sequence in the dynamic quantum circuit based on the identified condition. Instead, Capelluto simply discloses inserting a defined sequence of error- mitigating operations into the quantum program (as opposed to a dynamic quantum circuit) based on the noise condition. Furthermore, Capelluto discloses that an example of such a sequence of mitigating operations can correspond to one or many iterations of a Uhrig dynamical decoupling (UDD) sequence; one or more iterations of a concatenated dynamical decoupling (CDD) sequence; or a Knill dynamical decoupling (KDD) sequence. There is no discussion in Capelluto regarding a context-dependent dynamical decoupling sequence. Thus, Capelluto does not disclose all of the limitations of claims 1, 8 and 15, and thus Capelluto does not anticipate claims 1, 8 and 15. M.P.E.P. §2131.”. See response above. -Applicant states “Claims 2 and 6 each recite a combination of features of independent claim 1, and hence claims 2 and 6 are not anticipated by Capelluto for at least the reasons that claim 1 is not anticipated by Capelluto. Furthermore, claims 9 and 13 each recite a combination of features of independent claim 8, and hence claims 9 and 13 are not anticipated by Capelluto for at least the reasons that claim 8 is not anticipated by Capelluto. Additionally, claims 16 and 20 each recite a combination of features of independent claim 15, and hence claims 16 and 20 are not anticipated by Capelluto for at least the reasons that claim 15 is not anticipated by Capelluto.”. See response above. -Applicant states “II. REJECTIONS UNDER 35 U.S.C. Q 103: The Examiner has rejected claims 3, 4, 10, 11, 17 and 18 under 35 U.S.C. § 103 as being unpatentable over Capelluto in view of Bernien et al. (U.S. Patent Application Publication No. 2026/0044767) (hereinafter "Bernien"). The Examiner has further rejected claims 5, 7, 12, 14 and 19 under 35 U.S.C. §103 as being unpatentable over Capelluto in view of Solano et al. (U.S. Patent Application Publication No. 2026/0037849) (hereinafter "Solano"). Applicant respectfully traverses these rejections for at least the reasons stated below and respectfully requests the Examiner to reconsider and withdraw these rejections. Claims 3 and 4 each recite a combination of features of independent claim 1, and hence claims 3 and 4 are patentable over Capelluto in view of Bernien for at least the reasons that claim 1 is not anticipated by Capelluto. Furthermore, claims 10 and 11 each recite a combination of features of independent claim 8, and hence claims 10 and 11 are patentable over Capelluto in view of Bernien for at least the reasons that claim 8 is not anticipated by Capelluto. Additionally, claims 17 and 18 each recite a combination of features of independent claim 15, and hence claims 17 and 18 are patentable over Capelluto in view of Bernien for at least the reasons that claim 15 is not anticipated by Capelluto. Furthermore, claims 5 and 7 each recite a combination of features of independent claim 1, and hence claims 5 and 7 are patentable over Capelluto in view of Solano for at least the reasons that claim 1 is not anticipated by Capelluto. Additionally, claims 12 and 14 each recite a combination of features of independent claim 8, and hence claims 12 and 14 are patentable over Capelluto in view of Solano for at least the reasons that claim 8 is not anticipated by Capelluto. Furthermore, claim 19 recites a combination of features of independent claim 15, and hence claim 19 is patentable over Capelluto in view of Solano for at least the reasons that claim 15 is not anticipated by Capelluto.”. See response above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYMOND NIMOX whose telephone number is (469)295-9226. The examiner can normally be reached Mon-Thu 10am-8pm CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREW SCHECHTER can be reached at (571) 272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. RAYMOND NIMOX Primary Examiner Art Unit 2857 /RAYMOND L NIMOX/Primary Examiner, Art Unit 2857
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Prosecution Timeline

Jan 11, 2024
Application Filed
Apr 03, 2026
Non-Final Rejection mailed — §103
Apr 27, 2026
Response Filed
Jul 21, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
71%
Grant Probability
81%
With Interview (+10.0%)
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