DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Priority
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claims 1 – 20 are pending for examination. Claims 1 -2, 10 – 11, and 19 – 20 are currently amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Koeplinger et al., (US PUB 20220092247 hereinafter Koeplinger) in view of Chang et al., (US PUB 2022/0066760 hereinafter Chang).
Koeplinger and Chang references were cited in previous office action.
As to claim 1, Koeplinger teaches a data processing method, wherein the method is performed by a data processing system, the data processing system comprises a processor (“...processors...” para. 0029) and a computing core (“..The compile time logic has access to the memory and is configured to process the dataflow graph to determine, for the tensors, expected producer memory layouts, expected consumer memory layouts, and current memory layouts....” para. 0029 - 0040), and the method comprises:
obtaining, by the processor, metadata (“...the memory layout metadata 2602 (e.g., 2612, 2622, 2632) is fed to a translation function 2604 along with the underlying tensor (e.g., tensor 302) to retrieve the memory layouts...” para. 0151 and 0152. Note: each memory layout having memory layout metadata) of first data (“...current memory layouts...” abstract and para. 0030, 0038) and (“..Each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment...” para. 0030). and metadata of second data (“...expected consumer memory layout...” abstract and para. 0030 – 0041) and (“...a consumer's expected memory layout...” para. 0136),
wherein the second data is obtained by performing a first operation set on the first data (“...In one implementation, the compile time logic is further configured to reprocess the dataflow graph in a backward traversal, starting from a last operation unit and progressing to preceding operation units, to determine the expected consumer memory layouts using the memory layout functions, and redetermine the current memory layouts based on the expected consumer memory layouts...” para. 0032) and (“…the memory layout conversion operations include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors…” para. 0038) and (“..iterate the processing and the reprocessing of the dataflow graph until convergence...” para. 0034),
wherein the first operation set comprises at least two first operations (“...process the dataflow graph in a forward traversal, starting from a first operation unit and progressing to successive operation units, to determine the expected producer memory layouts using the memory layout functions, and the current memory layouts based on the expected producer memory layouts. In one implementation, the compile time logic is further configured to reprocess the dataflow graph in a backward traversal, starting from a last operation unit and progressing to preceding operation units, to determine the expected consumer memory layouts using the memory layout functions...” para. 0032) and (“…In some implementations, the memory layout conversion operations include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors. In other implementations, the memory layout conversion operations include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors…” para. 0038), and
wherein memory addresses associated with elements at adjacent positions in each row of the second data (“Each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment. The memory layouts provide a mapping between elements of the tensors and locations in linear memory. A linear memory model, also known as the flat memory model, refers to a memory addressing technique in which memory is organized in a single contiguous address space. This means that a processing unit can access these memory locations directly as well as linearly. An address is an offset which is used to denote the exact place of a memory chunk. Data is the value stored in that memory location. In a linear memory model, the entire memory space is linear, sequential, and contiguous...” para. 0102) and (“...FIG. 3 also shows a column (C) vector dimension 312 and a row (R) vector dimension 322...” figures 3 and 4 and associated text, especially para. 0103 – 0104. Note: memory are in rows and columns) [are discontinuous];
identifying, by the processor, the first operation set based on the metadata of the second data, and determining each first operation in the first operation set (“...detect the memory layout conflict when the expected consumer memory layouts are different from corresponding ones of the current memory layouts, and to resolve the memory layout conflict by modifying the dataflow graph... In some implementations, the memory layout conversion operations include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors. In other implementations, the memory layout conversion operations include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors. In yet other implementations, the memory layout conversion operations include a realignment operation that modifies the current memory layouts by changing the data alignment of the corresponding ones of the tensors…” para. 0037 – 0038 and 0040);
determining, by the processor, a second operation set that matches the first operation set, wherein a second operation that matches each first operation in the first operation set exists in the second operation set (“...to cause the expected consumer memory layouts to match the corresponding ones of the current memory layouts.” para. 0037 and 0040) and (“…The compile time logic is further configured to insert, in the dataflow graph, new operation units that implement the memory layout conversion operations, and to generate an updated version of the dataflow graph. In some implementations, the compile time logic is further configured to iterate the processing and the reprocessing of the updated version of the dataflow graph as long as the undefined instances of the current memory layouts and the memory layout conflict are detected” para. 0038); and
obtaining, by the computing core, third data based on the first data and the second operation set (“..In some implementations, the compile time logic is further configured to iterate the processing and the reprocessing of the updated version of the dataflow graph as long as the undefined instances of the current memory layouts and the memory layout conflict are detected....” para. 0038. Note: the second operation set is the same with the first operation set that iterates the processing of the conversion operations that comprises transpose operation, insert... util the current memory layouts and the expected memory layouts are matched/convergence as mapped the first operation set as taught para. 0034 – 0037 and 0040 - 0041) and (“...If no memory layout conflicts are detected, then the final memory layouts 274 are produced as output...” para. 0131. Note: the output is the third data after the first and second operation sets described above process and produce final output), wherein memory addresses associated with elements at adjacent positions in each row of the third data are continuous (“Each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment. The memory layouts provide a mapping between elements of the tensors and locations in linear memory. A linear memory model, also known as the flat memory model, refers to a memory addressing technique in which memory is organized in a single contiguous address space. This means that a processing unit can access these memory locations directly as well as linearly. An address is an offset which is used to denote the exact place of a memory chunk. Data is the value stored in that memory location. In a linear memory model, the entire memory space is linear, sequential, and contiguous....” figure 4 and associated text, especially para. 0102) and (“…In other implementations, the memory layout conversion operations 262 include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors. In yet other implementations, the memory layout conversion operations 262 include a realignment operation that modifies the current memory layouts by changing the data alignment of the corresponding ones of the tensors.” Para. 0126).
While Koeplinger teaches the expected consumer memory layouts is different and conflict with the current memory layouts (0037 – 0038 and 0040), and provide mapping between elements of the tensors until the memory are matched and contiguous according to the memory layout and linear memory model (para. 0102) and apply memory layout functions like discontinuous (“...The memory layout functions 212 span all known operation types like non-linearities...” para. 0111), Koeplinger does not but Chang teaches the data is discontinuous (“...The inference engine circuit architecture 50 implements a “tensor” construct, in which data operation may be performed across a three-dimensional volume of non-contiguous data...” para. 0074),
wherein the first data is a source tensor (“…The tensor decoder 250 of the MM processor circuit 200 and/or MM accelerator circuits 100 can process a single instruction to read such a volume of data, tensor 144, given a start address 132, a depth 134 (for obtaining data in a “depth first” pattern), a stride 138 from a second or end address 136 of the first data plane 151 to the next non-contiguous data start address 140 of the second or next data plane 152, and continuing through the last or end address 142, bringing in multiple planes 151, 152, and 153 of maps or kernel data of the selected tensor 144,…” para. 0074), wherein the second data is a discontinuous tensor [obtained by performing the first operation set] on the source tensor (“…a stride 138 from a second or end address 136 of the first data plane 151 to the next non-contiguous data start address 140 of the second or next data plane 152, and continuing through the last or end address 142, bringing in multiple planes 151, 152, and 153 of maps or kernel data of the selected tensor 144,…” para. 0074), wherein the third data is a continuous tensor [obtained by performing the second operation set on the source tensor (“…the tensor decoder circuit adapted to generate and output a sequence of addresses starting with a base address and incrementing the base address until the output address is equal to the base address plus a tensor length…” para. 0016), and wherein the first operation is a discontinuous framework operator (“…a stride 138 from a second or end address 136 of the first data plane 151 to the next non-contiguous data start address 140 of the second or next data plane 152, and continuing through the last or end address 142, bringing in multiple planes 151, 152, and 153 of maps or kernel data of the selected tensor 144,…” para. 0074).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Koeplinger by applying the teachings of Chang because Chang also teaches mapping memory address of non-contiguous tensor to be contiguous tensor (para 0030) and provides multiple operation sets while mapping processes and multiple operation sets including first and second sets such as stride and transpose (para. 0074, 0113, 0124, and 0202, etc.) used for Koeplinger’s mapping processes. Chang would clearly provide the method of merging or mapping from non-contiguous data to contiguous to make data consistent to provide high performance for applications (para. 0010, 0113 and 0152).
As to claim 2, Koeplinger modified by Chang teaches The method according to claim 1, Koeplinger teaches wherein the identifying, by the processor, the first operation set based on the metadata of the second data, and the determining each first operation in the first operation set comprise:
sequentially identifying, by the processor, based on a preset priority (“..at least one of a vector ordering....” para. 0041 and 0102), the first operations comprised in the first operation set (“...the memory layout conversion operations include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors. In other implementations, the memory layout conversion operations include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors. In yet other implementations, the memory layout conversion operations include a realignment operation that modifies the current memory layouts by changing the data alignment of the corresponding ones of the tensors. The compile time logic is further configured to insert, in the dataflow graph, new operation units that implement the memory layout conversion operations...” para. 0038); and
determining, by the processor based on a first operation identified each time, a feature scenario that is a generation scenarios of the [discontinuous] tensor and that is associated with the first operation (“…The dataflow graph has operation units that are configured to be producer operation units to produce tensors for execution of the application, and to be consumer operation units to consume the tensors for execution of the application. The compile time logic has access to the memory and is configured to process the dataflow graph to determine, for the tensors, expected producer memory layouts, expected consumer memory layouts, and current memory layouts. The expected producer memory layouts specify memory layouts required by the producer operation units that produce the tensors…” para. 0030. Note: scenarios is output tensor), and sequentially putting feature scenarios into a scenario information stack (“...tensor shape modifiers like transpose, and so on...” para. 0111).
While Koeplinger teaches the expected consumer memory layouts is different and conflict with the current memory layouts (0037 – 0038 and 0040), and provide mapping between elements of the tensors until the memory are matched and contiguous according to the memory layout and linear memory model (para. 0102) and apply memory layout functions like discontinuous (“...The memory layout functions 212 span all known operation types like non-linearities...” para. 0111), Koeplinger does not but Chang teaches the data is discontinuous (“...The inference engine circuit architecture 50 implements a “tensor” construct, in which data operation may be performed across a three-dimensional volume of non-contiguous data...” para. 0074),
See motivation for claim 1 above.
As to claim 3, Koeplinger modified by Chang teaches The method according to claim 2, Koeplinger teaches wherein the sequentially identifying, by the processor based on the preset priority, the first operations comprised in the first operation set comprise:
determining, by the processor, whether the metadata of the second data matches at least one piece of feature information of a to-be-identified first operation (“...detect the memory layout conflict when the expected consumer memory layouts are different from corresponding ones of the current memory layouts...” para. 0037 – 0038 and 0040), and based on the metadata of the second data matches matching the at least one piece of feature information of the to-be-identified first operation, determining, by the processor, the to-be-identified first operation, wherein the metadata of the second data comprises a shape (“...tensor shape...” para. 0105), [a stride], and a memory offset of the second data (“..An address is an offset which is used to denote the exact place of a memory chunk...” para. 0102) and (“..adding appropriate offsets and so...” para. 0205).
Koeplinger does not but Chang teaches a stride (“...tensor 144, given a start address 132, a depth 134 (for obtaining data in a “depth first” pattern), a stride...” para. 0074 and 0113).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Koeplinger by applying the teachings of Chang because Chang also teaches mapping memory tensor to be continuous (para 0030). Chang would provide more operations to apply during conversion process.
As to claim 4, Koeplinger modified by Chang teaches The method according to claim 1, Koeplinger teaches wherein the determining, by the processor, the second operation set that matches the first operation set comprises:
traversing, by the processor, an operator information library, wherein the operator information library comprises a plurality of tensor boost engine (TBE) operators (“...a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors....” para. 0038) and (“...tensor shape modifiers like transpose, ” para. 0111. Note: para. 0009 of the specification disclose operators comprise transpose, narrow and expand operator) and (“...the memory layout conversion operations 262 include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors ...” para. 0126) and (“...inserted in the dataflow graph...” para. 0130); and
for each first operation identified from the first operation set, determining, by the processor as a second operation that matches the first operation (“...detect the memory layout conflict when the expected consumer memory layouts are different from corresponding ones of the current memory layouts...” para. 0037 – 0038 and 0040), an operator that is in the operator information library and that has a same feature as the first operation, and sequentially putting second operations into an operator information stack (“...the memory layout conversion operations include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors. In other implementations, the memory layout conversion operations include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors. In yet other implementations, the memory layout conversion operations include a realignment operation that modifies the current memory layouts by changing the data alignment of the corresponding ones of the tensors. The compile time logic is further configured to insert, in the dataflow graph, new operation units that implement the memory layout conversion operations...” para. 0038).
As to claim 5, Koeplinger modified by Chang teaches The method according to claim 1, Koeplinger teaches wherein before the obtaining, by the computing core, the third data, the method further comprises:
delivering, by the processor, a conversion command to the computing core (“..using memory layout conversion operations...” para. 0038), wherein the conversion command comprises the second operation set (“...” para. ), and the conversion command indicates the computing core to calculate determine the first data based on the second operation set, to obtain the third data (“..the memory layout conversion operations 262 include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors....” para. 0126) and (“..generate an updated version of the dataflow graph...” para. 0038.
As to claim 6, Koeplinger modified by Chang teaches The method according to claim 1, Koeplinger teaches wherein the obtaining, by the computing core, the third data comprises:
constructing, by the processor, fourth data, wherein metadata of the fourth data is the same as the metadata of the first data, and the fourth data and the first data share a memory (“..generate an updated version of the dataflow graph...” para. 0038. Note: generate many version of data including fourth when the system iterates the process) and
sequentially performing, by the computing core, the second operations in the second operation set on the fourth data, to obtain the third data (“..the memory layout conversion operations 262 include a transpose operation that modifies the current memory layouts by changing the vector dimension of corresponding ones of the tensors....” para. 0126) and (“..generate an updated version of the dataflow graph...” para. 0038).
As to claim 7, Koeplinger modified by Chang teaches The method according to claim 1, Koeplinger teaches wherein the first operation set comprises a transpose operator, a narrow operator, and an expand operator “..generate an updated version of the dataflow graph...” para. 0038. Note: the second operation set is the same with the first operation set that iterates the processing of the conversion operations that comprises transpose operation, insert... util the current memory layouts and the expected memory layouts are matched/convergence as mapped the first operation set as taught para. 0034 – 0037 and 0040 - 0041) and (“....the memory layout conversion operations 262 include a shuffle operation that modifies the current memory layouts by changing the vector ordering of the corresponding ones of the tensors...” para. 0126) and (“....If no memory layout conflicts are detected, then the final memory layouts 274 are produced as output...” para. 0131).
As to claim 8, Koeplinger modified by Chang teaches the method according to claim 1, Koeplinger does not but Chang teaches wherein the data processing system further comprises a host and a chip, the processor is located in the host, and the computing core is located in the chip (“...The inference engine circuit architecture 50 and other DNN accelerators are composed of an on-chip memory...” para. 0150) and (“...The inference engine 50 has multiple compute clusters, each with an independent control core 275, maps buffer 105 and kernel (weights) buffer 125...” para. 0163) and (“... is possible to instantiate the inference engine circuit architecture 50 on different FPGA cards...” para. 0172).
See motivation for claim 1 above.
As to claim 9, Koeplinger modified by Chang teaches The method according to claim 8, Koeplinger does not but Chang teaches wherein the chip comprises at least one of a neural-network processing unit (NPU) (“...The inference engine circuit architecture 50 reaches 99.9% efficiency in a large majority of deep neural network layers...” para. 0121), a graphics processing unit (GPU), a tensor processing unit (TPU), or a data processing unit (DPU).
See motivation for claim 1 above.
As to claim 10, this is a data processing system claim of claim 1. See rejection for claim 1 above.
As to claims 11 – 18, these claims recite similar scope of claims 2 - 9. See rejection for claims 2 - 9 above.
As to claim 19, this is a hardware claim of claim 1. See rejection for claim 1 above.
As to claim 20, see rejection for claim 2 above.
Response to Arguments
Rejection of Claims 1-20 as being directed to an abstract idea (pages 9 – 10 of remark)
Applicant’s arguments, with respect to 101 rejection to abstract idea have been fully considered and are persuasive. The 101 rejection has been withdrawn.
Rejection of Claims 1-20 as being obvious over Koeplinger in view of Chang (pages 11 – 14 or remark).
Applicant's arguments, with respect to 103 rejection have been fully considered but they are not persuasive.
Applicant argued
“Applicant traverses the rejection of claims 1-20, including independent claims 1, 10 and 19, as being obvious over the teachings of Koeplinger in view of Chang. A prima facie case of obviousness cannot be established with regard to any one of the currently pending claims since the combined teachings of the cited Koeplinger and Chang references do not describe each recited element of any currently pending independent claim. Notably, neither reference describes at least Applicant's further recited feature combination of:
wherein the first data is a source tensor,
wherein the second data is a discontinuous tensor obtained by performing
the first operation set on the source tensor,
wherein the third data is a continuous tensor obtained by performing the
second operation set on the source tensor, and
wherein the first operation is a discontinuous framework operator.
Moreover, a proper reason cannot be established for one skilled in the art to modify Koeplinger's teachings, in view of Chang, in a way that would result in Applicant's claimed invention. Notably, none of the references demonstrates any awareness of a particularized problem that would provide a reason to modify Koeplinger (in view of Chang) in a way that resulted in Applicant's claimed invention” (page
In response,
Koeplinger teaches mapping tensor data during compiling process to produce
data alignment and the entire memory space is linear, sequential, and contiguous data ( figure 4 and associated text, especially para. 0102), wherein the mapping would apply multiple operation sets including stride, transpose and mapping memory address ( Chang teaches mapping memory address of non-contiguous tensor to be contiguous tensor (para 0030) and provides multiple operation sets while mapping processes and multiple operation sets including first and second sets such as stride and transpose (para. 0074, 0113, 0124, and 0202, etc.). While Koeplinger teaches all the operations mentioned above for the compiler produces continuous data, Koeplinger just silents on the data before conversion is non-continuous data or sensor. Chang also teaches mapping memory address of non-contiguous tensor to be contiguous tensor (para 0030) and provides multiple operation sets while mapping processes and multiple operation sets including first and second sets such as stride and transpose (para. 0074, 0113, 0124, and 0202, etc.) used for Koeplinger’s mapping processes. Chang would clearly provide the method of merging or mapping from non-contiguous data to contiguous to make data consistent to provide high performance for applications (para. 0010, 0113 and 0152). Therefore, Koeplinger and Chang teaches the same field of the invention and can be combined.
a. Applicant's Claimed Invention
“Applicant's claimed invention is directed to a particular arrangement of a processor component and (separate) computing core component to carry out a machine learning/AI data processing operation. In particular claim 1, provided in clean form below, recites:
A data processing method, wherein the method is performed by a data
processing system, the data processing system comprises a processor and a
computing core, and the method comprises:
obtaining, by the processor, metadata of first data and metadata of second
data,
wherein the second data is obtained by performing a first operation set on the first data,
wherein the first operation set comprises at least two first operations, and
wherein memory addresses associated with elements at adjacent positions in each row of the second data are discontinuous;
identifying, by the processor, the first operation set based on the metadata
of the second data, and determining each first operation in the first operation set;
determining, by the processor, a second operation set that matches the first
operation set, wherein a second operation that matches each first operation in the
first operation set exists in the second operation set; and
obtaining, by the computing core, third data based on the first data and the
second operation set, wherein memory addresses associated with elements at
adjacent positions in each row of the third data are continuous,
wherein the first data is a source tensor,
wherein the second data is a discontinuous tensor obtained by
performing the first operation set on the source tensor,
wherein the third data is a continuous tensor obtained by performing the
second operation set on the source tensor, and
wherein the first operation is a discontinuous framework operator.
(Emphasis added).
Thus, Applicant's claimed invention provides an improved physical computing arrangement/architecture that improves efficiency and performance of the machine learning/AI- related task of converting from discontinuous tensors to continuous tensors in carrying out data processing in a machine learning/AI processing environment.” (pages 11 – 12 of remark).
b. The Combined teachings of the cited references do not render the claimed invention
Applicant argued
“Applicant, in view of the current clarifying amendments to each of the independent claims, traverses the rejection of each of the independent claims 1, 10 and 19 that recite substantially the same combination of elements. As noted/discussed above, Applicant's claimed invention is directed to a specific physical data processing hardware arrangement including: (1) a processor, and (2) a computing core - as two separate physical components that perform specific aspects of the operation of converting from discontinuous tensors to continuous tensors in carrying out data processing in a machine learning/AI processing environment. In response to the previous grounds for rejection, Applicant has amended each of the independent claims to now recite:
wherein the first data is a source tensor,
wherein the second data is a discontinuous tensor obtained by
performing the first operation set on the source tensor,
wherein the third data is a continuous tensor obtained by performing the second operation set on the source tensor, and
wherein the first operation is a discontinuous framework operator.
(Emphasis added).
Applicant submits that the teachings of the previously cited Koeplinger and Chang references cannot be combined to render Applicant's claimed invention clarified by the now added feature combination provided above.
Koeplinger, upon which the Office action primarily relies, describes and is directed to compile time determination of tensor memory layouts, and the detection and resolution of conflicts between such layouts. The Office action, at page 15 does not identify "a computing core" (distinct from the "processor") executing the "obtaining...third data based on the first data and the second operation set...." For at least this reason the current grounds for rejection cannot stand - even without Applicant's current clarifications” (pages 12 – 13 first para. of remark).
In response,
In Koeplinger, the compiler which is claim the computing core, iterates the first and second process including transposing, modifying the current memory layout, realignment, etc. until no more conflict (para. 0037 – 0040). Note: the second operation set is the same with the first operation set that iterates the processing of the conversion operations that comprises transpose operation, insert... util the current memory layouts and the expected memory layouts are matched/convergence as mapped the first operation set as taught para. 0034 – 0037 and 0040 - 0041) and (“...If no memory layout conflicts are detected, then the final memory layouts 274 are produced as output...” para. 0131. Note: the output is the third data after the first and second operation sets described above process and produce final output which is claimed third data),
Applicant argued
“The Office action, at page 16, relies upon the further teachings of Chang to fill admits gaps in Koeplinger regarding Applicant's claimed "wherein memory addresses associated with elements at adjacent positions in each row of the second data are discontinuous." Emphasis added. However, the teachings of Chang, upon which the Office action relies, refer to "non- contiguous data". Applicant specifically requests clarification of how Chang's "non- contiguous data" corresponds to Applicant's recited "memory addresses associated with elements of adjacent position in each row of the second data are discontinuous."
Furthermore, the above-mentioned concerns relating to Applicant's currently rejected claim 1, are rendered moot by Applicant's further clarifying amendments to each of the independent claims to now recite:
wherein the first data is a source tensor,
wherein the second data is a discontinuous tensor obtained by
performing the first operation set on the source tensor,
wherein the third data is a continuous tensor obtained by performing the
second operation set on the source tensor, and
wherein the first operation is a discontinuous framework operator.
(Emphasis added).
Such features are directed to an improved interworking relationship between a "processor" and a "computing core" to provide a more efficient way of carrying out data processing in a machine learning/AI data processing environment.
For at least the above reasons, Applicant traverses the rejection of independent claims 1, 10 and 19 as being obvious over the combined teachings of Koeplinger and Chang.” (pages 13 – 14 of remark).
In response,
As responded above, Chang teaches the compiler, which is claimed computing core, during conversion process, maps data including data address of non-contiguous data to contiguous data (para. 0074, 0113, 0124, and 0202, etc.). Therefore, Chang teaches claimed invention and teaches the same field of the invention of Koeplinger that compile data to produce aligned data as responded above (para. 0037 – 0040).
Therefore, Koeplinger modified by Change teaches claims 1, 10 and 19.
c. The dependent claims are not rendered obvious by the cited references' teachings
Applicant argued
“Claims 2-9, 11-18 and 20 variously depend from independent claims 1, 10 and 19, respectively, and incorporate each of the elements discussed herein above that are neither described nor suggested in either Koeplinger or Chang. Applicant traverses the rejection of dependent claims 2-9, 11-18 and 20 for at least the reasons discussed above with reference to claims 1, 10 and 19.
Applicant reserves the right to provide additional reasons for distinguishing claims 2-9, 11-18 and 20 from the teachings of the prior art in the event that any further Office action recites new grounds for rejecting claims 2-9, 11-18 and 20, or any claim from which claims 2-9, 11-18 and 20 depend.” (page 14 of remark).
In response,
Dependent claims 2-9, 11-18 and 20 are rejected as they depend on their rejected independent claims.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Ware, (US PUB US 2024/0419758), discloses a tensor processing unit simultaneously execute, in each of a sequence of multiply-accumulate cycles, respective complex-data multiply operations using a shared complex data operand (title, abstract and figures 1 – 35).
Geng, (US PAT 11,789,709), discloses a compiler obtains a first intermediate representation IR including tensor and generate a second IR (title, abstract and figures 1 – 5).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached at 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUONG N HOANG/Examiner, Art Unit 2194
/KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
