CTNF 18/411,022 CTNF 71085 DETAILED ACTION This Office action responds to the patent application no. 18/411,022 filed on January 12, 2024. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Drawings 06-22 AIA The drawings are objected to because : FIG. 2D is missing a direction legend, has 2 PNs (second electrodes) where the second PN surround the first PN should be the DE, and the pattern used for CT2 (second cell contact plug) looks like the same pattern used for the conductive lines/gate for 122 and 132 in FIG. 1. FIG. 3A shows 133 above 120 . However, according to ¶ [0027] “a second pillar pad 133 disposed over a corresponding second semiconductor pillar 130 ” and ¶ [0026] “a first pillar pad 123 that is disposed over the first semiconductor pillar 120 ”. FIG. 22 shows the second hole-type recesses as both 33 and 34 . The second pillar pads 34 are not formed until FIG. 23. The numbers 40 and 41 on the far right point to the opening 45 in FIG. 29. The numbers 49 and 50 on the far right in FIG. 31 is not described in ¶ [000115]-[00117] . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 07-29 AIA The disclosure is objected to because of the following informalities: The description, “The first level-vertical conductive line 122 and the second level-vertical conductive line 132 may extend in a first direction D1 ” in paragraph (¶) [0022] does not match with the conductive line 122 and 132 extend in a second direction D2 as shown in FIGs. 2A and 2B. The description, “the flat portion of the second gate dielectric layer 131 may directly contact the barrier layer 111” in ¶ [0053] does not match with the flat portion of the gate dielectric layer 131 shown in FIG. 3B or the flat portion of the second gate dielectric layer 29 shown in FIG. 20. This second gate dielectric layer belongs to the second vertical transistor VT2 above the first vertical transistor VT1 and away from the barrier layer 111 due to the sandwiched VT1. It is unclear how the flat portion of the second gate dielectric layer 131 can directly contact the barrier layer 111. The description, “the second direction D3 shown in FIG. 1” in ¶ [0058] is the only used once in the Specification. All the other “the second direction” usages are associated with D2 and the other “D3” usages are associated with “the third direction” throughout the Specification. Shouldn’t the 21P of “the first oxide semiconductor pillars 21P” be 15P in ¶ [0071]? Shouldn’t the number 26 of “the second oxide semiconductor pillars 26” be 26P in ¶ [00121]? Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 7 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitations “IGZO, IZTO or ZTO” in line 2 are not spelled out and the limitation “an indium content greater than indium contents of gallium and zinc ” in lines 5-6 is not understood how “gallium and zinc” includes “indium contents”. According to ¶ [0043] in the specification, “Indium-rich IGZO may refer to a material having an indium content higher than gallium (Ga) and zinc (Zn) in IGZO”. Claim 10 recites the limitations “IGZO, IZTO or ZTO” in line 2 are not spelled out. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sung (US 2023/0164977) in view of Chung et al. (Chung hereinafter) (US 2011/0223731), further in view of Jang et al. (Jang hereinafter) (US 2023/0021017), and further in view of Sills et al. (Sill hereinafter) (US 2019/0259663) . Examiner assumed the above 112 rejections of Claims 7 and 10 are overcome. Regarding Claims 1-13: Sung (see FIGs. 1D, 1E, 4A, 4B, and others) teaches {1} a semiconductor device comprising: a bit line 110 ; a plurality of first semiconductor pillars 120 disposed over the bit line; {2} a first vertical gate 124 having a double structure disposed on both sidewalls of each of the first semiconductor pillars; {3} each of the first vertical gates has a tapered shape; {4} each of the first vertical gates includes an upper level portion 124U and a lower level portion 124L that is thinner than the upper level portion; {5} each of the first semiconductor pillars includes an oxide semiconductor material; {6} each of the first semiconductor pillars 120 includes: a lower interface layer 122 ; an upper interface layer 123 ; and a channel layer 121 between the lower interface layer and the upper interface layer; {7} the channel layer includes IGZO, IZTO or ZTO, and the lower and upper interface layers include indium-rich IGZO, and the indium-rich IGZO includes IGZO having an indium content greater than indium contents of gallium and zinc; {8} the bit line includes a metal material; {9} a substrate 101 disposed below the bit line, and a buffer layer 102 disposed between the bit line and the substrate; {10} each of the first semiconductor pillars includes IGZO, IZTO, ZTO, indium-rich IGZO, or a combination thereof; {11} each of the capacitors 130 includes a first electrode 132/ 37 , a dielectric layer 135/ 39 , and a second electrode 136/ 40 , wherein the first electrode includes a cylinder-shape electrode, and wherein a pillar-shaped electrode is disposed inside the cylinder-shape electrode; and {12} the capacitors further include a multi-layer level supporter supporting outer walls of the first electrodes. Sung (see ¶ [0031], [0032], [0033], [0035], [0039], [0041], [0046], [0049], [0050], [0094], [0098], [0099] ) teaches a) “Each oxide semiconductor pillar 120 may include a lower interface layer 122 coupled to the first conductive line 110, an upper interface layer 123 coupled to the memory cell 130, and an oxide semiconductor channel layer 121 disposed between the lower interface layer 122 and the upper interface layer 123”, b) “The semiconductor device 100 may include a Dynamic Random Access Memory (DRAM), and the first conductive lines 110 and the second conductive lines 124 may correspond to bit lines and word lines, respectively. The memory elements 130 may correspond to capacitors”; c) “The semiconductor device 100 may include an oxide semiconductor channel layer 121 , a bit line 110 disposed at a lower level than the oxide semiconductor layer 121, a capacitor 130 disposed at a higher level than the oxide semiconductor channel layer 121, a tapered vertical word line 124 disposed over a sidewall of the oxide semiconductor channel layer 121”; d) “The semiconductor device 100 may include a substrate 101, a buffer layer 102 over the substrate 101, a bit line over the buffer layer 102, a vertical channel transistor TR over the bit line 110, and a capacitor over the vertical channel transistor TR“; e) “The bit line 110 may include a metal -based material … a metal , ”; f) “the oxide semiconductor channel layer 121 may include … (IGZO), … (ITZO), … (ZTO), the lower interface layer 122 and the upper interface layer 123 may include indium-rich IGZO … a material with a higher indium content than gallium (Ga) and zinc (Zinc) in IGZO”; g) “A tapered vertical word line 124 having a double structure … may include a lower level portion 124L which is adjacent to the bit line 110 and an upper level portion 124U which is adjacent to the capacitor 130. The thickness of the lower level portion 124L … may be smaller than the thickness of the upper level portion 124U”; h) “the first contact plug 126 and the second contact plug 127 may include a metal , a metal nitride, or a combination thereof”; i) “the lower electrodes 132 may be supported by the supporters 133 and 134”; j) “the lower electrode 37 may include a hybrid structure of a titanium nitride cylinder and a polysilicon pillar ”; k) “a dielectric layer 39 may be formed over the lower electrode 37”, and l) “an upper electrode 40 may be formed over the dielectric layer 39”. However, Sung does not explicitly teach {1} a plurality of first cell contact plugs disposed between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first cell contact plugs; a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; and a plurality of capacitors respectively coupled to the second semiconductor pillars and the second cell contact plugs; {2} a second vertical gate having a double structure disposed on both sidewalls of each of the second semiconductor pillars; {3} each of the second vertical gates has a tapered shape; {4} each of the second vertical gates includes an upper level portion and a lower level portion that is thinner than the upper level portion; {5} each of the second semiconductor pillars includes an oxide semiconductor material; {6} each of the second semiconductor pillars includes: a lower interface layer; an upper interface layer; and a channel layer between the lower interface layer and the upper interface layer; {10} each of the second semiconductor pillars includes IGZO, IZTO, ZTO, indium-rich IGZO, or a combination thereof; and {13} the first and second cell contact plugs include a metal-based material. Chung (see FIG. 18B and ¶ [0042] and [0072]) teaches “a plurality of vertical channels 115 … a plurality of wordlines 190 including a plurality of wordline plug-ins 180 connecting a plurality of gate electrodes 165 disposed on sidewalls of the vertical channels 115” and “The wordline plug-in 180 may formed of material identical to or different from that of the gate electrode 165 … may be formed of doped polysilicon or a metal … A vertical height of the wordline plug-in 180 may be equal to or different from that of the gate electrode 165” Jang (see FIG. 7 and ¶ [0069]) teaches “the semiconductor structure 80 may form a circuit … the source or the drain of the first transistor T1 is connected with the bit line, the drain or the source of the second transistor T2 is connected with a capacitor … a circuit structure of 2T-1C … having two transistors and one capacitor, is formed, and may be used in the storage unit of a memory such as a Dynamic Random Access Memory (DRAM)”. Sills (see FIG. 6 and ¶ [0037]) teaches triple stacked vertical transistors with their own pillars 36 and “The structure 66 may be, for example a memory/storage cell” It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Sung to include the teaching of Chung to add metal contact plugs between the vertical channels in order to provide additional interconnection capability among the vertical transistors; to further include the teaching of Jang to vertically stack two tiers of the vertical transistors with identical structures and shapes and materials of the vertical channels and vertical gates being separated by contact plugs, with one capacitor as a memory cell to improve the performance and reliability with similar manufacturing processes; to further include the teaching of Sills to form its own semiconductor pillars for each tier of vertical transistors to have the freedom to electrically connect between two tiers of vertical transistors to meet circuitry design of 2T1C in each memory cell. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALICE W TANG/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814 Application/Control Number: 18/411,022 Page 2 Art Unit: 2814 Application/Control Number: 18/411,022 Page 3 Art Unit: 2814 Application/Control Number: 18/411,022 Page 4 Art Unit: 2814 Application/Control Number: 18/411,022 Page 5 Art Unit: 2814 Application/Control Number: 18/411,022 Page 6 Art Unit: 2814 Application/Control Number: 18/411,022 Page 7 Art Unit: 2814 Application/Control Number: 18/411,022 Page 8 Art Unit: 2814 Application/Control Number: 18/411,022 Page 9 Art Unit: 2814 Application/Control Number: 18/411,022 Page 10 Art Unit: 2814
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