DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 11/26/2025 has been entered. Applicant's remarks about the objection to the drawing are persuasive. Therefore, the previous objection to the drawing is withdrawn. Applicant's remarks about the objection to the claims have overcome claim objection previously set forth in the Non-Final Office Action mailed on 08/29/2025.
Response to Arguments
Applicant’s arguments with respect to claims 1-2 and 4-20 have been considered but are moot in light of the new grounds of rejection set forth below which was necessitated by applicant’s amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, 10, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US20080304204) in view of Ikeda (US20210335548).
With respect to claim 1, Suzuki teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) comprising: a multilayer body (see FIG. 1, element 10) including a plurality of dielectric layers (see FIG. 2, element 3) and a plurality of internal electrode layers (see FIG. 2, elements 1 and 2) laminated therein, a first main surface (see FIG. 1, Top surface) and a second main surface (see FIG. 1, Bottom surface) opposed to each other in a lamination direction (see FIG. 1 and FIG. 2, stacking direction), a first lateral surface (see FIG. 1, element 21) and a second lateral surface (see FIG. 1, element 22) opposed to each other in a width direction intersecting the lamination direction (see FIG. 1, along line B-B), and two end surfaces (see FIG. 1, elements 11 and 12) opposed to each other in a length direction intersecting the lamination direction and the width direction (see FIG. 1, along line A-A); and two external electrodes (see FIG. 1, elements 31 and 32) respectively provided on the two end surfaces of the multilayer body (see FIG. 1, elements 10, 11 and 12); wherein as seen in a plane including the width direction and the lamination direction in a middle portion in the length direction (see FIG. 1, along line A-A and B-B), among the plurality of internal electrode layers, end portions in the width direction of about 90% or more of internal electrode layers in a middle in the lamination direction are curved toward the second main surface (see FIG. 5 clearly shows the end portions of all of the internal electrode elements are curved toward the bottom of the multilayer ceramic capacitor body).
Suzuki does not expressly teach that the end portions in the width direction of the plurality of internal electrode layers are each aligned to be positioned in a range of about 3 µm in the lamination direction.
Ikeda, on the other hand, teaches and the end portions in the width direction of the plurality of internal electrode layers are each aligned to be positioned in a range of about 3 µm in the lamination direction (see paragraph 39).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki and Ikeda to form the claimed invention in order to improve reliability and reduce the stress on the multilayer ceramic capacitor (see paragraph 49).
With respect of claim 2, the combined teachings of Suzuki and Ikeda teach that a variation in dimensions in the width direction of the plurality of internal electrode layers is within about ±5% in standard deviation (see Suzuki paragraph 114, the reference implicitly discloses a constant width for the internal electrodes, such that the standard deviation would approach zero, and thus, is within 5% standard deviation).
With respect of claim 4, the combined teachings of Suzuki and Ikeda teach that among the plurality of internal electrode layers, about 90% or more of the internal electrode layers in the middle in the lamination direction each including the end portions in the width direction curved toward the second main surface include an internal electrode layer defining an outermost layer adjacent to the second main surface (see Suzuki FIG. 5 clearly shows the end portions of all of the internal electrode elements are curved toward the bottom of the multilayer ceramic capacitor body).
With respect of claim 5, the combined teachings of Suzuki and Ikeda teach that the multilayer body (see Suzuki FIG. 1, element 10) includes a first side margin portion (see Suzuki FIG. 3, element G.sub.s) provided between the first lateral surface and ends of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) adjacent to the first lateral surface (see Suzuki FIG. 3, element 21), and a second side margin portion (see Suzuki FIG. 3, element G.sub.s) provided between the second lateral surface and ends of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) adjacent to the second lateral surface (see Suzuki FIG. 3, element 21); and each of the first side margin portion and the second side margin portion includes a plurality of dielectric layers provided in the width direction (see Suzuki FIG. 3, element 3).
With respect of claim 10, the combined teachings of Suzuki and Ikeda teach that the multilayer body (see Suzuki FIG. 1, element 10) includes a first side margin portion (see Suzuki FIG. 3, element G.sub.s) provided between the first lateral surface and ends of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) adjacent to the first lateral surface (see Suzuki FIG. 3, element 21), and a second side margin portion (see Suzuki FIG. 3, element G.sub.s) provided between the second lateral surface and ends of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) adjacent to the second lateral surface (see Suzuki FIG. 3, element 22); and each of the first side margin portion and the second side margin portion includes one dielectric layer provided in the width direction (see Suzuki FIG. 3, element 3).
With respect of claim 15, the combined teachings of Suzuki and Ikeda teach that each of the plurality of dielectric layers has a thickness of about 0.3 µm or more and about 0.5 µm or less (see Ikeda paragraph 34, noting the dielectric layer 14 preferably has a thickness of about 0.5 μm or less).
With respect of claim 16, the combined teachings of Suzuki and Ikeda teach that the plurality of internal electrode layers include a plurality of first internal electrode layers (see Suzuki FIG. 2, element 1) and a plurality of second internal electrode layers (see Suzuki FIG. 2, element 2) which oppose one another; and at least some of both of the plurality of first internal electrode layers and the plurality of second internal electrode layers include the end portions which are curved toward the second main surface (see Suzuki FIG. 5 clearly shows the end portions of all of the internal electrode elements are curved toward the bottom of the multilayer ceramic capacitor body).
With respect of claim 17, the combined teachings of Suzuki and Ikeda teach that the multilayer body (see Suzuki FIG. 1, element 10) includes a first side margin portion (see Suzuki FIG. 3, element G.sub.s) provided between the first lateral surface and ends of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) adjacent to the first lateral surface (see Suzuki FIG. 3, element 21), and a second side margin portion (see Suzuki FIG. 3, element G.sub.s) provided between the second lateral surface and ends of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) adjacent to the second lateral surface (see Suzuki FIG. 3, element 22); and each of the first side margin portion and the second side margin portion includes a plurality of dielectric layers provided in the width direction (see Suzuki FIG. 3, element 3).
With respect of claim 18, the combined teachings of Suzuki and Ikeda teach that the end portions which are curved toward the second main surface (see Suzuki FIG. 5 clearly shows the end portions of all of the internal electrode elements are curved toward the bottom of the multilayer ceramic capacitor body) are adjacent to one of the first side margin portion and the second side margin portion (see Suzuki FIG. 3, element G.sub.s).
With respect of claim 19, the combined teachings of Suzuki and Ikeda teach that central portions of the plurality of internal electrode layers (see Suzuki FIG. 3, elements 1 and 2) are located in an electrode counter portion of the multilayer body (see Suzuki FIG. 3, element 10); and the first side margin portion and the second side margin portion sandwich the electrode counter portion (see Suzuki FIG. 3, element G.sub.s, elements 1, 2 and 3).
With respect of claim 20, the combined teachings of Suzuki and Ikeda teach that the end portions are located in both the first and second side margin portions and also the electrode counter portion (see Suzuki FIG. 3, element G.sub.s).
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki and Ikeda, as applied to claims 5 and 10 above, and further in view of Fukunaga et al. (JP2018174336).
With respect of claim 6, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 5.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, an average particle size of dielectric grains included in an outermost layer of the plurality of dielectric layers adjacent to the first lateral surface is larger than an average particle size of dielectric grains included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers; and in the second side margin portion, an average particle size of dielectric grains included in an outermost layer of the plurality of dielectric layer adjacent to the second lateral surface is larger than an average particle size of dielectric grains included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers.
Fukunaga ‘336, on the other hand, teaches in the first side margin portion (see FIG. 3, element 32), an average particle size of dielectric grains included in an outermost layer (see FIG. 3, element 32a) of the plurality of dielectric layers adjacent to the first lateral surface is larger than an average particle size of dielectric grains included in an innermost layer (see FIG. 3, element 32b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers (see paragraph 25, machine translated version, noting the particle size in 32b and 34b is smaller than 32a and 34a); and in the second side margin portion (see FIG. 3, element 34), an average particle size of dielectric grains included in an outermost layer (see FIG. 3, element 34a) of the plurality of dielectric layer adjacent to the second lateral surface is larger than an average particle size of dielectric grains included in an innermost layer (see FIG. 3, element 34b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers (see paragraph 25, machine translated version, noting the particle size in 32b and 34b is smaller than 32a and 34a).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Fukunaga ‘336 to form the claimed invention in order to improve the reliability of the multilayer ceramic capacitor having the side margin portion (see Fukunaga ‘336, paragraph 28, machine translated version).
With respect of claim 11, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 10.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the first lateral surface is larger than an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers; and in the second side margin portion, an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the second lateral surface is larger than an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers.
Fukunaga ‘336, on the other hand, teaches in the first side margin portion (see FIG. 3, element 32), an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the first lateral surface (see FIG. 3, element 32a) is larger than an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see paragraph 25, machine translated version, noting the particle size in 32b and 34b is smaller than 32a and 34a);
and in the second side margin portion (see FIG. 3, element 34), an average particle size
of dielectric grains included in a region of the dielectric layer adjacent to the second lateral surface (see FIG. 3, element 34a) is larger than an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see paragraph 25, machine translated version, noting the particle size in 32b and 34b is smaller than 32a and 34a).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Fukunaga to form the claimed invention in order to improve the reliability of the multilayer ceramic capacitor having the side margin portion (see Fukunaga ‘336, paragraph 28, machine translated version).
Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki and Ikeda, as applied to claims 5 and 10 above, and further in view of Fukunaga et al. (US20150340155).
With respect of claim 9, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 5.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, voids included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers are larger in number than void included in an outermost layer of the plurality of dielectric layers adjacent to the first lateral surface; and in the second side margin portion, voids included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers are larger in number than voids included in an outermost layer of the plurality of dielectric layers adjacent to the second lateral surface.
Fukunaga ‘155, on the other hand, teaches in the first side margin portion (see FIG. 3, element 32), voids included in an innermost layer (see FIG. 3, element 32b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers are larger in number than void included in an outermost layer (see FIG. 3, element 32a) of the plurality of dielectric layers adjacent to the first lateral surface (see paragraph 41, noting outer portions 32a and 34a contains fewer pores than inner portion 32b and 34b); and in the second side margin portion (see FIG. 3, element 34), voids included in an innermost layer (see FIG. 3, element 34b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers are larger in number than voids included in an outermost layer (see FIG. 3, element 34a) of the plurality of dielectric layers adjacent to the second lateral surface (see paragraph 41, noting outer portions 32a and 34a contains fewer pores than inner portion 32b and 34b).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Fukunaga ‘155 to form the claimed invention in order to improve in moisture resistance of the multilayer ceramic capacitor (see Fukunaga ‘155, paragraph 51).
With respect of claim 14, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 10.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers are larger in number than voids included in a region of the dielectric layer adjacent to the first lateral surface; and in the second side margin portion, voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers are larger in number than voids included in a region of the dielectric layer adjacent to the second lateral surface.
Fukunaga ‘155, on the other hand, teaches in the first side margin portion (see FIG. 3, element 32), voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see FIG. 3, element 32b) are larger in number than voids included in a region of the dielectric layer adjacent to the first lateral surface (see paragraph 41, noting outer portions 32a and 34a contains fewer pores than inner portion 32b and 34b); and in the second side margin portion (see FIG. 3, element 34), voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see FIG. 3, element 34b) are larger in number than voids included in a region of the dielectric layer adjacent to the second lateral surface (see paragraph 41, noting outer portions 32a and 34a contains fewer pores than inner portion 32b and 34b).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Fukunaga ‘155 to form the claimed invention in order to improve in moisture resistance of the multilayer ceramic capacitor (see Fukunaga ‘155, paragraph 51).
Claims 7-8 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki and Ikeda, as applied to claims 5 and 10 above, and further in view of Park et al. (US20210005382).
With respect of claim 7, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 5.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, an average particle size of dielectric grains included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers is larger than an average particle size of dielectric grains included in an outermost layer of the plurality of dielectric layers adjacent to the first lateral surface; and in the second side margin portion, an average particle size of dielectric grains included in an innermost layer of the
plurality of dielectric layers adjacent to the plurality of internal electrode layers is larger than an average particle size of dielectric grains included in an outermost layer of the
plurality of dielectric layers adjacent to the second lateral surface.
Park, on the other hand, teaches in the first side margin portion (see FIG. 4, element 112), an average particle size of dielectric grains included in an innermost layer (see FIG. 4, element 112b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers is larger than an average particle size of dielectric grains included in an outermost layer (see FIG. 4, element 112a) of the plurality of dielectric layers adjacent to the first lateral surface (see paragraph 84, noting second regions 112b and 113b particle size is larger than first regions 112a and 113a); and in the second side margin portion (see FIG. 4, element 113), an average particle size of dielectric grains included in an innermost layer (see FIG. 4, element 113b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers is larger than an average particle size of dielectric grains included in an outermost layer (see FIG. 4, element 113a) of the plurality of dielectric layers adjacent to the second lateral surface (see paragraph 84, noting second regions 112b and 113b particle size is larger than first regions 112a and 113a).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Park to form the claimed invention in order to improve the moisture resistance of the multilayer ceramic capacitor (see paragraph 89).
With respect of claim 8, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 5.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, voids included in an outermost layer of the plurality of dielectric layers adjacent to the first lateral surface are larger in number than voids included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers; and in the second side margin portion, voids included in an outermost layer of the plurality of dielectric layers adjacent to the second lateral surface are larger in number than voids included in an innermost layer of the plurality of dielectric layers adjacent to the plurality of internal electrode layers.
Park, on the other hand, teaches in the first side margin portion (see FIG. 4, element 112), voids included in an outermost layer (see FIG. 4, element 112a) of the plurality of dielectric layers adjacent to the first lateral surface are larger in number than voids included in an innermost layer (see FIG. 4, element 112b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers (see paragraph 74, noting pores per unit area in the second regions 112b and 113b is less than in the first regions 112a and 113a); and in the second side margin portion (see FIG. 4, element 113), voids included in an outermost layer (see FIG. 4, element 113a) of the plurality of dielectric layers adjacent to the second lateral surface are larger in number than voids included in an innermost layer (see FIG. 4, element 113b) of the plurality of dielectric layers adjacent to the plurality of internal electrode layers (see paragraph 74, noting pores per unit area in the second regions 112b and 113b is less than in the first regions 112a and 113a).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Park to form the claimed invention in order to improve the moisture resistance of the multilayer ceramic capacitor (see paragraph 89).
With respect of claim 12, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 10.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers is larger than an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the first lateral surface; and in the second side margin portion, an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers is larger than an average particle size of dielectric grains include in a region of the dielectric layer adjacent to the second lateral surface.
Park, on the other hand, teaches in the first side margin portion (see FIG. 4, element 112), an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see FIG. 4, element 112b) is larger than an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the first lateral surface (see paragraph 84, noting second regions 112b and 113b particle size is larger than first regions 112a and 113a); and in the second side margin portion (see FIG. 4, element 113), an average particle size of dielectric grains included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see FIG. 4, element 113b) is larger than an average particle size of dielectric grains include in a region of the dielectric layer adjacent to the second lateral surface (see paragraph 84, noting second regions 112b and 113b particle size is larger than first regions 112a and 113a).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Park to form the claimed invention in order to improve the moisture resistance of the multilayer ceramic capacitor (see paragraph 89).
With respect of claim 13, Suzuki and Ikeda teaches a multilayer ceramic capacitor (see FIG. 1, paragraph 46) of claim 10.
Suzuki and Ikeda do not expressly teach that in the first side margin portion, voids included in a region of the dielectric layer adjacent to the first lateral surface are larger in number than voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers; and in the second side margin portion, voids included in a region of the dielectric layer adjacent to the second lateral surface are larger in number than voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers.
Park, on the other hand, teaches in the first side margin portion (see FIG. 4, element 112), voids included in a region of the dielectric layer adjacent to the first lateral surface (see FIG. 4, element 112a) are larger in number than voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see paragraph 74, noting pores per unit area in the second regions 112b and 113b is less than in the first regions 112a and 113a); and in the second side margin portion (see FIG. 4, element 113), voids included in a region of the dielectric layer adjacent to the second lateral surface (see FIG. 4, element 113a) are larger in number than voids included in a region of the dielectric layer adjacent to the plurality of internal electrode layers (see paragraph 74, noting pores per unit area in the second regions 112b and 113b is less than in the first regions 112a and 113a).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Suzuki, Ikeda and Park to form the claimed invention in order to improve the moisture resistance of the multilayer ceramic capacitor (see paragraph 89).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESTHER N LIAN whose telephone number is (571)272-5726. The examiner can normally be reached Monday-Friday 8:00 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ESTHER N LIAN/Examiner, Art Unit 2848
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2848