Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18411451 filed on 01/12/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Election/Restrictions
Applicants’ election with traverse of Group I, claims 1-10, in the reply filed on 06/29/2026 is acknowledged.
The traversal is on the ground(s) that “One of ordinary skill in the art of semiconductor manufacturing would understand that the order of forming the gate contact metallization and the first field plate would have almost no effect on the manufacturing process used. This minor change in the order of deposition does not constitute a materially different process. Thus, the two groups do not meet the requirement that the product as claimed can be made by another materially different process”.
The examiner would like to note that the sequence of forming the gate contact metallization and the first field plate does constitute a materially different process as the order of layers require different conditions in method of forming such as deposition and removing of conductive materials and insulating materials.
Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US 2020/0350399 A1).
Regarding claim 1, Wong et al. teach a semiconductor device comprising:
a substrate (fig. 1, elements 102-106 [0026] [0034] [0045]) made of a
semiconductor material [0027];
a gate structure (fig. 1, elements 108, 110 & 112 [0026] [0030] [0031]) placed on the substrate (fig. 1, elements 108, 110 and 112 are disposed on element 102-106 [0028]);
a passivation layer (fig. 1, element 114 [0040]) placed on the substrate and on a
portion of the gate structure (fig. 1, element 114 placed on a portion of element 108, 110 and 112);
a sealing dielectric layer (fig. 1, elements 116 & 152 [0042] [0046], paragraph [0088] discloses that a dielectric layer can be made of silicon nitride. Accordingly, it would have been obvious to one of ordinally skill in the art to select silicon nitride as the sealing dielectric material for elements 116 and 152) placed on the passivation layer,
wherein the sealing dielectric layer is thicker than the passivation layer (fig. 1 elements 116 & 152 together is thicker than element 114);
a first field plate (fig. 1, element 122 [0047]) placed on a portion of the sealing dielectric layer (fig. 1, element 122 placed on a portion of elements 116 &152);
a dielectric layer (fig. 1, element 154 [0046]) placed on the first field plate and on
the sealing dielectric layer (fig. 1, element 154 is placed on element 122 and on elements 116 & 152);
a second field plate (fig. 1, element 124 [0047]) placed on a portion of the dielectric layer (fig. 1, element 124 placed on a portion of upper portion of element 154);
and a source contact metallization (fig. 1, elements 118 and 170 [0043] [0053]) and
a drain contact metallization (fig. 1, elements 120 and 170 [0043] [0053]).
Regarding claim 3, Wong et al. teach the semiconductor device, wherein
the source contact metallization and the drain contact metallization formed on
corresponding portions of the substrate (fig. 1, elements 118 and 120 are formed through element 114 to contact element 106 [0045]) in corresponding voids in the passivation layer, the sealing dielectric layer, and the dielectric layer (fig. 1, the source contact and drain contact holes are formed by etching elements 114 &116 [0096] and interconnect structure element 170 running though elements 152 & 154 [0109]).
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Regarding claim 4, Wong et al. teach the semiconductor device, wherein
the dielectric layer (fig. 1, element 154 [0046]) comprises a first dielectric sub-layer (see annotated figure above, the bottom portion below the segment shown above is considered the first dielectric sub-layer) and a second dielectric sub-layer (see annotated figure above, the top portion above the segment shown above is considered the second dielectric sub-layer).
Regarding claim 5, Wong et al. teach the semiconductor device, wherein
the first dielectric sub-layer (see annotated figure above, the bottom portion below the segment shown above is considered the first dielectric sub-layer) is partially overlapped by the source and drain contact metallizations (see annotated figure above, the first dielectric sub-layer partially overlapped by the T-shaped horizontal portion of element 118 and element 120 and both interconnect element 170).
Regarding claim 6, Wong et al. teach the semiconductor device, wherein
the second dielectric sub-layer (see annotated figure above, the top portion above the segment shown above is considered the second dielectric sub-layer) overlaps the source and drain contact metallizations (see annotated figure above, the second dielectric sub-layer partially overlapped by the T-shaped horizontal portion of element 118 and element 120 and both interconnect element 170).
Regarding claim 7, Wong et al. teach the semiconductor device, further comprising
a gate contact dielectric layer (fig. 1, element 156 [0046]) placed on the second field plate (fig. 1, element 124 [0047]) and on a portion of the dielectric layer (fig. 1, element 156 placed on element 154 [0046]).
Regarding claim 9, Wong et al. teach the semiconductor device, wherein the gate structure is made of gallium nitride (GaN) [0029];
and wherein the semiconductor device comprises a GaN high electron mobility transistor [0004] [0054].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US 2020/0350399 A1) in view of Liao et al. (US 2022/0375926 A1).
Regarding claim 2, Wong et al. teach all the limitations as discussed above.
Wong et al. do not explicitly teach the sealing dielectric layer and the dielectric layer are made of a nitride or an oxide material.
However, Liao et al. is a pertinent art which discloses a GaN HEMT comprising stack of dielectric layer (fig. 3, elements 351-358 [0026] [0057]) on which first field plate and second field plate are formed (fig. 3, elements 381 & 382 [0026]), wherein the passivation layer may serve as an interlayer dielectric material may include a nitride such as silicon nitride and also may include oxide such as silicon oxide materials [0057].
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the semiconductor device of Wong et al. to form the dielectric layer of a nitride or an oxide material as taught by Liao et al. in order to provide the inter layer dielectric functions of those layer with a material recognized in the art as suitable for those functions in GaN HEMT [0057]. The selection of a known material based on its suitability for its intended use is prima facie obvious.
Regarding claim 8, Wong et al. teach all the limitations as discussed above. Wong et al. further teach the semiconductor device, comprising
a gate contact metallization (fig. 1 of Wong et al. elements 110 & 112 [0026]) placed on the gate structure (fig. 1 of Wong et al. elements 108, 110 & 112 [0026] [0030] [0031]) in the gate contact dielectric layer, the dielectric layer, the sealing dielectric layer, and the passivation layer.
Wong et al. do not explicitly teach a gate contact metallization placed on the gate structure in a void in the gate contact dielectric layer, the dielectric layer, the sealing dielectric layer, and the passivation layer.
However, Liao et al. is a pertinent art which teaches a gate contact metallization (fig. 3 of Liao et al. element 375 [0034]) placed on the gate structure (fig. 3 of Liao et al. elements 362 and 363 [0026] [0040]) in a void of four stacked dielectric layers (fig. 3 of Liao et al. element 375 disposed on elements 351, 352, 353 and 354 [0026] [0039] wherein element 375 may function as gate or a gate terminal of the transistor T1 [0040]). Furthermore, Liao et al. discloses that all four passivation layers are formed before the void is opened [0072] and all four passivation layers may serve as an interlayer dielectric layer and may include the same materials or different materials [0057].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Wong et al. so that the gate contact metallization is placed on the gate structure in a void in the four gate contact passivation layers as taught by Liao et al. in order to provide the conductive structure may serve as a through via electrically connecting the conductive structure to the outside [0045].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (US 2020/0350399 A1) in view of Iucolano et al. (US 2021/0175350 A1).
Regarding claim 10, Wong et al. teach all the limitations as discussed above.
Wong et al. do not explicitly teach the second field plate partially contacts the first
field plate through a further void in the dielectric layer.
However, Iucolano et al. is a pertinent art which discloses a HEMT, wherein the second field plate (fig. 13, element 85 [0047]) contact the first filed plate (fig. 13, element 84” [0107]) through a further void (fig. 13, field plate connecting through opening element 89 [0107]) in the dielectric layer (fig. 13, element 62 [0045] [0107] the first field plate and the same metal layer that forms the second field plate fills that void. The field plate connection via electrically connects the first field plate to the second field plate region [0101] [0107]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Wong et al. to establish partial contact between the second field plate and the first field plate through a void in the dielectric layer as taught by Iucolano et al. in order to connect the first field plate to the source metallization through the second field plate to have the effect of modifying the existing electric field and in particular making it more uniform during the operation of the HEMT transistor [0052] [0106].
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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