Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 27 April 2026.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, and 4-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over O (US PG PUB No. 2020/0294575) in view of Yu (US PG PUB No. 2022/0036929).
As per claim 1, O discloses a processing-in-memory (PIM) system (see O FIG 1: 200) comprising:
a plurality of PIM controllers (see e.g., O FIG 5: PE Controller and [0062]) and a plurality of PIM devices (see e.g., O FIG 5: BG0 and [0060]), the plurality of PIM controllers coupled to the host through a plurality of channels (see e.g., O FIG 5: CH1 and [0059]), and a plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels (see e.g., FIG 8: 500 and [0077]).
However, O does not expressly disclose but in the same field of endeavor Yu discloses
a host (see e.g., Yu FIG 2: 210) configured to receive an address including an identification (ID) from outside the PIM system (see e.g., Yu FIG 1: 110 and [0021]), the identification identifying a request received from outside the PIM system (see Yu FIG 2: 132 and [0045]), and to output an address signal including a channel address (see Yu FIG 4: Channel Address and [0082]);
[Yu discloses internal processing requests and general processing requests identified based on SID (see Yu FIG 6 and [0034]-[0035]).]
wherein the host including an ID-channel mapper configured to generate the channel address corresponding to the identification (see Yu FIG 4: Channel Address and [0082]); and
It would have been obvious before the effective filing date of the invention to modify O to implement a host to receive an identification and output a channel address as taught by Yu.
The suggestion/motivation for doing so would have been for the benefit of improving internal processing (see Yu [0005] and [0045]).
Therefore it would have been obvious before the effective filing date of the invention to modify O to receive an address including identification and output an address signal including a channel address as taught by Yu for the benefit of enabling outside access to arrive at the invention as specified in the claims.
As per claim 4, the PIM system of claim 1,
further comprising an interconnection bus coupled between the host and the plurality of PIM controllers (see O FIG 5: Databus).
As per claim 5, the PIM system of claim 4,
wherein the interconnection bus includes a plurality of channel terminals respectively coupled to the plurality of channels (see O FIG 2: 231 and [0045]).
As per claim 6, the PIM system of claim 5,
wherein the plurality of PIM controllers are respectively coupled to the plurality of channel terminals through the plurality of channels (see O FIG 5: PE 0, PE1 and [0045]).
As per claim 7, the PIM system of claim 6,
wherein the plurality of PIM devices are respectively coupled to the plurality of PIM controllers through the plurality of channels (see O FIG 5: CH1, CH2).
As per claim 8, the PIM system of claim 1,
wherein the plurality of PIM devices are configured to store arithmetic data used in the same type of arithmetic operation, and to perform the same type of arithmetic operation using the arithmetic data (see O [0033]: “neural network operations”).
As per claim 9, the PIM system of claim 1,
wherein the plurality of PIM devices are configured to store arithmetic data used in different types of arithmetic operations, and to perform the different types of arithmetic operations using the arithmetic data (see O [0084]: “data and a weight”).
As per claim 10, the PIM system of claim 1,
wherein among the plurality of PIM devices, a first PIM device coupled to a first PIM controller among the plurality of PIM controllers through a first channel is configured to perform an arithmetic operation in response to a command and address signal transmitted from the first PIM controller (see O [0034]).
As per claim 11, the PIM system of claim 1,
wherein the identification is received from a software domain (see Yu [0021]).
[The address is taken as an identification as recited in the claims, where the issuer is taken as a software domain to the extent a memory request is issued in response to executing software instructions.]
Claims 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over O (US PG PUB No. 2020/0294575) in view of Yu (US PG PUB No. 2022/0036929) as applied to claim 1 above and further in view of Madruga (US PG PUB No. 2009/0150575).
As per claim 3, O discloses the PIM system of claim 1,
However, O does not expressly disclose but in the same field of endeavor Madruga discloses
wherein the ID-channel mapper includes a table in which the identification and the plurality of channels are mapped to each other (see Madruga FIG 3: 300 and [0035]).
It would have been obvious before the effective filing date of the invention to modify O in view of Yu to further implement a channel bitmap as taught by Madruga.
The suggestion/motivation for doing so would have been for the benefit of a dynamic allocation (See Madruga [0006]).
Therefore it would have been obvious before the effective filing date of the invention to modify O in view of Yu to further include a table as taught by Madruga for the benefit of dynamic allocation to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
1st ARGUMENT:
However, the presently claimed invention requires a fundamentally different operation at the host side. In particular, claim 1 recites "a host configured to receive an address including an identification (ID) from outside the PIM system, the identification identifying a request received from outside the PIM system, and to output an address signal including a channel address, wherein the host includes an ID-channel mapper configured to generate the channel address corresponding to the identification." As illustrated in Applicant's FIG. 74, the host 7100 receives an address from a software domain 6000, where the address includes an identification (ID) corresponding to a request originating outside the PIM system (see, e.g., FIG. 74; see also, e.g., specification describing receipt of command/address information from an external host in paragraph 25-27). The host 7100 further includes an ID-channel mapper 7110 that generates a channel address corresponding to the identification, for example using a mapping relationship between IDs and channels. Thus, Applicant's system performs a host-side mapping from an externally received request identifier to a channel address, prior to transmitting the address signal to the PIM controllers and devices. Stated differently, the claimed invention performs an "identification, mapping, channel address" operation at the host, rather than an "address, decoding, channel selection" operation as in the prior art.
The specification further supports this operation by explaining that the host and memory controller cooperate to control operations of the memory device based on received command/address information (see, e.g., paragraphs 25-27), and that channel-based access is performed through structured channel interconnections (see, e.g., paragraphs 59-62). However, unlike O, Applicant introduces an additional abstraction layer in which an identification identifying an external request is first received and then translated into a channel address via the ID-channel mapper, thereby enabling request-based routing across multiple channels.
The claims do not specify a host side as argued because the claims do not specify the host is for example a host as labeled in O. As per FIG 74 the host is disclosed as part of the PIM system (see Specification [0319]).
Paragraph [0025]-[0027] of the Specification describe FIG. 30-33 and do not appear to disclose the subject matter Applicant is suggesting. It is unclear if Applicant is pointing to a different section of the Specification.
2nd ARGUMENT:
Turning to Yu, the Examiner relies on Yu to teach the claimed "identification." However, Yu does not disclose the claimed feature. As shown in Yu FIG. 4, channels are labeled using identifiers such as CH1a-CH8a, and these channels are selected based on a channel address (see also paragraph 82). Specifically, Yu explains that channels CH1a to CH8a may be addressed using a multi-bit channel address, and that selection among channels is determined by decoding bits of the channel address (e.g., the most significant bit distinguishing between subsets of channels) (see paragraph 82). For example, Yu explicitly discloses that when the most significant bit of the channel address is "0," a first subset of channels is selected, and when the most significant bit is "1," a different subset of channels is selected (see paragraph 82), thereby confirming that channel selection is performed through decoding of address bits rather than through any mapping from an external identification. Similarly, Yu describes that banks are selected based on bank address bits, again using conventional decoding (see paragraph 85). Thus, Yu clearly teaches that address bits are decoded to select predefined channels or banks.
Importantly, the "channel IDs" in Yu are not "identifications" as claimed. They do
not represent identifiers of requests received from outside the PIM system. Rather, they are fixed labels corresponding to physical channels within the memory architecture. Yu does not disclose receiving an identification associated with a request, nor does Yu disclose any structure or functionality for mapping such an identification to a channel address. Instead, Yu follows the same conventional approach as O, in which an address is decoded to directly select a channel.
Yu discloses an address received from outside the PIM system (see e.g., FIG 2: 132) is decoded to identify a channel, where the memory is partitioned between Normal and PIM region (see [0083]: “The most significant bit of the channel address is a specific address that divides the memory cell array 121 of the memory device 120 a into the PIM region 122 and the normal memory region 124 and may be stored in the control register 116 of the memory controller 112.”). The address received from outside the PIM system to access the normal memory region encompasses an identification as recited in the claims because the normal memory region is accessed by outside the PIM system.
3rd ARGUMENT:
In contrast, the present claims, particularly as amended, require that the identification identifies a request received from outside the PIM system, and that the host generates a channel address corresponding to that identification using an ID- channel mapper. This establishes a clear distinction between (i) Applicant's identification-based mapping mechanism and (ii) Yu's conventional address decoding scheme. The Office's interpretation effectively equates Yu's channel labels or address bits with the claimed identification, which improperly reads out the requirement that the identification is associated with an external request and is used as an input to a mapping function. In other words, Yu discloses only channel selection based on a channel address, whereas the present claims require generation of the channel address itself based on an external request identification.
The claims do not specify a host as argued as noted in response to the first argument. As per FIG 6 the specific address is an identification to the extent required by the claims because the specific address determines weather to perform the data transaction using Normal Memory region (see Yu FIG 6: S651 and [0035]). Yu discloses a normal mode where the memory controller performs general operations (see Yu [0033]), and an internal mode where the memory controller performs internal operations (see Yu [0034]). Yu discloses the limitation to the extent Yu discloses a specific address determines the region and by relation the channel.
4th ARGUMENT:
Furthermore, there is no teaching or suggestion in O or Yu to modify the conventional address decoding approach of O to incorporate Applicant's identification- based mapping mechanism. Implementing such functionality would require introducing a host-side mapping layer that converts external request identifiers into channel addresses prior to transmission, an architectural change that is neither disclosed nor suggested by the cited references. The combination proposed by the Examiner would therefore require impermissible hindsight reconstruction.
Examiner notes the claims do not specify a host-side mapping layer as argued. FIG 74 discloses a PIM system (FIG 74: 7000) comprising a ‘host’ (see FIG 74: 7100). The claims do not specify if the host is external to the PIM system as apparently argued. The argument is unclear because the claims do not specify ‘prior to transmission’ and the remarks do not specify the target of the transmission.
Examiner maintains a person of ordinary skill in the art would have found it obvious before the effective filing date of the invention to implement a mode selection operation as taught by Yu for the benefit of improved internal processing.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
Prosecution Insights