Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 6 January 2026.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, and 4-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over O (US PG PUB No. 2020/0294575) in view of Yu (US PG PUB No. 2022/0036929).
As per claim 1, O discloses a processing-in-memory (PIM) system (see O FIG 1: 200) comprising:
a plurality of PIM controllers (see e.g., O FIG 5: PE Controller and [0062]) and a plurality of PIM devices (see e.g., O FIG 5: BG0 and [0060]), the plurality of PIM controllers coupled to the host through a plurality of channels (see e.g., O FIG 5: CH1 and [0059]), and a plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels (see e.g., FIG 8: 500 and [0077]).
However, O does not expressly disclose but in the same field of endeavor Yu discloses
a host (see e.g., Yu FIG 2: 210) configured to receive an address including an identification (ID) from outside the PIM system (see e.g., Yu FIG 1: 110 and [0021]) and to output an address signal including a channel address corresponding to the identification (see Yu FIG 4: Channel Address and [0082]);
It would have been obvious before the effective filing date of the invention to modify O to implement a host to receive an identification and output a channel address as taught by Yu.
The suggestion/motivation for doing so would have been for the benefit of addressing from outside the PIM system (see Yu [0045]).
Therefore it would have been obvious before the effective filing date of the invention to modify O to receive an address including identification and output an address signal including a channel address as taught by Yu for the benefit of enabling outside access to arrive at the invention as specified in the claims.
As per claim 4, the PIM system of claim 1,
further comprising an interconnection bus coupled between the host and the plurality of PIM controllers (see O FIG 5: Databus).
As per claim 5, the PIM system of claim 4,
wherein the interconnection bus includes a plurality of channel terminals respectively coupled to the plurality of channels (see O FIG 2: 231 and [0045]).
As per claim 6, the PIM system of claim 5,
wherein the plurality of PIM controllers are respectively coupled to the plurality of channel terminals through the plurality of channels (see O FIG 5: PE 0, PE1 and [0045]).
As per claim 7, the PIM system of claim 6,
wherein the plurality of PIM devices are respectively coupled to the plurality of PIM controllers through the plurality of channels (see O FIG 5: CH1, CH2).
As per claim 8, the PIM system of claim 1,
wherein the plurality of PIM devices are configured to store arithmetic data used in the same type of arithmetic operation, and to perform the same type of arithmetic operation using the arithmetic data (see O [0033]: “neural network operations”).
As per claim 9, the PIM system of claim 1,
wherein the plurality of PIM devices are configured to store arithmetic data used in different types of arithmetic operations, and to perform the different types of arithmetic operations using the arithmetic data (see O [0084]: “data and a weight”).
As per claim 10, the PIM system of claim 1,
wherein among the plurality of PIM devices, a first PIM device coupled to a first PIM controller among the plurality of PIM controllers through a first channel is configured to perform an arithmetic operation in response to a command and address signal transmitted from the first PIM controller (see O [0034]).
As per claim 11, the PIM system of claim 1,
wherein the identification is received from a software domain (see Yu [0021]).
[The address is taken as an identification as recited in the claims, where the issuer is taken as a software domain to the extent a memory request is issued in response to executing software instructions.]
Claims 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over O (US PG PUB No. 2020/0294575) in view of Yu (US PG PUB No. 2022/0036929) as applied to claim 1 above and further in view of Madruga (US PG PUB No. 2009/0150575).
As per claim 3, O discloses the PIM system of claim 1,
However, O does not expressly disclose but in the same field of endeavor Madruga discloses
wherein the ID-channel mapper includes a table in which the identification and the plurality of channels are mapped to each other (see Madruga FIG 3: 300 and [0035]).
It would have been obvious before the effective filing date of the invention to modify O in view of Yu to further implement a channel bitmap as taught by Madruga.
The suggestion/motivation for doing so would have been for the benefit of a dynamic allocation (See Madruga [0006]).
Therefore it would have been obvious before the effective filing date of the invention to modify O in view of Yu to further include a table as taught by Madruga for the benefit of dynamic allocation to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
1st ARGUMENT:
Neither reference suggests modifying the O reference to include any ID-based channel mapping, nor is there any teaching or suggestion that sub-channel selection in DRAM of the Lee reference would be applicable to PIM routing at the host level as claimed.
Examiner notes Yu is relied upon to further teach addressing memory organized in channels using a channel mapper as recited in the claims. Examiner maintains a person of ordinary skill in the art would have found it obvious to manage access to memory organized in channels by outputting channel addressing as recited in the claims.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137